[AArch64] GAS Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15

2015-06-01 Jiong.Wang <jiong.wang@arm.com>

bfd/
  * reloc.c (BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15): New entry.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
  BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers.
  (md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.
  (aarch64_force_relocation): Ditto.

gas/testsuite/
  * gas/aarch64/reloc-insn.s: New testcase.
  * gas/aarch64/reloc-insn.d: Ditto.

bfd/ChangeLog

@@ -1,3 +1,11 @@
+2015-06-01  Jiong Wang  <jiong.wang@arm.com>
+
+	* reloc.c (BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15): New entry.
+	* bfd-in2.h: Regenerate.
+	* libbfd.h: Regenerate.
+	* elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
+	BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.
+
 2015-05-28  Catherine Moore  <clm@codesourcery.com>
 	    Bernd Schmidt <bernds@codesourcery.com>
 	    Paul Brook <paul@codesourcery.com>

bfd/bfd-in2.h

@@ -5737,6 +5737,9 @@ the GOT entry for this symbol.  Used in conjunction with
 BFD_RELOC_AARCH64_ADR_GOTPAGE.  Valid in ILP32 ABI only.  */
   BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
 
+/* Scaled 15 bit byte offset to the page base of the global offset table.  */
+  BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15,
+
 /* Get to the page base of the global offset table entry for a symbols
 tls_index structure as part of an adrp instruction using a 21 bit PC
 relative value.  Used in conjunction with

bfd/elfnn-aarch64.c

@@ -848,6 +848,22 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
 	 0xffc,			/* dst_mask */
 	 FALSE),		/* pcrel_offset */
 
+  /* LD64: GOT offset to the page address of GOT table.
+     (G(S) - PAGE (_GLOBAL_OFFSET_TABLE_)) & 0x7ff8.  */
+  HOWTO64 (AARCH64_R (LD64_GOTPAGE_LO15),	/* type */
+	 3,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 12,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_unsigned,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 AARCH64_R_STR (LD64_GOTPAGE_LO15),	/* name */
+	 FALSE,			/* partial_inplace */
+	 0x7ff8,		/* src_mask */
+	 0x7ff8,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
   /* Get to the page for the GOT entry for the symbol
      (G(S) - P) using an ADRP instruction.  */
   HOWTO (AARCH64_R (TLSGD_ADR_PAGE21),	/* type */

bfd/libbfd.h

@@ -2733,6 +2733,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_AARCH64_ADR_GOT_PAGE",
   "BFD_RELOC_AARCH64_LD64_GOT_LO12_NC",
   "BFD_RELOC_AARCH64_LD32_GOT_LO12_NC",
+  "BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15",
   "BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21",
   "BFD_RELOC_AARCH64_TLSGD_ADR_PREL21",
   "BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC",

bfd/reloc.c

@@ -6761,6 +6761,10 @@ ENUMDOC
   Unsigned 12 bit byte offset for 32 bit load/store from the page of
   the GOT entry for this symbol.  Used in conjunction with
   BFD_RELOC_AARCH64_ADR_GOTPAGE.  Valid in ILP32 ABI only.
+ENUM
+  BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
+ENUMDOC
+  Scaled 15 bit byte offset to the page base of the global offset table.
 ENUM
   BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
 ENUMDOC

gas/ChangeLog

@@ -1,3 +1,9 @@
+2015-06-01  Jiong Wang  <jiong.wang@arm.com>
+
+	* config/tc-aarch64.c (reloc_table): New relocation modifiers.
+	(md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.
+	(aarch64_force_relocation): Ditto.
+
 2015-05-28  Catherine Moore  <clm@codesourcery.com>
             Bernd Schmidt <bernds@codesourcery.com>
             Paul Brook <paul@codesourcery.com>

gas/config/tc-aarch64.c

@@ -2589,6 +2589,15 @@ static struct reloc_table_entry reloc_table[] = {
    0,
    0,
    0},
+
+  /* 15bit offset from got entry to base address of GOT table.  */
+  {"gotpage_lo15", 0,
+   0,
+   0,
+   0,
+   0,
+   BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15,
+   0},
 };
 
 /* Given the address of a pointer pointing to the textual name of a
@@ -6758,6 +6767,7 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
     case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
     case BFD_RELOC_AARCH64_GOT_LD_PREL19:
     case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
+    case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
     case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
     case BFD_RELOC_AARCH64_LDST128_LO12:
     case BFD_RELOC_AARCH64_LDST16_LO12:
@@ -6911,6 +6921,7 @@ aarch64_force_relocation (struct fix *fixp)
     case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
     case BFD_RELOC_AARCH64_GOT_LD_PREL19:
     case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
+    case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
     case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
     case BFD_RELOC_AARCH64_LDST128_LO12:
     case BFD_RELOC_AARCH64_LDST16_LO12:

gas/testsuite/ChangeLog

@@ -1,3 +1,8 @@
+2015-06-01  Jiong Wang  <jiong.wang@arm.com>
+
+	* gas/aarch64/reloc-insn.s: New testcase.
+	* gas/aarch64/reloc-insn.d: Ditto.
+
 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 
 	* gas/i386/avx512f.s: Adjust operand order for Intel syntax

gas/testsuite/gas/aarch64/reloc-insn.d

@@ -37,12 +37,12 @@ Disassembly of section \.text:
   5c:	f2d75301 	movk	x1, #0xba98, lsl #32
   60:	f2aeca81 	movk	x1, #0x7654, lsl #16
   64:	f2864201 	movk	x1, #0x3210
-  68:	58000960 	ldr	x0, 194 <llit>
+  68:	58000980 	ldr	x0, 198 <llit>
   6c:	58000001 	ldr	x1, 0 <func>
 			6c: R_AARCH64_LD_PREL_LO19	\.data\+0x8
   70:	58000002 	ldr	x2, 0 <xdata>
 			70: R_AARCH64_LD_PREL_LO19	xdata\+0xc
-  74:	10000900 	adr	x0, 194 <llit>
+  74:	10000920 	adr	x0, 198 <llit>
   78:	10000001 	adr	x1, 0 <func>
 			78: R_AARCH64_ADR_PREL_LO21	\.data\+0x8
   7c:	10000002 	adr	x2, 0 <func>
@@ -54,7 +54,7 @@ Disassembly of section \.text:
   88:	10000005 	adr	x5, 0 <xdata>
 			88: R_AARCH64_ADR_PREL_LO21	xdata\+0xff8
   8c:	90000000 	adrp	x0, 0 <func>
-			8c: R_AARCH64_ADR_PREL_PG_HI21	\.text\+0x194
+			8c: R_AARCH64_ADR_PREL_PG_HI21	\.text\+0x198
   90:	90000001 	adrp	x1, 0 <func>
 			90: R_AARCH64_ADR_PREL_PG_HI21	\.data\+0x8
   94:	90000002 	adrp	x2, 0 <func>
@@ -66,7 +66,7 @@ Disassembly of section \.text:
   a0:	90000005 	adrp	x5, 0 <xdata>
 			a0: R_AARCH64_ADR_PREL_PG_HI21	xdata\+0xff8
   a4:	90000000 	adrp	x0, 0 <func>
-			a4: R_AARCH64_ADR_PREL_PG_HI21	\.text\+0x194
+			a4: R_AARCH64_ADR_PREL_PG_HI21	\.text\+0x198
   a8:	90000001 	adrp	x1, 0 <func>
 			a8: R_AARCH64_ADR_PREL_PG_HI21	\.data\+0x8
   ac:	90000002 	adrp	x2, 0 <func>
@@ -78,7 +78,7 @@ Disassembly of section \.text:
   b8:	90000005 	adrp	x5, 0 <xdata>
 			b8: R_AARCH64_ADR_PREL_PG_HI21	xdata\+0xff8
   bc:	91000000 	add	x0, x0, #0x0
-			bc: R_AARCH64_ADD_ABS_LO12_NC	\.text\+0x194
+			bc: R_AARCH64_ADD_ABS_LO12_NC	\.text\+0x198
   c0:	91000021 	add	x1, x1, #0x0
 			c0: R_AARCH64_ADD_ABS_LO12_NC	\.data\+0x8
   c4:	91000042 	add	x2, x2, #0x0
@@ -91,7 +91,7 @@ Disassembly of section \.text:
 			d0: R_AARCH64_ADD_ABS_LO12_NC	xdata\+0xff8
   d4:	913ffcc6 	add	x6, x6, #0xfff
   d8:	39400000 	ldrb	w0, \[x0\]
-			d8: R_AARCH64_LDST8_ABS_LO12_NC	\.text\+0x194
+			d8: R_AARCH64_LDST8_ABS_LO12_NC	\.text\+0x198
   dc:	39400021 	ldrb	w1, \[x1\]
 			dc: R_AARCH64_LDST8_ABS_LO12_NC	\.data\+0x8
   e0:	39400042 	ldrb	w2, \[x2\]
@@ -103,22 +103,22 @@ Disassembly of section \.text:
   ec:	394000a5 	ldrb	w5, \[x5\]
 			ec: R_AARCH64_LDST8_ABS_LO12_NC	xdata\+0xff8
   f0:	397ffcc6 	ldrb	w6, \[x6,#4095\]
-  f4:	36000520 	tbz	w0, #0, 198 <lab>
+  f4:	36000540 	tbz	w0, #0, 19c <lab>
   f8:	b6f80001 	tbz	x1, #63, 0 <xlab>
 			f8: R_AARCH64_TSTBR14	xlab
-  fc:	374004e2 	tbnz	w2, #8, 198 <lab>
+  fc:	37400502 	tbnz	w2, #8, 19c <lab>
  100:	b7780002 	tbnz	x2, #47, 0 <xlab>
 			100: R_AARCH64_TSTBR14	xlab
- 104:	540004a0 	b\.eq	198 <lab>
+ 104:	540004c0 	b\.eq	19c <lab>
  108:	54000000 	b\.eq	0 <xlab>
 			108: R_AARCH64_CONDBR19	xlab
- 10c:	b4000460 	cbz	x0, 198 <lab>
+ 10c:	b4000480 	cbz	x0, 19c <lab>
  110:	b500001e 	cbnz	x30, 0 <xlab>
 			110: R_AARCH64_CONDBR19	xlab
- 114:	14000021 	b	198 <lab>
+ 114:	14000022 	b	19c <lab>
  118:	14000000 	b	0 <xlab>
 			118: R_AARCH64_JUMP26	xlab
- 11c:	9400001f 	bl	198 <lab>
+ 11c:	94000020 	bl	19c <lab>
  120:	94000000 	bl	0 <xlab>
 			120: R_AARCH64_CALL26	xlab
  124:	d2e24680 	mov	x0, #0x1234000000000000    	// #1311673391471656960
@@ -142,7 +142,7 @@ Disassembly of section \.text:
  16c:	f8500020 	ldur	x0, \[x1,#-256\]
  170:	f97ffc20 	ldr	x0, \[x1,#32760\]
  174:	79400000 	ldrh	w0, \[x0\]
-			174: R_AARCH64_LDST16_ABS_LO12_NC	\.text\+0x194
+			174: R_AARCH64_LDST16_ABS_LO12_NC	\.text\+0x198
  178:	b9400021 	ldr	w1, \[x1\]
 			178: R_AARCH64_LDST32_ABS_LO12_NC	\.data\+0x8
  17c:	f9400042 	ldr	x2, \[x2\]
@@ -155,6 +155,8 @@ Disassembly of section \.text:
 			188: R_AARCH64_GOT_LD_PREL19	cdata
  18c:	39400001 	ldrb	w1, \[x0\]
  190:	d65f03c0 	ret
+ 194:	f94001bc 	ldr	x28, \[x13\]
+			194: R_AARCH64_LD64_GOTPAGE_LO15	\.data
 
-0000000000000194 <llit>:
+0000000000000198 <llit>:
- 194:	deadf00d 	\.word	0xdeadf00d
+ 198:	deadf00d 	\.word	0xdeadf00d

gas/testsuite/gas/aarch64/reloc-insn.s

@@ -183,6 +183,9 @@ func:
 	
 	ret
 	
+	// BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
+	ldr	x28, [x13, #:gotpage_lo15:dummy]
+
 llit:	.word	0xdeadf00d
 	
 lab: