* gas/mips/mips32.s: Move out coprocessor2 insns from here ...
* gas/mips/mips32-cp2.s: ... to here. * gas/mips/mips32.d: Update. * gas/mips/mips32-cp2.d: New file. * gas/mips/mips32r2.s: Move out coprocessor2 insns from here ... * gas/mips/mips32r2-cp2.s: ... to here. * gas/mips/mips32r2.d: Update. * gas/mips/mips32r2-cp2.d: New file. * gas/mips/mips64.s: Move out coprocessor2 insns from here ... * gas/mips/mips64-cp2.s: ... to here. * gas/mips/mips64.d: Update. * gas/mips/mips64-cp2.d: New file. * gas/mips/mips.exp: Run mips32-cp2, mips32r2-cp2 and mips64-cp except for Octeon. * gas/mips/octeon.s: Add supported coprocessor insns. Move pop down to keep alphabetical order. * gas/mips/octeon.d: Update. * gas/mips/octeon-ill.s: Add unsupported coprocessor insns. * gas/mips/octeon-ill.l: Update.
This commit is contained in:
Adam Nemet
parent
b19e8a9bae
commit
a6d8f55bfd
18 changed files with 286 additions and 127 deletions
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@ -1,3 +1,25 @@
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2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
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* gas/mips/mips32.s: Move out coprocessor2 insns from here ...
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* gas/mips/mips32-cp2.s: ... to here.
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* gas/mips/mips32.d: Update.
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* gas/mips/mips32-cp2.d: New file.
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* gas/mips/mips32r2.s: Move out coprocessor2 insns from here ...
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* gas/mips/mips32r2-cp2.s: ... to here.
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* gas/mips/mips32r2.d: Update.
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* gas/mips/mips32r2-cp2.d: New file.
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* gas/mips/mips64.s: Move out coprocessor2 insns from here ...
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* gas/mips/mips64-cp2.s: ... to here.
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* gas/mips/mips64.d: Update.
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* gas/mips/mips64-cp2.d: New file.
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* gas/mips/mips.exp: Run mips32-cp2, mips32r2-cp2 and mips64-cp
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except for Octeon.
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* gas/mips/octeon.s: Add supported coprocessor insns. Move pop
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down to keep alphabetical order.
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* gas/mips/octeon.d: Update.
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* gas/mips/octeon-ill.s: Add unsupported coprocessor insns.
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* gas/mips/octeon-ill.l: Update.
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2008-07-07 Paul Brook <paul@codesourcery.com>
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* gas/arm/movw-local.d: New test.
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@ -552,8 +552,12 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test_arches "mips32-sf32" [mips_arch_list_matching mips32]
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run_list_test_arches "mips32-sf32" "-32 -msoft-float" \
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[mips_arch_list_matching mips32]
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run_dump_test_arches "mips32-cp2" [mips_arch_list_matching mips32 \
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!octeon]
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run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2]
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run_dump_test_arches "mips32r2-cp2" [mips_arch_list_matching mips32r2 \
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!octeon]
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run_dump_test_arches "mips32r2-fp32" \
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[mips_arch_list_matching mips32r2]
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run_list_test_arches "mips32r2-fp32" "-32 -msoft-float" \
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@ -566,6 +570,8 @@ if { [istarget mips*-*-vxworks*] } {
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[mips_arch_list_matching mips32r2]
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run_dump_test_arches "mips64" [mips_arch_list_matching mips64]
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run_dump_test_arches "mips64-cp2" [mips_arch_list_matching mips64 \
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!octeon]
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run_dump_test_arches "mips64r2" [mips_arch_list_matching mips64r2]
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run_list_test_arches "mips64r2-ill" "" [mips_arch_list_matching mips64r2]
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35
gas/testsuite/gas/mips/mips32-cp2.d
Normal file
35
gas/testsuite/gas/mips/mips32-cp2.d
Normal file
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@ -0,0 +1,35 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MIPS MIPS32 cop2 instructions
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#as: -32
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# Check MIPS32 cop2 instruction assembly
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> 4900ffff bc2f 0+0000 <text_label>
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0+0004 <[^>]*> 00000000 nop
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0+0008 <[^>]*> 4902fffd bc2fl 0+0000 <text_label>
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0+000c <[^>]*> 00000000 nop
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0+0010 <[^>]*> 4901fffb bc2t 0+0000 <text_label>
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0+0014 <[^>]*> 00000000 nop
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0+0018 <[^>]*> 4903fff9 bc2tl 0+0000 <text_label>
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0+001c <[^>]*> 00000000 nop
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0+0020 <[^>]*> 48411000 cfc2 at,\$2
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0+0024 <[^>]*> 4b234567 c2 0x1234567
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0+0028 <[^>]*> 48c21800 ctc2 v0,\$3
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0+002c <[^>]*> 48032000 mfc2 v1,\$4
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0+0030 <[^>]*> 48042800 mfc2 a0,\$5
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0+0034 <[^>]*> 48053007 mfc2 a1,\$6,7
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0+0038 <[^>]*> 48863800 mtc2 a2,\$7
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0+003c <[^>]*> 48874000 mtc2 a3,\$8
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0+0040 <[^>]*> 48884807 mtc2 t0,\$9,7
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0+0044 <[^>]*> 4900ffee bc2f 0+0000 <text_label>
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0+0048 <[^>]*> 00000000 nop
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0+004c <[^>]*> 4906ffec bc2fl \$cc1,0+0000 <text_label>
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0+0050 <[^>]*> 00000000 nop
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0+0054 <[^>]*> 4919ffea bc2t \$cc6,0+0000 <text_label>
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0+0058 <[^>]*> 00000000 nop
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0+005c <[^>]*> 491fffe8 bc2tl \$cc7,0+0000 <text_label>
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0+0060 <[^>]*> 00000000 nop
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#pass
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39
gas/testsuite/gas/mips/mips32-cp2.s
Normal file
39
gas/testsuite/gas/mips/mips32-cp2.s
Normal file
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@ -0,0 +1,39 @@
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# source file to test assembly of mips32 cop2 instructions
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.set noreorder
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.set noat
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.text
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text_label:
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# unprivileged coprocessor instructions.
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# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
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bc2f text_label
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nop
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bc2fl text_label
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nop
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bc2t text_label
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nop
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bc2tl text_label
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nop
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# XXX other BCzCond encodings not currently expressable
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cfc2 $1, $2
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cop2 0x1234567 # disassembles as c2 ...
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ctc2 $2, $3
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mfc2 $3, $4
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mfc2 $4, $5, 0 # disassembles without sel
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mfc2 $5, $6, 7
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mtc2 $6, $7
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mtc2 $7, $8, 0 # disassembles without sel
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mtc2 $8, $9, 7
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# Cop2 branches with cond code number, like bc1t/f
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bc2f $cc0,text_label
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nop
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bc2fl $cc1,text_label
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nop
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bc2t $cc6,text_label
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nop
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bc2tl $cc7,text_label
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nop
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@ -18,57 +18,32 @@ Disassembly of section .text:
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0+0020 <[^>]*> ce247fff pref 0x4,32767\(s1\)
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0+0024 <[^>]*> ce448000 pref 0x4,-32768\(s2\)
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0+0028 <[^>]*> 00000040 ssnop
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0+002c <[^>]*> 4900fff4 bc2f 0+0000 <text_label>
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0+0030 <[^>]*> 00000000 nop
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0+0034 <[^>]*> 4902fff2 bc2fl 0+0000 <text_label>
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0+0038 <[^>]*> 00000000 nop
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0+003c <[^>]*> 4901fff0 bc2t 0+0000 <text_label>
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0+0040 <[^>]*> 00000000 nop
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0+0044 <[^>]*> 4903ffee bc2tl 0+0000 <text_label>
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0+0048 <[^>]*> 00000000 nop
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0+004c <[^>]*> 48411000 cfc2 at,\$2
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0+0050 <[^>]*> 4b234567 c2 0x1234567
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0+0054 <[^>]*> 48c21800 ctc2 v0,\$3
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0+0058 <[^>]*> 48032000 mfc2 v1,\$4
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0+005c <[^>]*> 48042800 mfc2 a0,\$5
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0+0060 <[^>]*> 48053007 mfc2 a1,\$6,7
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0+0064 <[^>]*> 48863800 mtc2 a2,\$7
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0+0068 <[^>]*> 48874000 mtc2 a3,\$8
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0+006c <[^>]*> 48884807 mtc2 t0,\$9,7
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0+0070 <[^>]*> bc250000 cache 0x5,0\(at\)
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0+0074 <[^>]*> bc457fff cache 0x5,32767\(v0\)
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0+0078 <[^>]*> bc658000 cache 0x5,-32768\(v1\)
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0+007c <[^>]*> 3c010001 lui at,0x1
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0+0080 <[^>]*> 00240821 addu at,at,a0
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0+0084 <[^>]*> bc258000 cache 0x5,-32768\(at\)
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0+0088 <[^>]*> 3c01ffff lui at,0xffff
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0+008c <[^>]*> 00250821 addu at,at,a1
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0+0090 <[^>]*> bc257fff cache 0x5,32767\(at\)
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0+0094 <[^>]*> 3c010001 lui at,0x1
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0+0098 <[^>]*> bc258000 cache 0x5,-32768\(at\)
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0+009c <[^>]*> 3c01ffff lui at,0xffff
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0+00a0 <[^>]*> bc257fff cache 0x5,32767\(at\)
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0+00a4 <[^>]*> 42000018 eret
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0+00a8 <[^>]*> 42000008 tlbp
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0+00ac <[^>]*> 42000001 tlbr
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0+00b0 <[^>]*> 42000002 tlbwi
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0+00b4 <[^>]*> 42000006 tlbwr
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0+00b8 <[^>]*> 42000020 wait
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0+00bc <[^>]*> 42000020 wait
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0+00c0 <[^>]*> 4359e260 wait 0x56789
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0+00c4 <[^>]*> 0000000d break
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0+00c8 <[^>]*> 0000000d break
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0+00cc <[^>]*> 0345000d break 0x345
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0+00d0 <[^>]*> 0048d14d break 0x48,0x345
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0+00d4 <[^>]*> 7000003f sdbbp
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0+00d8 <[^>]*> 7000003f sdbbp
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0+00dc <[^>]*> 7159e27f sdbbp 0x56789
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0+00e0 <[^>]*> 4900ffc7 bc2f 0+0000 <text_label>
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0+00e4 <[^>]*> 00000000 nop
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0+00e8 <[^>]*> 4906ffc5 bc2fl \$cc1,0+0000 <text_label>
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0+00ec <[^>]*> 00000000 nop
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0+00f0 <[^>]*> 4919ffc3 bc2t \$cc6,0+0000 <text_label>
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0+00f4 <[^>]*> 00000000 nop
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0+00f8 <[^>]*> 491fffc1 bc2tl \$cc7,0+0000 <text_label>
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0+00fc <[^>]*> 00000000 nop
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0+002c <[^>]*> bc250000 cache 0x5,0\(at\)
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0+0030 <[^>]*> bc457fff cache 0x5,32767\(v0\)
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0+0034 <[^>]*> bc658000 cache 0x5,-32768\(v1\)
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0+0038 <[^>]*> 3c010001 lui at,0x1
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0+003c <[^>]*> 00240821 addu at,at,a0
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0+0040 <[^>]*> bc258000 cache 0x5,-32768\(at\)
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0+0044 <[^>]*> 3c01ffff lui at,0xffff
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0+0048 <[^>]*> 00250821 addu at,at,a1
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0+004c <[^>]*> bc257fff cache 0x5,32767\(at\)
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0+0050 <[^>]*> 3c010001 lui at,0x1
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0+0054 <[^>]*> bc258000 cache 0x5,-32768\(at\)
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0+0058 <[^>]*> 3c01ffff lui at,0xffff
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0+005c <[^>]*> bc257fff cache 0x5,32767\(at\)
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0+0060 <[^>]*> 42000018 eret
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0+0064 <[^>]*> 42000008 tlbp
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0+0068 <[^>]*> 42000001 tlbr
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0+006c <[^>]*> 42000002 tlbwi
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0+0070 <[^>]*> 42000006 tlbwr
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0+0074 <[^>]*> 42000020 wait
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0+0078 <[^>]*> 42000020 wait
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0+007c <[^>]*> 4359e260 wait 0x56789
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0+0080 <[^>]*> 0000000d break
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0+0084 <[^>]*> 0000000d break
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0+0088 <[^>]*> 0345000d break 0x345
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0+008c <[^>]*> 0048d14d break 0x48,0x345
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0+0090 <[^>]*> 7000003f sdbbp
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0+0094 <[^>]*> 7000003f sdbbp
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0+0098 <[^>]*> 7159e27f sdbbp 0x56789
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\.\.\.
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@ -21,29 +21,6 @@ text_label:
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ssnop
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# unprivileged coprocessor instructions.
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# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
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bc2f text_label
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nop
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bc2fl text_label
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nop
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bc2t text_label
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nop
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bc2tl text_label
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nop
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# XXX other BCzCond encodings not currently expressable
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cfc2 $1, $2
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cop2 0x1234567 # disassembles as c2 ...
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ctc2 $2, $3
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mfc2 $3, $4
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mfc2 $4, $5, 0 # disassembles without sel
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mfc2 $5, $6, 7
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mtc2 $6, $7
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mtc2 $7, $8, 0 # disassembles without sel
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mtc2 $8, $9, 7
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# privileged instructions
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cache 5, ($1)
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@ -79,15 +56,5 @@ text_label:
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sdbbp 0 # disassembles without code
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sdbbp 0x56789
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# Cop2 branches with cond code number, like bc1t/f
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bc2f $cc0,text_label
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nop
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bc2fl $cc1,text_label
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nop
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bc2t $cc6,text_label
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nop
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bc2tl $cc7,text_label
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nop
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.space 8
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12
gas/testsuite/gas/mips/mips32r2-cp2.d
Normal file
12
gas/testsuite/gas/mips/mips32r2-cp2.d
Normal file
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@ -0,0 +1,12 @@
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#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
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#name: MIPS MIPS32r2 cop2 instructions
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#as: -32
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# Check MIPS32 Release 2 (mips32r2) cop2 instruction assembly
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> 48715555 mfhc2 \$17,0x5555
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0+0004 <[^>]*> 48f15555 mthc2 \$17,0x5555
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#pass
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12
gas/testsuite/gas/mips/mips32r2-cp2.s
Normal file
12
gas/testsuite/gas/mips/mips32r2-cp2.s
Normal file
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@ -0,0 +1,12 @@
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# source file to test assembly of mips32r2 cop2 instructions
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.set noreorder
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.set noat
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.text
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text_label:
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# cp2 instructions
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mfhc2 $17, 0x5555
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mthc2 $17, 0x5555
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@ -40,6 +40,4 @@ Disassembly of section .text:
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0+0078 <[^>]*> 416a6020 ei \$10
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0+007c <[^>]*> 41595000 rdpgpr \$10,\$25
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0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25
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0+0084 <[^>]*> 48715555 mfhc2 \$17,0x5555
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0+0088 <[^>]*> 48f15555 mthc2 \$17,0x5555
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...
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@ -63,10 +63,5 @@ text_label:
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wrpgpr $10, $25
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# cp2 instructions
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mfhc2 $17, 0x5555
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mthc2 $17, 0x5555
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.space 8
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16
gas/testsuite/gas/mips/mips64-cp2.d
Normal file
16
gas/testsuite/gas/mips/mips64-cp2.d
Normal file
|
|
@ -0,0 +1,16 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MIPS MIPS64 cop2 instructions
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#as: -32
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# Check MIPS64 cop2 instruction assembly
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> 48232000 dmfc2 v1,\$4
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0+0004 <[^>]*> 48242800 dmfc2 a0,\$5
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0+0008 <[^>]*> 48253007 dmfc2 a1,\$6,7
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0+000c <[^>]*> 48a63800 dmtc2 a2,\$7
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0+0010 <[^>]*> 48a74000 dmtc2 a3,\$8
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0+0014 <[^>]*> 48a84807 dmtc2 t0,\$9,7
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#pass
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17
gas/testsuite/gas/mips/mips64-cp2.s
Normal file
17
gas/testsuite/gas/mips/mips64-cp2.s
Normal file
|
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@ -0,0 +1,17 @@
|
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# source file to test assembly of mips64 cop2 instructions
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.set noreorder
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.set noat
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.globl text_label .text
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text_label:
|
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|
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# unprivileged coprocessor instructions.
|
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# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
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dmfc2 $3, $4
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dmfc2 $4, $5, 0 # disassembles without sel
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dmfc2 $5, $6, 7
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dmtc2 $6, $7
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dmtc2 $7, $8, 0 # disassembles without sel
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dmtc2 $8, $9, 7
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@ -9,9 +9,4 @@
|
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Disassembly of section .text:
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||||
0+0000 <[^>]*> 70410825 dclo at,v0
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0+0004 <[^>]*> 70831824 dclz v1,a0
|
||||
0+0008 <[^>]*> 48232000 dmfc2 v1,\$4
|
||||
0+000c <[^>]*> 48242800 dmfc2 a0,\$5
|
||||
0+0010 <[^>]*> 48253007 dmfc2 a1,\$6,7
|
||||
0+0014 <[^>]*> 48a63800 dmtc2 a2,\$7
|
||||
0+0018 <[^>]*> 48a74000 dmtc2 a3,\$8
|
||||
0+001c <[^>]*> 48a84807 dmtc2 t0,\$9,7
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -10,13 +10,3 @@ text_label:
|
|||
|
||||
dclo $1, $2
|
||||
dclz $3, $4
|
||||
|
||||
# unprivileged coprocessor instructions.
|
||||
# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
|
||||
|
||||
dmfc2 $3, $4
|
||||
dmfc2 $4, $5, 0 # disassembles without sel
|
||||
dmfc2 $5, $6, 7
|
||||
dmtc2 $6, $7
|
||||
dmtc2 $7, $8, 0 # disassembles without sel
|
||||
dmtc2 $8, $9, 7
|
||||
|
|
|
|||
|
|
@ -8,12 +8,38 @@
|
|||
.*:18: Error: Improper size \(25\)
|
||||
.*:20: Error: Improper position \(64\)
|
||||
.*:21: Error: Improper size \(14\)
|
||||
.*:23: Error: Improper size \(32\)
|
||||
.*:25: Error: Improper position \(32\)
|
||||
.*:26: Error: Improper size \(29\)
|
||||
.*:28: Error: Improper position \(70\)
|
||||
.*:29: Error: Improper size \(25\)
|
||||
.*:31: Error: Improper immediate \(512\)
|
||||
.*:32: Error: Improper immediate \(-771\)
|
||||
.*:33: Error: Improper immediate \(615\)
|
||||
.*:34: Error: Improper immediate \(-513\)
|
||||
.*:23: Error: opcode not supported on this processor.*
|
||||
.*:24: Error: opcode not supported on this processor.*
|
||||
.*:25: Error: opcode not supported on this processor.*
|
||||
.*:26: Error: opcode not supported on this processor.*
|
||||
.*:27: Error: opcode not supported on this processor.*
|
||||
.*:28: Error: opcode not supported on this processor.*
|
||||
.*:29: Error: opcode not supported on this processor.*
|
||||
.*:30: Error: opcode not supported on this processor.*
|
||||
.*:31: Error: opcode not supported on this processor.*
|
||||
.*:32: Error: opcode not supported on this processor.*
|
||||
.*:33: Error: opcode not supported on this processor.*
|
||||
.*:34: Error: opcode not supported on this processor.*
|
||||
.*:35: Error: opcode not supported on this processor.*
|
||||
.*:36: Error: opcode not supported on this processor.*
|
||||
.*:37: Error: opcode not supported on this processor.*
|
||||
.*:39: Error: opcode not supported on this processor.*
|
||||
.*:40: Error: opcode not supported on this processor.*
|
||||
.*:41: Error: opcode not supported on this processor.*
|
||||
.*:42: Error: opcode not supported on this processor.*
|
||||
.*:43: Error: opcode not supported on this processor.*
|
||||
.*:45: Error: expression out of range
|
||||
.*:46: Error: expression out of range
|
||||
.*:47: Error: register value used as expression
|
||||
.*:48: Error: illegal operands `dmfc2'
|
||||
.*:49: Error: register value used as expression
|
||||
.*:50: Error: illegal operands `dmtc2'
|
||||
.*:52: Error: Improper size \(32\)
|
||||
.*:54: Error: Improper position \(32\)
|
||||
.*:55: Error: Improper size \(29\)
|
||||
.*:57: Error: Improper position \(70\)
|
||||
.*:58: Error: Improper size \(25\)
|
||||
.*:60: Error: Improper immediate \(512\)
|
||||
.*:61: Error: Improper immediate \(-771\)
|
||||
.*:62: Error: Improper immediate \(615\)
|
||||
.*:63: Error: Improper immediate \(-513\)
|
||||
|
|
|
|||
|
|
@ -20,6 +20,35 @@ foo:
|
|||
cins $24,$10,64,8
|
||||
cins $21,$30,50,14
|
||||
|
||||
c2 1
|
||||
bc2f foo
|
||||
bc2fl foo
|
||||
bc2t foo
|
||||
bc2tl foo
|
||||
cfc2 $25,$12
|
||||
ctc2 $12,$2
|
||||
ldc2 $10,0($25)
|
||||
lwc2 $11,12($31)
|
||||
mfc2 $24,$1
|
||||
mfhc2 $17,$20
|
||||
mtc2 $2,$21
|
||||
mthc2 $13,$25
|
||||
sdc2 $22,8($4)
|
||||
swc2 $2,24($2)
|
||||
|
||||
cop2 23
|
||||
ldc2 $8,foo
|
||||
lwc2 $16,foo+4
|
||||
sdc2 $10,0x12345678
|
||||
swc2 $16,0x12345($15)
|
||||
|
||||
dmfc2 $2,0x10000
|
||||
dmtc2 $2,0x12345
|
||||
dmfc2 $9,$12
|
||||
dmfc2 $4,$15,4
|
||||
dmtc2 $16,$8
|
||||
dmtc2 $22,$7,$4
|
||||
|
||||
exts $26,26,32
|
||||
|
||||
exts32 $7,$21,32,10
|
||||
|
|
|
|||
|
|
@ -29,22 +29,34 @@ Disassembly of section .text:
|
|||
.*: 71ef2973 cins32 \$15,\$15,0x5,0x5
|
||||
.*: 731c9803 dmul \$19,\$24,\$28
|
||||
.*: 72b9a803 dmul \$21,\$21,\$25
|
||||
.*: 7260402c pop \$8,\$19
|
||||
.*: 7040102c pop \$2,\$2
|
||||
.*: 72c0782d dpop \$15,\$22
|
||||
.*: 7180602d dpop \$12,\$12
|
||||
.*: 73847efa exts \$4,\$28,0x1b,0xf
|
||||
.*: 71ef347a exts \$15,\$15,0x11,0x6
|
||||
.*: 71a442bb exts32 \$4,\$13,0xa,0x8
|
||||
.*: 71efa2fb exts32 \$15,\$15,0xb,0x14
|
||||
.*: 70874dbb exts32 \$7,\$4,0x16,0x9
|
||||
.*: 7339c97b exts32 \$25,\$25,0x5,0x19
|
||||
.*: 400dc800 mfc0 \$13,\$25
|
||||
.*: 400d5807 mfc0 \$13,\$11,7
|
||||
.*: 40861000 mtc0 \$6,\$2
|
||||
.*: 40954806 mtc0 \$21,\$9,6
|
||||
.*: 4023e800 dmfc0 \$3,\$29
|
||||
.*: 402ba005 dmfc0 \$11,\$20,5
|
||||
.*: 40b71000 dmtc0 \$23,\$2
|
||||
.*: 40a77002 dmtc0 \$7,\$14,2
|
||||
.*: 41606000 di
|
||||
.*: 41606020 ei
|
||||
.*: 48230084 dmfc2 \$3,0x84
|
||||
.*: 48a84200 dmtc2 \$8,0x4200
|
||||
.*: 73400008 mtm0 \$26
|
||||
.*: 7260000c mtm1 \$19
|
||||
.*: 7240000d mtm2 \$18
|
||||
.*: 72000009 mtp0 \$16
|
||||
.*: 7320000a mtp1 \$25
|
||||
.*: 7120000b mtp2 \$9
|
||||
.*: 7260402c pop \$8,\$19
|
||||
.*: 7040102c pop \$2,\$2
|
||||
.*: 72c0782d dpop \$15,\$22
|
||||
.*: 7180602d dpop \$12,\$12
|
||||
.*: 72f8e82a seq \$29,\$23,\$24
|
||||
.*: 70dc302a seq \$6,\$6,\$28
|
||||
.*: 71f1802e seqi \$17,\$15,-512
|
||||
|
|
|
|||
|
|
@ -29,11 +29,6 @@ foo:
|
|||
dmul $19,$24,$28
|
||||
dmul $21,$25
|
||||
|
||||
pop $8,$19
|
||||
pop $2
|
||||
dpop $15,$22
|
||||
dpop $12
|
||||
|
||||
exts $4,$28,27,15
|
||||
exts $15,17,6
|
||||
exts32 $4,$13,10,8
|
||||
|
|
@ -41,6 +36,19 @@ foo:
|
|||
exts $7,$4,54,9
|
||||
exts $25,37,25
|
||||
|
||||
mfc0 $13,$25
|
||||
mfc0 $13,$11,7
|
||||
mtc0 $6,$2
|
||||
mtc0 $21,$9,6
|
||||
dmfc0 $3,$29
|
||||
dmfc0 $11,$20,5
|
||||
dmtc0 $23,$2
|
||||
dmtc0 $7,$14,2
|
||||
di
|
||||
ei
|
||||
dmfc2 $3,0x84
|
||||
dmtc2 $8,0x4200
|
||||
|
||||
mtm0 $26
|
||||
mtm1 $19
|
||||
mtm2 $18
|
||||
|
|
@ -49,6 +57,11 @@ foo:
|
|||
mtp1 $25
|
||||
mtp2 $9
|
||||
|
||||
pop $8,$19
|
||||
pop $2
|
||||
dpop $15,$22
|
||||
dpop $12
|
||||
|
||||
seq $29,$23,$24
|
||||
seq $6,$28
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue