gas/
2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (allow_pseudo_reg): New. (parse_real_register): Check for NULL just once. Allow all register table entries when allow_pseudo_reg is non-zero. Don't allow any registers without type when allow_pseudo_reg is zero. (tc_x86_regname_to_dw2regnum): Replace with ... (tc_x86_parse_to_dw2regnum): ... this. (tc_x86_frame_initial_instructions): Adjust for above change. * config/tc-i386.h (tc_regname_to_dw2regnum): Remove. (tc_parse_to_dw2regnum): New. (tc_x86_regname_to_dw2regnum): Replace with ... (tc_x86_parse_to_dw2regnum): ... this. * dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ... (cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust error handling. gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/cfi/cfi-i386.s: Add code testing use of all registers. Fix a few comments. * gas/cfi/cfi-x86_64.s: Likewise. * gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-gen.c (process_i386_registers): Process new fields. * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to unsigned char. Add dw2_regnum and Dw2Inval. * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo register names. * i386-tbl.h: Re-generate.
This commit is contained in:
Jan Beulich
parent
36af4ef676
commit
a60de03c61
14 changed files with 958 additions and 437 deletions
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@ -1,3 +1,21 @@
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2008-02-13 Jan Beulich <jbeulich@novell.com>
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* config/tc-i386.c (allow_pseudo_reg): New.
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(parse_real_register): Check for NULL just once. Allow all
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register table entries when allow_pseudo_reg is non-zero.
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Don't allow any registers without type when allow_pseudo_reg
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is zero.
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(tc_x86_regname_to_dw2regnum): Replace with ...
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(tc_x86_parse_to_dw2regnum): ... this.
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(tc_x86_frame_initial_instructions): Adjust for above change.
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* config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
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(tc_parse_to_dw2regnum): New.
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(tc_x86_regname_to_dw2regnum): Replace with ...
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(tc_x86_parse_to_dw2regnum): ... this.
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* dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
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(cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
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error handling.
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2008-02-12 Nick Clifton <nickc@redhat.com>
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* config/tc-tic4x.c (tic4x_insn_insert): Add const qualifier to
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@ -413,6 +413,9 @@ static int intel_mnemonic = !SYSV386_COMPAT;
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/* 1 if support old (<= 2.8.1) versions of gcc. */
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static int old_gcc = OLDGCC_COMPAT;
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/* 1 if pseudo registers are permitted. */
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static int allow_pseudo_reg = 0;
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/* 1 if register prefix % not required. */
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static int allow_naked_reg = 0;
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@ -7055,15 +7058,19 @@ parse_real_register (char *reg_string, char **end_op)
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}
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}
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if (r == NULL || allow_pseudo_reg)
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return r;
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if (UINTS_ALL_ZERO (r->reg_type))
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return (const reg_entry *) NULL;
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/* Don't allow fake index register unless allow_index_reg isn't 0. */
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if (r != NULL
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&& !allow_index_reg
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if (!allow_index_reg
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&& (r->reg_num == RegEiz || r->reg_num == RegRiz))
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return (const reg_entry *) NULL;
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if (r != NULL
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&& ((r->reg_flags & (RegRex64 | RegRex))
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|| r->reg_type.bitfield.reg64)
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if (((r->reg_flags & (RegRex64 | RegRex))
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|| r->reg_type.bitfield.reg64)
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&& (!cpu_arch_flags.bitfield.cpulm
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|| !UINTS_EQUAL (r->reg_type, control))
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&& flag_code != CODE_64BIT)
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@ -9134,79 +9141,54 @@ intel_putback_token (void)
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prev_token.str = NULL;
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}
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int
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tc_x86_regname_to_dw2regnum (char *regname)
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void
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tc_x86_parse_to_dw2regnum (expressionS *exp)
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{
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unsigned int regnum;
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unsigned int regnames_count;
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static const char *const regnames_32[] =
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{
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"eax", "ecx", "edx", "ebx",
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"esp", "ebp", "esi", "edi",
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"eip", "eflags", NULL,
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"st0", "st1", "st2", "st3",
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"st4", "st5", "st6", "st7",
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NULL, NULL,
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"xmm0", "xmm1", "xmm2", "xmm3",
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"xmm4", "xmm5", "xmm6", "xmm7",
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"mm0", "mm1", "mm2", "mm3",
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"mm4", "mm5", "mm6", "mm7",
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"fcw", "fsw", "mxcsr",
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"es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
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"tr", "ldtr"
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};
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static const char *const regnames_64[] =
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{
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"rax", "rdx", "rcx", "rbx",
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"rsi", "rdi", "rbp", "rsp",
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"r8", "r9", "r10", "r11",
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"r12", "r13", "r14", "r15",
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"rip",
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"xmm0", "xmm1", "xmm2", "xmm3",
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"xmm4", "xmm5", "xmm6", "xmm7",
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"xmm8", "xmm9", "xmm10", "xmm11",
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"xmm12", "xmm13", "xmm14", "xmm15",
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"st0", "st1", "st2", "st3",
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"st4", "st5", "st6", "st7",
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"mm0", "mm1", "mm2", "mm3",
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"mm4", "mm5", "mm6", "mm7",
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"rflags",
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"es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
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"fs.base", "gs.base", NULL, NULL,
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"tr", "ldtr",
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"mxcsr", "fcw", "fsw"
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};
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const char *const *regnames;
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int saved_naked_reg;
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char saved_register_dot;
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if (flag_code == CODE_64BIT)
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saved_naked_reg = allow_naked_reg;
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allow_naked_reg = 1;
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saved_register_dot = register_chars['.'];
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register_chars['.'] = '.';
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allow_pseudo_reg = 1;
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expression_and_evaluate (exp);
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allow_pseudo_reg = 0;
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register_chars['.'] = saved_register_dot;
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allow_naked_reg = saved_naked_reg;
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if (exp->X_op == O_register && exp->X_add_number >= 0)
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{
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regnames = regnames_64;
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regnames_count = ARRAY_SIZE (regnames_64);
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if ((addressT) exp->X_add_number < i386_regtab_size)
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{
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exp->X_op = O_constant;
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exp->X_add_number = i386_regtab[exp->X_add_number]
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.dw2_regnum[flag_code >> 1];
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}
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else
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exp->X_op = O_illegal;
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}
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else
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{
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regnames = regnames_32;
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regnames_count = ARRAY_SIZE (regnames_32);
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}
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for (regnum = 0; regnum < regnames_count; regnum++)
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if (regnames[regnum] != NULL
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&& strcmp (regname, regnames[regnum]) == 0)
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return regnum;
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return -1;
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}
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void
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tc_x86_frame_initial_instructions (void)
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{
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static unsigned int sp_regno;
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static unsigned int sp_regno[2];
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if (!sp_regno)
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sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
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? "rsp" : "esp");
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if (!sp_regno[flag_code >> 1])
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{
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char *saved_input = input_line_pointer;
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char sp[][4] = {"esp", "rsp"};
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expressionS exp;
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cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
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input_line_pointer = sp[flag_code >> 1];
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tc_x86_parse_to_dw2regnum (&exp);
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assert (exp.X_op == O_constant);
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sp_regno[flag_code >> 1] = exp.X_add_number;
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input_line_pointer = saved_input;
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}
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cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
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cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
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}
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@ -203,8 +203,8 @@ extern unsigned int x86_dwarf2_return_column;
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extern int x86_cie_data_alignment;
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#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
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#define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
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extern int tc_x86_regname_to_dw2regnum (char *);
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#define tc_parse_to_dw2regnum tc_x86_parse_to_dw2regnum
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extern void tc_x86_parse_to_dw2regnum (expressionS *);
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#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
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extern void tc_x86_frame_initial_instructions (void);
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@ -400,13 +400,11 @@ cfi_parse_separator (void)
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as_bad (_("missing separator"));
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}
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static unsigned
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cfi_parse_reg (void)
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#ifndef tc_parse_to_dw2regnum
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static void
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tc_parse_to_dw2regnum(expressionS *exp)
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{
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int regno;
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expressionS exp;
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#ifdef tc_regname_to_dw2regnum
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# ifdef tc_regname_to_dw2regnum
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SKIP_WHITESPACE ();
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if (is_name_beginner (*input_line_pointer)
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|| (*input_line_pointer == '%'
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@ -417,18 +415,24 @@ cfi_parse_reg (void)
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name = input_line_pointer;
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c = get_symbol_end ();
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if ((regno = tc_regname_to_dw2regnum (name)) < 0)
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{
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as_bad (_("bad register expression"));
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regno = 0;
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}
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exp->X_op = O_constant;
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exp->X_add_number = tc_regname_to_dw2regnum (name);
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*input_line_pointer = c;
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return regno;
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}
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else
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# endif
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expression_and_evaluate (exp);
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}
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#endif
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expression_and_evaluate (&exp);
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static unsigned
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cfi_parse_reg (void)
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{
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int regno;
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expressionS exp;
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tc_parse_to_dw2regnum (&exp);
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switch (exp.X_op)
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{
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case O_register:
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@ -437,9 +441,14 @@ cfi_parse_reg (void)
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break;
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default:
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regno = -1;
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break;
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}
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if (regno < 0)
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{
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as_bad (_("bad register expression"));
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regno = 0;
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break;
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}
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return regno;
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@ -1,3 +1,10 @@
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2008-02-13 Jan Beulich <jbeulich@novell.com>
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* gas/cfi/cfi-i386.s: Add code testing use of all registers.
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Fix a few comments.
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* gas/cfi/cfi-x86_64.s: Likewise.
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* gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust.
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2002-02-12 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run x86-64-arch-2 instead of
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@ -46,3 +46,107 @@ The section .eh_frame contains:
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DW_CFA_nop
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DW_CFA_nop
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0000008c 00000010 00000000 CIE
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Version: 1
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Augmentation: "zR"
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Code alignment factor: 1
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Data alignment factor: -4
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Return address column: 8
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Augmentation data: 1b
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DW_CFA_undefined: r8 \(eip\)
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DW_CFA_nop
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000000a0 00000094 00000018 FDE cie=0000008c pc=00000044..00000071
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DW_CFA_advance_loc: 1 to 00000045
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DW_CFA_undefined: r0 \(eax\)
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DW_CFA_advance_loc: 1 to 00000046
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DW_CFA_undefined: r1 \(ecx\)
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DW_CFA_advance_loc: 1 to 00000047
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DW_CFA_undefined: r2 \(edx\)
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DW_CFA_advance_loc: 1 to 00000048
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DW_CFA_undefined: r3 \(ebx\)
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DW_CFA_advance_loc: 1 to 00000049
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DW_CFA_undefined: r4 \(esp\)
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DW_CFA_advance_loc: 1 to 0000004a
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DW_CFA_undefined: r5 \(ebp\)
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DW_CFA_advance_loc: 1 to 0000004b
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DW_CFA_undefined: r6 \(esi\)
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DW_CFA_advance_loc: 1 to 0000004c
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DW_CFA_undefined: r7 \(edi\)
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DW_CFA_advance_loc: 1 to 0000004d
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DW_CFA_undefined: r9 \(eflags\)
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DW_CFA_advance_loc: 1 to 0000004e
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DW_CFA_undefined: r40 \(es\)
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DW_CFA_advance_loc: 1 to 0000004f
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DW_CFA_undefined: r41 \(cs\)
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DW_CFA_advance_loc: 1 to 00000050
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DW_CFA_undefined: r43 \(ds\)
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DW_CFA_advance_loc: 1 to 00000051
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DW_CFA_undefined: r42 \(ss\)
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DW_CFA_advance_loc: 1 to 00000052
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DW_CFA_undefined: r44 \(fs\)
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DW_CFA_advance_loc: 1 to 00000053
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DW_CFA_undefined: r45 \(gs\)
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DW_CFA_advance_loc: 1 to 00000054
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DW_CFA_undefined: r48 \(tr\)
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DW_CFA_advance_loc: 1 to 00000055
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DW_CFA_undefined: r49 \(ldtr\)
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DW_CFA_advance_loc: 1 to 00000056
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DW_CFA_undefined: r39 \(mxcsr\)
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DW_CFA_advance_loc: 1 to 00000057
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DW_CFA_undefined: r21 \(xmm0\)
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DW_CFA_advance_loc: 1 to 00000058
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DW_CFA_undefined: r22 \(xmm1\)
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DW_CFA_advance_loc: 1 to 00000059
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DW_CFA_undefined: r23 \(xmm2\)
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DW_CFA_advance_loc: 1 to 0000005a
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DW_CFA_undefined: r24 \(xmm3\)
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DW_CFA_advance_loc: 1 to 0000005b
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DW_CFA_undefined: r25 \(xmm4\)
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DW_CFA_advance_loc: 1 to 0000005c
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DW_CFA_undefined: r26 \(xmm5\)
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DW_CFA_advance_loc: 1 to 0000005d
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DW_CFA_undefined: r27 \(xmm6\)
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DW_CFA_advance_loc: 1 to 0000005e
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DW_CFA_undefined: r28 \(xmm7\)
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DW_CFA_advance_loc: 1 to 0000005f
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DW_CFA_undefined: r37 \(fcw\)
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DW_CFA_advance_loc: 1 to 00000060
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DW_CFA_undefined: r38 \(fsw\)
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DW_CFA_advance_loc: 1 to 00000061
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DW_CFA_undefined: r11 \(st\(?0?\)?\)
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DW_CFA_advance_loc: 1 to 00000062
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DW_CFA_undefined: r12 \(st\(?1\)?\)
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DW_CFA_advance_loc: 1 to 00000063
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DW_CFA_undefined: r13 \(st\(?2\)?\)
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DW_CFA_advance_loc: 1 to 00000064
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DW_CFA_undefined: r14 \(st\(?3\)?\)
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DW_CFA_advance_loc: 1 to 00000065
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DW_CFA_undefined: r15 \(st\(?4\)?\)
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DW_CFA_advance_loc: 1 to 00000066
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DW_CFA_undefined: r16 \(st\(?5\)?\)
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DW_CFA_advance_loc: 1 to 00000067
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DW_CFA_undefined: r17 \(st\(?6\)?\)
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DW_CFA_advance_loc: 1 to 00000068
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DW_CFA_undefined: r18 \(st\(?7\)?\)
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DW_CFA_advance_loc: 1 to 00000069
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DW_CFA_undefined: r29 \(mm0\)
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DW_CFA_advance_loc: 1 to 0000006a
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DW_CFA_undefined: r30 \(mm1\)
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DW_CFA_advance_loc: 1 to 0000006b
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DW_CFA_undefined: r31 \(mm2\)
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DW_CFA_advance_loc: 1 to 0000006c
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DW_CFA_undefined: r32 \(mm3\)
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DW_CFA_advance_loc: 1 to 0000006d
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DW_CFA_undefined: r33 \(mm4\)
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DW_CFA_advance_loc: 1 to 0000006e
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DW_CFA_undefined: r34 \(mm5\)
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DW_CFA_advance_loc: 1 to 0000006f
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DW_CFA_undefined: r35 \(mm6\)
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DW_CFA_advance_loc: 1 to 00000070
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DW_CFA_undefined: r36 \(mm7\)
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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|
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@ -1,5 +1,3 @@
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#; $ as -o test.o gas-cfi-test.s && gcc -nostdlib -o test test.o
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.text
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#; func_locvars
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@ -52,7 +50,7 @@ func_prologue:
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#; func_otherreg
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#; - function that moves frame pointer to
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#; another register (r12) and then allocates
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#; another register (ebx) and then allocates
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#; a space for local variables
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.type func_otherreg,@function
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@ -65,14 +63,14 @@ func_otherreg:
|
|||
|
||||
#; alocate space for local vars
|
||||
#; (no .cfi_{def,adjust}_cfa_offset here,
|
||||
#; because CFA is computed from r12!)
|
||||
#; because CFA is computed from ebx!)
|
||||
sub $100,%esp
|
||||
|
||||
#; function body
|
||||
call func_prologue
|
||||
add $2, %eax
|
||||
|
||||
#; restore frame pointer from r12
|
||||
#; restore frame pointer from ebx
|
||||
mov %ebx,%esp
|
||||
.cfi_def_cfa esp,4
|
||||
ret
|
||||
|
|
@ -105,3 +103,63 @@ _start:
|
|||
int $0x80
|
||||
hlt
|
||||
.cfi_endproc
|
||||
|
||||
#; func_all_registers
|
||||
#; - test for all .cfi register numbers.
|
||||
#; This function is never called and the CFI info doesn't make sense.
|
||||
|
||||
.type func_all_registers,@function
|
||||
func_all_registers:
|
||||
.cfi_startproc simple
|
||||
|
||||
.cfi_undefined eip ; nop
|
||||
.cfi_undefined eax ; nop
|
||||
.cfi_undefined ecx ; nop
|
||||
.cfi_undefined edx ; nop
|
||||
.cfi_undefined ebx ; nop
|
||||
.cfi_undefined esp ; nop
|
||||
.cfi_undefined ebp ; nop
|
||||
.cfi_undefined esi ; nop
|
||||
.cfi_undefined edi ; nop
|
||||
.cfi_undefined eflags ; nop
|
||||
|
||||
.cfi_undefined es ; nop
|
||||
.cfi_undefined cs ; nop
|
||||
.cfi_undefined ds ; nop
|
||||
.cfi_undefined ss ; nop
|
||||
.cfi_undefined fs ; nop
|
||||
.cfi_undefined gs ; nop
|
||||
.cfi_undefined tr ; nop
|
||||
.cfi_undefined ldtr ; nop
|
||||
|
||||
.cfi_undefined mxcsr ; nop
|
||||
.cfi_undefined xmm0 ; nop
|
||||
.cfi_undefined xmm1 ; nop
|
||||
.cfi_undefined xmm2 ; nop
|
||||
.cfi_undefined xmm3 ; nop
|
||||
.cfi_undefined xmm4 ; nop
|
||||
.cfi_undefined xmm5 ; nop
|
||||
.cfi_undefined xmm6 ; nop
|
||||
.cfi_undefined xmm7 ; nop
|
||||
|
||||
.cfi_undefined fcw ; nop
|
||||
.cfi_undefined fsw ; nop
|
||||
.cfi_undefined st ; nop
|
||||
.cfi_undefined st(1) ; nop
|
||||
.cfi_undefined st(2) ; nop
|
||||
.cfi_undefined st(3) ; nop
|
||||
.cfi_undefined st(4) ; nop
|
||||
.cfi_undefined st(5) ; nop
|
||||
.cfi_undefined st(6) ; nop
|
||||
.cfi_undefined st(7) ; nop
|
||||
|
||||
.cfi_undefined mm0 ; nop
|
||||
.cfi_undefined mm1 ; nop
|
||||
.cfi_undefined mm2 ; nop
|
||||
.cfi_undefined mm3 ; nop
|
||||
.cfi_undefined mm4 ; nop
|
||||
.cfi_undefined mm5 ; nop
|
||||
.cfi_undefined mm6 ; nop
|
||||
.cfi_undefined mm7 ; nop
|
||||
|
||||
.cfi_endproc
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ The section .eh_frame contains:
|
|||
|
||||
DW_CFA_def_cfa: r7 \(rsp\) ofs 8
|
||||
|
||||
000000a4 00000030 00000018 FDE cie=00000090 pc=0000004d..00000058
|
||||
000000a4 0000002c 00000018 FDE cie=00000090 pc=0000004d..00000058
|
||||
DW_CFA_advance_loc: 1 to 0000004e
|
||||
DW_CFA_def_cfa_offset: 16
|
||||
DW_CFA_advance_loc: 1 to 0000004f
|
||||
|
|
@ -82,6 +82,144 @@ The section .eh_frame contains:
|
|||
DW_CFA_advance_loc: 1 to 00000057
|
||||
DW_CFA_restore_state
|
||||
DW_CFA_nop
|
||||
|
||||
000000d4 00000010 00000000 CIE
|
||||
Version: 1
|
||||
Augmentation: "zR"
|
||||
Code alignment factor: 1
|
||||
Data alignment factor: -8
|
||||
Return address column: 16
|
||||
Augmentation data: 1b
|
||||
|
||||
DW_CFA_undefined: r16 \(rip\)
|
||||
DW_CFA_nop
|
||||
|
||||
000000e8 000000cc 00000018 FDE cie=000000d4 pc=00000058..00000097
|
||||
DW_CFA_advance_loc: 1 to 00000059
|
||||
DW_CFA_undefined: r0 \(rax\)
|
||||
DW_CFA_advance_loc: 1 to 0000005a
|
||||
DW_CFA_undefined: r2 \(rcx\)
|
||||
DW_CFA_advance_loc: 1 to 0000005b
|
||||
DW_CFA_undefined: r1 \(rdx\)
|
||||
DW_CFA_advance_loc: 1 to 0000005c
|
||||
DW_CFA_undefined: r3 \(rbx\)
|
||||
DW_CFA_advance_loc: 1 to 0000005d
|
||||
DW_CFA_undefined: r7 \(rsp\)
|
||||
DW_CFA_advance_loc: 1 to 0000005e
|
||||
DW_CFA_undefined: r6 \(rbp\)
|
||||
DW_CFA_advance_loc: 1 to 0000005f
|
||||
DW_CFA_undefined: r4 \(rsi\)
|
||||
DW_CFA_advance_loc: 1 to 00000060
|
||||
DW_CFA_undefined: r5 \(rdi\)
|
||||
DW_CFA_advance_loc: 1 to 00000061
|
||||
DW_CFA_undefined: r8 \(r8\)
|
||||
DW_CFA_advance_loc: 1 to 00000062
|
||||
DW_CFA_undefined: r9 \(r9\)
|
||||
DW_CFA_advance_loc: 1 to 00000063
|
||||
DW_CFA_undefined: r10 \(r10\)
|
||||
DW_CFA_advance_loc: 1 to 00000064
|
||||
DW_CFA_undefined: r11 \(r11\)
|
||||
DW_CFA_advance_loc: 1 to 00000065
|
||||
DW_CFA_undefined: r12 \(r12\)
|
||||
DW_CFA_advance_loc: 1 to 00000066
|
||||
DW_CFA_undefined: r13 \(r13\)
|
||||
DW_CFA_advance_loc: 1 to 00000067
|
||||
DW_CFA_undefined: r14 \(r14\)
|
||||
DW_CFA_advance_loc: 1 to 00000068
|
||||
DW_CFA_undefined: r15 \(r15\)
|
||||
DW_CFA_advance_loc: 1 to 00000069
|
||||
DW_CFA_undefined: r49 \([er]flags\)
|
||||
DW_CFA_advance_loc: 1 to 0000006a
|
||||
DW_CFA_undefined: r50 \(es\)
|
||||
DW_CFA_advance_loc: 1 to 0000006b
|
||||
DW_CFA_undefined: r51 \(cs\)
|
||||
DW_CFA_advance_loc: 1 to 0000006c
|
||||
DW_CFA_undefined: r53 \(ds\)
|
||||
DW_CFA_advance_loc: 1 to 0000006d
|
||||
DW_CFA_undefined: r52 \(ss\)
|
||||
DW_CFA_advance_loc: 1 to 0000006e
|
||||
DW_CFA_undefined: r54 \(fs\)
|
||||
DW_CFA_advance_loc: 1 to 0000006f
|
||||
DW_CFA_undefined: r55 \(gs\)
|
||||
DW_CFA_advance_loc: 1 to 00000070
|
||||
DW_CFA_undefined: r62 \(tr\)
|
||||
DW_CFA_advance_loc: 1 to 00000071
|
||||
DW_CFA_undefined: r63 \(ldtr\)
|
||||
DW_CFA_advance_loc: 1 to 00000072
|
||||
DW_CFA_undefined: r58 \(fs\.base\)
|
||||
DW_CFA_advance_loc: 1 to 00000073
|
||||
DW_CFA_undefined: r59 \(gs\.base\)
|
||||
DW_CFA_advance_loc: 1 to 00000074
|
||||
DW_CFA_undefined: r64 \(mxcsr\)
|
||||
DW_CFA_advance_loc: 1 to 00000075
|
||||
DW_CFA_undefined: r17 \(xmm0\)
|
||||
DW_CFA_advance_loc: 1 to 00000076
|
||||
DW_CFA_undefined: r18 \(xmm1\)
|
||||
DW_CFA_advance_loc: 1 to 00000077
|
||||
DW_CFA_undefined: r19 \(xmm2\)
|
||||
DW_CFA_advance_loc: 1 to 00000078
|
||||
DW_CFA_undefined: r20 \(xmm3\)
|
||||
DW_CFA_advance_loc: 1 to 00000079
|
||||
DW_CFA_undefined: r21 \(xmm4\)
|
||||
DW_CFA_advance_loc: 1 to 0000007a
|
||||
DW_CFA_undefined: r22 \(xmm5\)
|
||||
DW_CFA_advance_loc: 1 to 0000007b
|
||||
DW_CFA_undefined: r23 \(xmm6\)
|
||||
DW_CFA_advance_loc: 1 to 0000007c
|
||||
DW_CFA_undefined: r24 \(xmm7\)
|
||||
DW_CFA_advance_loc: 1 to 0000007d
|
||||
DW_CFA_undefined: r25 \(xmm8\)
|
||||
DW_CFA_advance_loc: 1 to 0000007e
|
||||
DW_CFA_undefined: r26 \(xmm9\)
|
||||
DW_CFA_advance_loc: 1 to 0000007f
|
||||
DW_CFA_undefined: r27 \(xmm10\)
|
||||
DW_CFA_advance_loc: 1 to 00000080
|
||||
DW_CFA_undefined: r28 \(xmm11\)
|
||||
DW_CFA_advance_loc: 1 to 00000081
|
||||
DW_CFA_undefined: r29 \(xmm12\)
|
||||
DW_CFA_advance_loc: 1 to 00000082
|
||||
DW_CFA_undefined: r30 \(xmm13\)
|
||||
DW_CFA_advance_loc: 1 to 00000083
|
||||
DW_CFA_undefined: r31 \(xmm14\)
|
||||
DW_CFA_advance_loc: 1 to 00000084
|
||||
DW_CFA_undefined: r32 \(xmm15\)
|
||||
DW_CFA_advance_loc: 1 to 00000085
|
||||
DW_CFA_undefined: r65 \(fcw\)
|
||||
DW_CFA_advance_loc: 1 to 00000086
|
||||
DW_CFA_undefined: r66 \(fsw\)
|
||||
DW_CFA_advance_loc: 1 to 00000087
|
||||
DW_CFA_undefined: r33 \(st\(?0?\)?\)
|
||||
DW_CFA_advance_loc: 1 to 00000088
|
||||
DW_CFA_undefined: r34 \(st\(?1\)?\)
|
||||
DW_CFA_advance_loc: 1 to 00000089
|
||||
DW_CFA_undefined: r35 \(st\(?2\)?\)
|
||||
DW_CFA_advance_loc: 1 to 0000008a
|
||||
DW_CFA_undefined: r36 \(st\(?3\)?\)
|
||||
DW_CFA_advance_loc: 1 to 0000008b
|
||||
DW_CFA_undefined: r37 \(st\(?4\)?\)
|
||||
DW_CFA_advance_loc: 1 to 0000008c
|
||||
DW_CFA_undefined: r38 \(st\(?5\)?\)
|
||||
DW_CFA_advance_loc: 1 to 0000008d
|
||||
DW_CFA_undefined: r39 \(st\(?6\)?\)
|
||||
DW_CFA_advance_loc: 1 to 0000008e
|
||||
DW_CFA_undefined: r40 \(st\(?7\)?\)
|
||||
DW_CFA_advance_loc: 1 to 0000008f
|
||||
DW_CFA_undefined: r41 \(mm0\)
|
||||
DW_CFA_advance_loc: 1 to 00000090
|
||||
DW_CFA_undefined: r42 \(mm1\)
|
||||
DW_CFA_advance_loc: 1 to 00000091
|
||||
DW_CFA_undefined: r43 \(mm2\)
|
||||
DW_CFA_advance_loc: 1 to 00000092
|
||||
DW_CFA_undefined: r44 \(mm3\)
|
||||
DW_CFA_advance_loc: 1 to 00000093
|
||||
DW_CFA_undefined: r45 \(mm4\)
|
||||
DW_CFA_advance_loc: 1 to 00000094
|
||||
DW_CFA_undefined: r46 \(mm5\)
|
||||
DW_CFA_advance_loc: 1 to 00000095
|
||||
DW_CFA_undefined: r47 \(mm6\)
|
||||
DW_CFA_advance_loc: 1 to 00000096
|
||||
DW_CFA_undefined: r48 \(mm7\)
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
#; $ as -o test.o gas-cfi-test.s && gcc -nostdlib -o test test.o
|
||||
|
||||
.text
|
||||
|
||||
#; func_locvars
|
||||
|
|
@ -136,3 +134,81 @@ func_alldirectives:
|
|||
.cfi_restore_state
|
||||
ret
|
||||
.cfi_endproc
|
||||
|
||||
#; func_all_registers
|
||||
#; - test for all .cfi register numbers.
|
||||
#; This function is never called and the CFI info doesn't make sense.
|
||||
|
||||
.type func_all_registers,@function
|
||||
func_all_registers:
|
||||
.cfi_startproc simple
|
||||
|
||||
.cfi_undefined rip ; nop
|
||||
.cfi_undefined rax ; nop
|
||||
.cfi_undefined rcx ; nop
|
||||
.cfi_undefined rdx ; nop
|
||||
.cfi_undefined rbx ; nop
|
||||
.cfi_undefined rsp ; nop
|
||||
.cfi_undefined rbp ; nop
|
||||
.cfi_undefined rsi ; nop
|
||||
.cfi_undefined rdi ; nop
|
||||
.cfi_undefined r8 ; nop
|
||||
.cfi_undefined r9 ; nop
|
||||
.cfi_undefined r10 ; nop
|
||||
.cfi_undefined r11 ; nop
|
||||
.cfi_undefined r12 ; nop
|
||||
.cfi_undefined r13 ; nop
|
||||
.cfi_undefined r14 ; nop
|
||||
.cfi_undefined r15 ; nop
|
||||
.cfi_undefined rflags ; nop
|
||||
|
||||
.cfi_undefined es ; nop
|
||||
.cfi_undefined cs ; nop
|
||||
.cfi_undefined ds ; nop
|
||||
.cfi_undefined ss ; nop
|
||||
.cfi_undefined fs ; nop
|
||||
.cfi_undefined gs ; nop
|
||||
.cfi_undefined tr ; nop
|
||||
.cfi_undefined ldtr ; nop
|
||||
.cfi_undefined fs.base ; nop
|
||||
.cfi_undefined gs.base ; nop
|
||||
|
||||
.cfi_undefined mxcsr ; nop
|
||||
.cfi_undefined xmm0 ; nop
|
||||
.cfi_undefined xmm1 ; nop
|
||||
.cfi_undefined xmm2 ; nop
|
||||
.cfi_undefined xmm3 ; nop
|
||||
.cfi_undefined xmm4 ; nop
|
||||
.cfi_undefined xmm5 ; nop
|
||||
.cfi_undefined xmm6 ; nop
|
||||
.cfi_undefined xmm7 ; nop
|
||||
.cfi_undefined xmm8 ; nop
|
||||
.cfi_undefined xmm9 ; nop
|
||||
.cfi_undefined xmm10 ; nop
|
||||
.cfi_undefined xmm11 ; nop
|
||||
.cfi_undefined xmm12 ; nop
|
||||
.cfi_undefined xmm13 ; nop
|
||||
.cfi_undefined xmm14 ; nop
|
||||
.cfi_undefined xmm15 ; nop
|
||||
|
||||
.cfi_undefined fcw ; nop
|
||||
.cfi_undefined fsw ; nop
|
||||
.cfi_undefined st ; nop
|
||||
.cfi_undefined st(1) ; nop
|
||||
.cfi_undefined st(2) ; nop
|
||||
.cfi_undefined st(3) ; nop
|
||||
.cfi_undefined st(4) ; nop
|
||||
.cfi_undefined st(5) ; nop
|
||||
.cfi_undefined st(6) ; nop
|
||||
.cfi_undefined st(7) ; nop
|
||||
|
||||
.cfi_undefined mm0 ; nop
|
||||
.cfi_undefined mm1 ; nop
|
||||
.cfi_undefined mm2 ; nop
|
||||
.cfi_undefined mm3 ; nop
|
||||
.cfi_undefined mm4 ; nop
|
||||
.cfi_undefined mm5 ; nop
|
||||
.cfi_undefined mm6 ; nop
|
||||
.cfi_undefined mm7 ; nop
|
||||
|
||||
.cfi_endproc
|
||||
|
|
|
|||
|
|
@ -1,3 +1,12 @@
|
|||
2008-02-13 Jan Beulich <jbeulich@novell.com>
|
||||
|
||||
* i386-gen.c (process_i386_registers): Process new fields.
|
||||
* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
|
||||
unsigned char. Add dw2_regnum and Dw2Inval.
|
||||
* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
|
||||
register names.
|
||||
* i386-tbl.h: Re-generate.
|
||||
|
||||
2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
|
||||
|
|
|
|||
|
|
@ -802,6 +802,7 @@ process_i386_registers (FILE *table)
|
|||
char buf[2048];
|
||||
char *str, *p, *last;
|
||||
char *reg_name, *reg_type, *reg_flags, *reg_num;
|
||||
char *dw2_32_num, *dw2_64_num;
|
||||
|
||||
filename = "i386-reg.tbl";
|
||||
fp = fopen (filename, "r");
|
||||
|
|
@ -863,11 +864,24 @@ process_i386_registers (FILE *table)
|
|||
/* Find reg_num. */
|
||||
reg_num = next_field (str, ',', &str);
|
||||
|
||||
if (str >= last)
|
||||
abort ();
|
||||
|
||||
fprintf (table, " { \"%s\",\n ", reg_name);
|
||||
|
||||
process_i386_operand_type (table, reg_type, 0, "\t");
|
||||
|
||||
fprintf (table, ",\n %s, %s },\n", reg_flags, reg_num);
|
||||
/* Find 32-bit Dwarf2 register number. */
|
||||
dw2_32_num = next_field (str, ',', &str);
|
||||
|
||||
if (str >= last)
|
||||
abort ();
|
||||
|
||||
/* Find 64-bit Dwarf2 register number. */
|
||||
dw2_64_num = next_field (str, ',', &str);
|
||||
|
||||
fprintf (table, ",\n %s, %s, { %s, %s } },\n",
|
||||
reg_flags, reg_num, dw2_32_num, dw2_64_num);
|
||||
}
|
||||
|
||||
fclose (fp);
|
||||
|
|
|
|||
|
|
@ -492,15 +492,17 @@ typedef struct
|
|||
{
|
||||
char *reg_name;
|
||||
i386_operand_type reg_type;
|
||||
unsigned int reg_flags;
|
||||
unsigned char reg_flags;
|
||||
#define RegRex 0x1 /* Extended register. */
|
||||
#define RegRex64 0x2 /* Extended 8 bit register. */
|
||||
unsigned int reg_num;
|
||||
#define RegRip ((unsigned int ) ~0)
|
||||
unsigned char reg_num;
|
||||
#define RegRip ((unsigned char ) ~0)
|
||||
#define RegEip (RegRip - 1)
|
||||
/* EIZ and RIZ are fake index registers. */
|
||||
#define RegEiz (RegEip - 1)
|
||||
#define RegRiz (RegEiz - 1)
|
||||
signed char dw2_regnum[2];
|
||||
#define Dw2Inval (-1)
|
||||
}
|
||||
reg_entry;
|
||||
|
||||
|
|
|
|||
|
|
@ -20,187 +20,206 @@
|
|||
// 02110-1301, USA.
|
||||
|
||||
// Make %st first as we test for it.
|
||||
st, FloatReg|FloatAcc, 0, 0
|
||||
st, FloatReg|FloatAcc, 0, 0, 11, 33
|
||||
// 8 bit regs
|
||||
al, Reg8|Acc|Byte, 0, 0
|
||||
cl, Reg8|ShiftCount, 0, 1
|
||||
dl, Reg8, 0, 2
|
||||
bl, Reg8, 0, 3
|
||||
ah, Reg8, 0, 4
|
||||
ch, Reg8, 0, 5
|
||||
dh, Reg8, 0, 6
|
||||
bh, Reg8, 0, 7
|
||||
axl, Reg8|Acc|Byte, RegRex64, 0
|
||||
cxl, Reg8, RegRex64, 1
|
||||
dxl, Reg8, RegRex64, 2
|
||||
bxl, Reg8, RegRex64, 3
|
||||
spl, Reg8, RegRex64, 4
|
||||
bpl, Reg8, RegRex64, 5
|
||||
sil, Reg8, RegRex64, 6
|
||||
dil, Reg8, RegRex64, 7
|
||||
r8b, Reg8, RegRex|RegRex64, 0
|
||||
r9b, Reg8, RegRex|RegRex64, 1
|
||||
r10b, Reg8, RegRex|RegRex64, 2
|
||||
r11b, Reg8, RegRex|RegRex64, 3
|
||||
r12b, Reg8, RegRex|RegRex64, 4
|
||||
r13b, Reg8, RegRex|RegRex64, 5
|
||||
r14b, Reg8, RegRex|RegRex64, 6
|
||||
r15b, Reg8, RegRex|RegRex64, 7
|
||||
al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
|
||||
cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
|
||||
dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
|
||||
bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
|
||||
ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
|
||||
ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
|
||||
dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
|
||||
bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
|
||||
axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
|
||||
cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
|
||||
dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
|
||||
bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
|
||||
spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
|
||||
bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
|
||||
sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
|
||||
dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
|
||||
r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
|
||||
r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
|
||||
r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
|
||||
r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
|
||||
r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
|
||||
r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
|
||||
r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
|
||||
r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
|
||||
// 16 bit regs
|
||||
ax, Reg16|Acc|Word, 0, 0
|
||||
cx, Reg16, 0, 1
|
||||
dx, Reg16|InOutPortReg, 0, 2
|
||||
bx, Reg16|BaseIndex, 0, 3
|
||||
sp, Reg16, 0, 4
|
||||
bp, Reg16|BaseIndex, 0, 5
|
||||
si, Reg16|BaseIndex, 0, 6
|
||||
di, Reg16|BaseIndex, 0, 7
|
||||
r8w, Reg16, RegRex, 0
|
||||
r9w, Reg16, RegRex, 1
|
||||
r10w, Reg16, RegRex, 2
|
||||
r11w, Reg16, RegRex, 3
|
||||
r12w, Reg16, RegRex, 4
|
||||
r13w, Reg16, RegRex, 5
|
||||
r14w, Reg16, RegRex, 6
|
||||
r15w, Reg16, RegRex, 7
|
||||
ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
|
||||
cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
|
||||
dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
|
||||
bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
|
||||
sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
|
||||
bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
|
||||
si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
|
||||
di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
|
||||
r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// 32 bit regs
|
||||
eax, Reg32|BaseIndex|Acc|Dword, 0, 0
|
||||
ecx, Reg32|BaseIndex, 0, 1
|
||||
edx, Reg32|BaseIndex, 0, 2
|
||||
ebx, Reg32|BaseIndex, 0, 3
|
||||
esp, Reg32, 0, 4
|
||||
ebp, Reg32|BaseIndex, 0, 5
|
||||
esi, Reg32|BaseIndex, 0, 6
|
||||
edi, Reg32|BaseIndex, 0, 7
|
||||
r8d, Reg32|BaseIndex, RegRex, 0
|
||||
r9d, Reg32|BaseIndex, RegRex, 1
|
||||
r10d, Reg32|BaseIndex, RegRex, 2
|
||||
r11d, Reg32|BaseIndex, RegRex, 3
|
||||
r12d, Reg32|BaseIndex, RegRex, 4
|
||||
r13d, Reg32|BaseIndex, RegRex, 5
|
||||
r14d, Reg32|BaseIndex, RegRex, 6
|
||||
r15d, Reg32|BaseIndex, RegRex, 7
|
||||
rax, Reg64|BaseIndex|Acc|Qword, 0, 0
|
||||
rcx, Reg64|BaseIndex, 0, 1
|
||||
rdx, Reg64|BaseIndex, 0, 2
|
||||
rbx, Reg64|BaseIndex, 0, 3
|
||||
rsp, Reg64, 0, 4
|
||||
rbp, Reg64|BaseIndex, 0, 5
|
||||
rsi, Reg64|BaseIndex, 0, 6
|
||||
rdi, Reg64|BaseIndex, 0, 7
|
||||
r8, Reg64|BaseIndex, RegRex, 0
|
||||
r9, Reg64|BaseIndex, RegRex, 1
|
||||
r10, Reg64|BaseIndex, RegRex, 2
|
||||
r11, Reg64|BaseIndex, RegRex, 3
|
||||
r12, Reg64|BaseIndex, RegRex, 4
|
||||
r13, Reg64|BaseIndex, RegRex, 5
|
||||
r14, Reg64|BaseIndex, RegRex, 6
|
||||
r15, Reg64|BaseIndex, RegRex, 7
|
||||
eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
|
||||
ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
|
||||
edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
|
||||
ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
|
||||
esp, Reg32, 0, 4, 4, Dw2Inval
|
||||
ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
|
||||
esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
|
||||
edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
|
||||
r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
|
||||
rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
|
||||
rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
|
||||
rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
|
||||
rsp, Reg64, 0, 4, Dw2Inval, 7
|
||||
rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
|
||||
rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
|
||||
rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
|
||||
r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
|
||||
r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
|
||||
r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
|
||||
r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
|
||||
r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
|
||||
r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
|
||||
r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
|
||||
r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
|
||||
// Segment registers.
|
||||
es, SReg2, 0, 0
|
||||
cs, SReg2, 0, 1
|
||||
ss, SReg2, 0, 2
|
||||
ds, SReg2, 0, 3
|
||||
fs, SReg3, 0, 4
|
||||
gs, SReg3, 0, 5
|
||||
es, SReg2, 0, 0, 40, 50
|
||||
cs, SReg2, 0, 1, 41, 51
|
||||
ss, SReg2, 0, 2, 42, 52
|
||||
ds, SReg2, 0, 3, 43, 53
|
||||
fs, SReg3, 0, 4, 44, 54
|
||||
gs, SReg3, 0, 5, 45, 55
|
||||
// Control registers.
|
||||
cr0, Control, 0, 0
|
||||
cr1, Control, 0, 1
|
||||
cr2, Control, 0, 2
|
||||
cr3, Control, 0, 3
|
||||
cr4, Control, 0, 4
|
||||
cr5, Control, 0, 5
|
||||
cr6, Control, 0, 6
|
||||
cr7, Control, 0, 7
|
||||
cr8, Control, RegRex, 0
|
||||
cr9, Control, RegRex, 1
|
||||
cr10, Control, RegRex, 2
|
||||
cr11, Control, RegRex, 3
|
||||
cr12, Control, RegRex, 4
|
||||
cr13, Control, RegRex, 5
|
||||
cr14, Control, RegRex, 6
|
||||
cr15, Control, RegRex, 7
|
||||
cr0, Control, 0, 0, Dw2Inval, Dw2Inval
|
||||
cr1, Control, 0, 1, Dw2Inval, Dw2Inval
|
||||
cr2, Control, 0, 2, Dw2Inval, Dw2Inval
|
||||
cr3, Control, 0, 3, Dw2Inval, Dw2Inval
|
||||
cr4, Control, 0, 4, Dw2Inval, Dw2Inval
|
||||
cr5, Control, 0, 5, Dw2Inval, Dw2Inval
|
||||
cr6, Control, 0, 6, Dw2Inval, Dw2Inval
|
||||
cr7, Control, 0, 7, Dw2Inval, Dw2Inval
|
||||
cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// Debug registers.
|
||||
db0, Debug, 0, 0
|
||||
db1, Debug, 0, 1
|
||||
db2, Debug, 0, 2
|
||||
db3, Debug, 0, 3
|
||||
db4, Debug, 0, 4
|
||||
db5, Debug, 0, 5
|
||||
db6, Debug, 0, 6
|
||||
db7, Debug, 0, 7
|
||||
db8, Debug, RegRex, 0
|
||||
db9, Debug, RegRex, 1
|
||||
db10, Debug, RegRex, 2
|
||||
db11, Debug, RegRex, 3
|
||||
db12, Debug, RegRex, 4
|
||||
db13, Debug, RegRex, 5
|
||||
db14, Debug, RegRex, 6
|
||||
db15, Debug, RegRex, 7
|
||||
dr0, Debug, 0, 0
|
||||
dr1, Debug, 0, 1
|
||||
dr2, Debug, 0, 2
|
||||
dr3, Debug, 0, 3
|
||||
dr4, Debug, 0, 4
|
||||
dr5, Debug, 0, 5
|
||||
dr6, Debug, 0, 6
|
||||
dr7, Debug, 0, 7
|
||||
dr8, Debug, RegRex, 0
|
||||
dr9, Debug, RegRex, 1
|
||||
dr10, Debug, RegRex, 2
|
||||
dr11, Debug, RegRex, 3
|
||||
dr12, Debug, RegRex, 4
|
||||
dr13, Debug, RegRex, 5
|
||||
dr14, Debug, RegRex, 6
|
||||
dr15, Debug, RegRex, 7
|
||||
db0, Debug, 0, 0, Dw2Inval, Dw2Inval
|
||||
db1, Debug, 0, 1, Dw2Inval, Dw2Inval
|
||||
db2, Debug, 0, 2, Dw2Inval, Dw2Inval
|
||||
db3, Debug, 0, 3, Dw2Inval, Dw2Inval
|
||||
db4, Debug, 0, 4, Dw2Inval, Dw2Inval
|
||||
db5, Debug, 0, 5, Dw2Inval, Dw2Inval
|
||||
db6, Debug, 0, 6, Dw2Inval, Dw2Inval
|
||||
db7, Debug, 0, 7, Dw2Inval, Dw2Inval
|
||||
db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
|
||||
dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
|
||||
dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
|
||||
dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
|
||||
dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
|
||||
dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
|
||||
dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
|
||||
dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
|
||||
dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// Test registers.
|
||||
tr0, Test, 0, 0
|
||||
tr1, Test, 0, 1
|
||||
tr2, Test, 0, 2
|
||||
tr3, Test, 0, 3
|
||||
tr4, Test, 0, 4
|
||||
tr5, Test, 0, 5
|
||||
tr6, Test, 0, 6
|
||||
tr7, Test, 0, 7
|
||||
tr0, Test, 0, 0, Dw2Inval, Dw2Inval
|
||||
tr1, Test, 0, 1, Dw2Inval, Dw2Inval
|
||||
tr2, Test, 0, 2, Dw2Inval, Dw2Inval
|
||||
tr3, Test, 0, 3, Dw2Inval, Dw2Inval
|
||||
tr4, Test, 0, 4, Dw2Inval, Dw2Inval
|
||||
tr5, Test, 0, 5, Dw2Inval, Dw2Inval
|
||||
tr6, Test, 0, 6, Dw2Inval, Dw2Inval
|
||||
tr7, Test, 0, 7, Dw2Inval, Dw2Inval
|
||||
// MMX and simd registers.
|
||||
mm0, RegMMX, 0, 0
|
||||
mm1, RegMMX, 0, 1
|
||||
mm2, RegMMX, 0, 2
|
||||
mm3, RegMMX, 0, 3
|
||||
mm4, RegMMX, 0, 4
|
||||
mm5, RegMMX, 0, 5
|
||||
mm6, RegMMX, 0, 6
|
||||
mm7, RegMMX, 0, 7
|
||||
xmm0, RegXMM, 0, 0
|
||||
xmm1, RegXMM, 0, 1
|
||||
xmm2, RegXMM, 0, 2
|
||||
xmm3, RegXMM, 0, 3
|
||||
xmm4, RegXMM, 0, 4
|
||||
xmm5, RegXMM, 0, 5
|
||||
xmm6, RegXMM, 0, 6
|
||||
xmm7, RegXMM, 0, 7
|
||||
xmm8, RegXMM, RegRex, 0
|
||||
xmm9, RegXMM, RegRex, 1
|
||||
xmm10, RegXMM, RegRex, 2
|
||||
xmm11, RegXMM, RegRex, 3
|
||||
xmm12, RegXMM, RegRex, 4
|
||||
xmm13, RegXMM, RegRex, 5
|
||||
xmm14, RegXMM, RegRex, 6
|
||||
xmm15, RegXMM, RegRex, 7
|
||||
mm0, RegMMX, 0, 0, 29, 41
|
||||
mm1, RegMMX, 0, 1, 30, 42
|
||||
mm2, RegMMX, 0, 2, 31, 43
|
||||
mm3, RegMMX, 0, 3, 32, 44
|
||||
mm4, RegMMX, 0, 4, 33, 45
|
||||
mm5, RegMMX, 0, 5, 34, 46
|
||||
mm6, RegMMX, 0, 6, 35, 47
|
||||
mm7, RegMMX, 0, 7, 36, 48
|
||||
xmm0, RegXMM, 0, 0, 21, 17
|
||||
xmm1, RegXMM, 0, 1, 22, 18
|
||||
xmm2, RegXMM, 0, 2, 23, 19
|
||||
xmm3, RegXMM, 0, 3, 24, 20
|
||||
xmm4, RegXMM, 0, 4, 25, 21
|
||||
xmm5, RegXMM, 0, 5, 26, 22
|
||||
xmm6, RegXMM, 0, 6, 27, 23
|
||||
xmm7, RegXMM, 0, 7, 28, 24
|
||||
xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
|
||||
xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
|
||||
xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
|
||||
xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
|
||||
xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
|
||||
xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
|
||||
xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
|
||||
xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
|
||||
// No type will make these registers rejected for all purposes except
|
||||
// for addressing. This saves creating one extra type for RIP/EIP.
|
||||
rip, BaseIndex, RegRex64, RegRip
|
||||
eip, BaseIndex, RegRex64, RegEip
|
||||
rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
|
||||
eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
|
||||
// No type will make these registers rejected for all purposes except
|
||||
// for addressing.
|
||||
eiz, BaseIndex, 0, RegEiz
|
||||
riz, BaseIndex, 0, RegRiz
|
||||
eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
|
||||
riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval
|
||||
// fp regs.
|
||||
st(0), FloatReg|FloatAcc, 0, 0
|
||||
st(1), FloatReg, 0, 1
|
||||
st(2), FloatReg, 0, 2
|
||||
st(3), FloatReg, 0, 3
|
||||
st(4), FloatReg, 0, 4
|
||||
st(5), FloatReg, 0, 5
|
||||
st(6), FloatReg, 0, 6
|
||||
st(7), FloatReg, 0, 7
|
||||
st(0), FloatReg|FloatAcc, 0, 0, 11, 33
|
||||
st(1), FloatReg, 0, 1, 12, 34
|
||||
st(2), FloatReg, 0, 2, 13, 35
|
||||
st(3), FloatReg, 0, 3, 14, 36
|
||||
st(4), FloatReg, 0, 4, 15, 37
|
||||
st(5), FloatReg, 0, 5, 16, 38
|
||||
st(6), FloatReg, 0, 6, 17, 39
|
||||
st(7), FloatReg, 0, 7, 18, 40
|
||||
// Pseudo-register names only used in .cfi_* directives
|
||||
eflags, 0, 0, 0, 9, 49
|
||||
rflags, 0, 0, 0, Dw2Inval, 49
|
||||
fs.base, 0, 0, 0, Dw2Inval, 58
|
||||
gs.base, 0, 0, 0, Dw2Inval, 59
|
||||
tr, 0, 0, 0, 48, 62
|
||||
ldtr, 0, 0, 0, 49, 63
|
||||
// st0...7 for backward compatibility
|
||||
st0, 0, 0, 0, 11, 33
|
||||
st1, 0, 0, 1, 12, 34
|
||||
st2, 0, 0, 2, 13, 35
|
||||
st3, 0, 0, 3, 14, 36
|
||||
st4, 0, 0, 4, 15, 37
|
||||
st5, 0, 0, 5, 16, 38
|
||||
st6, 0, 0, 6, 17, 39
|
||||
st7, 0, 0, 7, 18, 40
|
||||
fcw, 0, 0, 0, 37, 65
|
||||
fsw, 0, 0, 0, 38, 66
|
||||
mxcsr, 0, 0, 0, 39, 64
|
||||
|
|
|
|||
File diff suppressed because it is too large
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Reference in a new issue