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sim-main.h: Re-arange r5900 registers so that they have their own

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little struct.
interp.c: Update.  Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite.  Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
This commit is contained in:
Andrew Cagney 1998-02-23 16:55:38 +00:00
parent 0325f2dc89
commit a48e8c8d21
7 changed files with 628 additions and 261 deletions
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43
sim/mips/ChangeLog
View file

@ -1,3 +1,46 @@
start-sanitize-r5900
Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_store_register, sim_fetch_register): Pull swifty
to get gdb talking to re-aranged sim_cpu register structure.
end-sanitize-r5900
Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-main.h (Max, Min): Declare.
* interp.c (Max, Min): New functions.
* mips.igen (BC1): Add tracing.
start-sanitize-vr5400
Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
* mdmx.igen: Tag all functions as requiring either with mdmx or
vr5400 processor.
end-sanitize-vr5400
start-sanitize-r5900
Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
to 32.
(SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
* mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
* r5900.igen: Rewrite.
* sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
struct.
(GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
end-sanitize-r5900
Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
* interp.c Added memory map for stack in vr4100
Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com> Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
* interp.c (load_memory): Add missing "break"'s. * interp.c (load_memory): Add missing "break"'s.

138
sim/mips/configure vendored
View file

@ -76,7 +76,7 @@
# Guess values for system-dependent variables and create Makefiles. # Guess values for system-dependent variables and create Makefiles.
# Generated automatically using autoconf version 2.12.1 # Generated automatically using autoconf version 2.12
# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. # Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
# #
# This configure script is free software; the Free Software Foundation # This configure script is free software; the Free Software Foundation
@ -156,7 +156,6 @@ mandir='${prefix}/man'
# Initialize some other variables. # Initialize some other variables.
subdirs= subdirs=
MFLAGS= MAKEFLAGS= MFLAGS= MAKEFLAGS=
SHELL=${CONFIG_SHELL-/bin/sh}
# Maximum number of lines to put in a shell here document. # Maximum number of lines to put in a shell here document.
ac_max_here_lines=12 ac_max_here_lines=12
@ -440,7 +439,7 @@ EOF
verbose=yes ;; verbose=yes ;;
-version | --version | --versio | --versi | --vers) -version | --version | --versio | --versi | --vers)
echo "configure generated by autoconf version 2.12.1" echo "configure generated by autoconf version 2.12"
exit 0 ;; exit 0 ;;
-with-* | --with-*) -with-* | --with-*)
@ -628,7 +627,7 @@ fi
echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
echo "configure:632: checking how to run the C preprocessor" >&5 echo "configure:631: checking how to run the C preprocessor" >&5
# On Suns, sometimes $CPP names a directory. # On Suns, sometimes $CPP names a directory.
if test -n "$CPP" && test -d "$CPP"; then if test -n "$CPP" && test -d "$CPP"; then
CPP= CPP=
@ -643,13 +642,13 @@ else
# On the NeXT, cc -E runs the code through the compiler's parser, # On the NeXT, cc -E runs the code through the compiler's parser,
# not just through cpp. # not just through cpp.
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 647 "configure" #line 646 "configure"
#include "confdefs.h" #include "confdefs.h"
#include <assert.h> #include <assert.h>
Syntax Error Syntax Error
EOF EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:653: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } { (eval echo configure:652: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out` ac_err=`grep -v '^ *+' conftest.out`
if test -z "$ac_err"; then if test -z "$ac_err"; then
: :
@ -660,13 +659,13 @@ else
rm -rf conftest* rm -rf conftest*
CPP="${CC-cc} -E -traditional-cpp" CPP="${CC-cc} -E -traditional-cpp"
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 664 "configure" #line 663 "configure"
#include "confdefs.h" #include "confdefs.h"
#include <assert.h> #include <assert.h>
Syntax Error Syntax Error
EOF EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:670: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } { (eval echo configure:669: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out` ac_err=`grep -v '^ *+' conftest.out`
if test -z "$ac_err"; then if test -z "$ac_err"; then
: :
@ -734,33 +733,33 @@ esac
# Make sure we can run config.sub. # Make sure we can run config.sub.
if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then : if $ac_config_sub sun4 >/dev/null 2>&1; then :
else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
fi fi
echo $ac_n "checking host system type""... $ac_c" 1>&6 echo $ac_n "checking host system type""... $ac_c" 1>&6
echo "configure:743: checking host system type" >&5 echo "configure:742: checking host system type" >&5
host_alias=$host host_alias=$host
case "$host_alias" in case "$host_alias" in
NONE) NONE)
case $nonopt in case $nonopt in
NONE) NONE)
if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then : if host_alias=`$ac_config_guess`; then :
else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
fi ;; fi ;;
*) host_alias=$nonopt ;; *) host_alias=$nonopt ;;
esac ;; esac ;;
esac esac
host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias` host=`$ac_config_sub $host_alias`
host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
echo "$ac_t""$host" 1>&6 echo "$ac_t""$host" 1>&6
echo $ac_n "checking target system type""... $ac_c" 1>&6 echo $ac_n "checking target system type""... $ac_c" 1>&6
echo "configure:764: checking target system type" >&5 echo "configure:763: checking target system type" >&5
target_alias=$target target_alias=$target
case "$target_alias" in case "$target_alias" in
@ -771,14 +770,14 @@ NONE)
esac ;; esac ;;
esac esac
target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias` target=`$ac_config_sub $target_alias`
target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
echo "$ac_t""$target" 1>&6 echo "$ac_t""$target" 1>&6
echo $ac_n "checking build system type""... $ac_c" 1>&6 echo $ac_n "checking build system type""... $ac_c" 1>&6
echo "configure:782: checking build system type" >&5 echo "configure:781: checking build system type" >&5
build_alias=$build build_alias=$build
case "$build_alias" in case "$build_alias" in
@ -789,7 +788,7 @@ NONE)
esac ;; esac ;;
esac esac
build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias` build=`$ac_config_sub $build_alias`
build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
@ -822,7 +821,7 @@ test "$program_transform_name" = "" && program_transform_name="s,x,x,"
# Extract the first word of "gcc", so it can be a program name with args. # Extract the first word of "gcc", so it can be a program name with args.
set dummy gcc; ac_word=$2 set dummy gcc; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:826: checking for $ac_word" >&5 echo "configure:825: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
@ -851,7 +850,7 @@ if test -z "$CC"; then
# Extract the first word of "cc", so it can be a program name with args. # Extract the first word of "cc", so it can be a program name with args.
set dummy cc; ac_word=$2 set dummy cc; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:855: checking for $ac_word" >&5 echo "configure:854: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
@ -899,7 +898,7 @@ fi
fi fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
echo "configure:903: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 echo "configure:902: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
ac_ext=c ac_ext=c
# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@ -909,11 +908,11 @@ ac_link='${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS
cross_compiling=$ac_cv_prog_cc_cross cross_compiling=$ac_cv_prog_cc_cross
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 913 "configure" #line 912 "configure"
#include "confdefs.h" #include "confdefs.h"
main(){return(0);} main(){return(0);}
EOF EOF
if { (eval echo configure:917: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then if { (eval echo configure:916: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
ac_cv_prog_cc_works=yes ac_cv_prog_cc_works=yes
# If we can't run a trivial program, we are probably using a cross compiler. # If we can't run a trivial program, we are probably using a cross compiler.
if (./conftest; exit) 2>/dev/null; then if (./conftest; exit) 2>/dev/null; then
@ -933,12 +932,12 @@ if test $ac_cv_prog_cc_works = no; then
{ echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
fi fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
echo "configure:937: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "configure:936: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
cross_compiling=$ac_cv_prog_cc_cross cross_compiling=$ac_cv_prog_cc_cross
echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
echo "configure:942: checking whether we are using GNU C" >&5 echo "configure:941: checking whether we are using GNU C" >&5
if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
@ -947,7 +946,7 @@ else
yes; yes;
#endif #endif
EOF EOF
if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:951: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:950: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
ac_cv_prog_gcc=yes ac_cv_prog_gcc=yes
else else
ac_cv_prog_gcc=no ac_cv_prog_gcc=no
@ -962,7 +961,7 @@ if test $ac_cv_prog_gcc = yes; then
ac_save_CFLAGS="$CFLAGS" ac_save_CFLAGS="$CFLAGS"
CFLAGS= CFLAGS=
echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
echo "configure:966: checking whether ${CC-cc} accepts -g" >&5 echo "configure:965: checking whether ${CC-cc} accepts -g" >&5
if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
@ -996,12 +995,11 @@ fi
# SunOS /usr/etc/install # SunOS /usr/etc/install
# IRIX /sbin/install # IRIX /sbin/install
# AIX /bin/install # AIX /bin/install
# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
# AFS /usr/afsws/bin/install, which mishandles nonexistent args # AFS /usr/afsws/bin/install, which mishandles nonexistent args
# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
# ./install, which can be erroneously created by make from ./install.sh. # ./install, which can be erroneously created by make from ./install.sh.
echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
echo "configure:1005: checking for a BSD compatible install" >&5 echo "configure:1003: checking for a BSD compatible install" >&5
if test -z "$INSTALL"; then if test -z "$INSTALL"; then
if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
@ -1013,13 +1011,12 @@ else
/|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;; /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;
*) *)
# OSF1 and SCO ODT 3.0 have their own names for install. # OSF1 and SCO ODT 3.0 have their own names for install.
# Don't use installbsd from OSF since it installs stuff as root for ac_prog in ginstall installbsd scoinst install; do
# by default.
for ac_prog in ginstall scoinst install; do
if test -f $ac_dir/$ac_prog; then if test -f $ac_dir/$ac_prog; then
if test $ac_prog = install && if test $ac_prog = install &&
grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then
# AIX install. It has an incompatible calling convention. # AIX install. It has an incompatible calling convention.
# OSF/1 installbsd also uses dspmsg, but is usable.
: :
else else
ac_cv_path_install="$ac_dir/$ac_prog -c" ac_cv_path_install="$ac_dir/$ac_prog -c"
@ -1067,7 +1064,7 @@ AR=${AR-ar}
# Extract the first word of "ranlib", so it can be a program name with args. # Extract the first word of "ranlib", so it can be a program name with args.
set dummy ranlib; ac_word=$2 set dummy ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:1071: checking for $ac_word" >&5 echo "configure:1068: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
@ -1101,17 +1098,17 @@ for ac_hdr in stdlib.h string.h strings.h unistd.h time.h sys/time.h sys/resourc
do do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:1105: checking for $ac_hdr" >&5 echo "configure:1102: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 1110 "configure" #line 1107 "configure"
#include "confdefs.h" #include "confdefs.h"
#include <$ac_hdr> #include <$ac_hdr>
EOF EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:1115: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } { (eval echo configure:1112: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out` ac_err=`grep -v '^ *+' conftest.out`
if test -z "$ac_err"; then if test -z "$ac_err"; then
rm -rf conftest* rm -rf conftest*
@ -1140,12 +1137,12 @@ done
for ac_func in getrusage time sigaction for ac_func in getrusage time sigaction
do do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:1144: checking for $ac_func" >&5 echo "configure:1141: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 1149 "configure" #line 1146 "configure"
#include "confdefs.h" #include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes, /* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */ which can conflict with char $ac_func(); below. */
@ -1168,7 +1165,7 @@ $ac_func();
; return 0; } ; return 0; }
EOF EOF
if { (eval echo configure:1172: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then if { (eval echo configure:1169: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
rm -rf conftest* rm -rf conftest*
eval "ac_cv_func_$ac_func=yes" eval "ac_cv_func_$ac_func=yes"
else else
@ -1197,11 +1194,12 @@ done
USE_MAINTAINER_MODE=no
# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
if test "${enable_maintainer_mode+set}" = set; then if test "${enable_maintainer_mode+set}" = set; then
enableval="$enable_maintainer_mode" enableval="$enable_maintainer_mode"
case "${enableval}" in case "${enableval}" in
yes) MAINT="" ;; yes) MAINT="" USE_MAINTAINER_MODE=yes ;;
no) MAINT="#" ;; no) MAINT="#" ;;
*) { echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;; *) { echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;;
esac esac
@ -1340,12 +1338,12 @@ fi
echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6 echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6
echo "configure:1344: checking return type of signal handlers" >&5 echo "configure:1342: checking return type of signal handlers" >&5
if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 1349 "configure" #line 1347 "configure"
#include "confdefs.h" #include "confdefs.h"
#include <sys/types.h> #include <sys/types.h>
#include <signal.h> #include <signal.h>
@ -1362,7 +1360,7 @@ int main() {
int i; int i;
; return 0; } ; return 0; }
EOF EOF
if { (eval echo configure:1366: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then if { (eval echo configure:1364: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest* rm -rf conftest*
ac_cv_type_signal=void ac_cv_type_signal=void
else else
@ -1506,14 +1504,14 @@ else
if test "x$cross_compiling" = "xno"; then if test "x$cross_compiling" = "xno"; then
echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6 echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
echo "configure:1510: checking whether byte ordering is bigendian" >&5 echo "configure:1508: checking whether byte ordering is bigendian" >&5
if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
ac_cv_c_bigendian=unknown ac_cv_c_bigendian=unknown
# See if sys/param.h defines the BYTE_ORDER macro. # See if sys/param.h defines the BYTE_ORDER macro.
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 1517 "configure" #line 1515 "configure"
#include "confdefs.h" #include "confdefs.h"
#include <sys/types.h> #include <sys/types.h>
#include <sys/param.h> #include <sys/param.h>
@ -1524,11 +1522,11 @@ int main() {
#endif #endif
; return 0; } ; return 0; }
EOF EOF
if { (eval echo configure:1528: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then if { (eval echo configure:1526: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest* rm -rf conftest*
# It does; now see whether it defined to BIG_ENDIAN or not. # It does; now see whether it defined to BIG_ENDIAN or not.
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 1532 "configure" #line 1530 "configure"
#include "confdefs.h" #include "confdefs.h"
#include <sys/types.h> #include <sys/types.h>
#include <sys/param.h> #include <sys/param.h>
@ -1539,7 +1537,7 @@ int main() {
#endif #endif
; return 0; } ; return 0; }
EOF EOF
if { (eval echo configure:1543: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then if { (eval echo configure:1541: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest* rm -rf conftest*
ac_cv_c_bigendian=yes ac_cv_c_bigendian=yes
else else
@ -1559,7 +1557,7 @@ if test "$cross_compiling" = yes; then
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; } { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
else else
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 1563 "configure" #line 1561 "configure"
#include "confdefs.h" #include "confdefs.h"
main () { main () {
/* Are we little or big endian? From Harbison&Steele. */ /* Are we little or big endian? From Harbison&Steele. */
@ -1572,7 +1570,7 @@ main () {
exit (u.c[sizeof (long) - 1] == 1); exit (u.c[sizeof (long) - 1] == 1);
} }
EOF EOF
if { (eval echo configure:1576: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null if { (eval echo configure:1574: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
then then
ac_cv_c_bigendian=no ac_cv_c_bigendian=no
else else
@ -1634,6 +1632,7 @@ case "${target}" in
# start-sanitize-r5900 # start-sanitize-r5900
mips64r59*-*-*) SIMCONF="-mips3 --warnings -mcpu=r5900";; mips64r59*-*-*) SIMCONF="-mips3 --warnings -mcpu=r5900";;
# end-sanitize-r5900 # end-sanitize-r5900
mips64vr4100-*-*) SIMCOMF="-mips0 -mcpu=r4100 -mgp64 --warnings" ;;
mips64*-*-*) SIMCONF="-mips0 --warnings";; mips64*-*-*) SIMCONF="-mips0 --warnings";;
mips16*-*-*) SIMCONF="-mips0 --warnings";; mips16*-*-*) SIMCONF="-mips0 --warnings";;
mips*-*-*) SIMCONF="-mips2 --warnings";; mips*-*-*) SIMCONF="-mips2 --warnings";;
@ -1721,12 +1720,13 @@ fi
# #
# Select the bitsize of the target # Select the bitsize of the target
# #
mips_addr_bitsize=
case "${target}" in case "${target}" in
# start-sanitize-tx19 # start-sanitize-tx19
mipstx19*-*-*) mips_bitsize=32 ; mips_msb=31 ;; mipstx19*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
# end-sanitize-tx19 # end-sanitize-tx19
# start-sanitize-r5900 # start-sanitize-r5900
mips64r59*-*-*) mips_bitsize=64 ; mips_msb=63 ;; mips64r59*-*-*) mips_bitsize=64 ; mips_msb=63 ; mips_addr_bitsize=32;;
# end-sanitize-r5900 # end-sanitize-r5900
mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;; mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;; mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
@ -1735,7 +1735,7 @@ case "${target}" in
esac esac
wire_word_bitsize="$mips_bitsize" wire_word_bitsize="$mips_bitsize"
wire_word_msb="$mips_msb" wire_word_msb="$mips_msb"
wire_address_bitsize="" wire_address_bitsize="$mips_addr_bitsize"
wire_cell_bitsize="" wire_cell_bitsize=""
# Check whether --enable-sim-bitsize or --disable-sim-bitsize was given. # Check whether --enable-sim-bitsize or --disable-sim-bitsize was given.
if test "${enable_sim_bitsize+set}" = set; then if test "${enable_sim_bitsize+set}" = set; then
@ -1809,7 +1809,7 @@ case "${target}" in
mips_fpu_bitsize=32 mips_fpu_bitsize=32
;; ;;
# start-sanitize-r5900 # start-sanitize-r5900
mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ;; mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
# end-sanitize-r5900 # end-sanitize-r5900
mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;; mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;; mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
@ -1922,6 +1922,15 @@ case "${target}" in
sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5000" sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5000"
# end-sanitize-vr5400 # end-sanitize-vr5400
;; ;;
mips64vr4100-*-*) echo "NOTE: mips64vr4100 still uses gencode"
sim_default_gen=M16
sim_igen_machine="-M tx19"
sim_m16_machine="-M tx19"
sim_igen_filter = "32,64,f"
sim_m16_filter = "16"
sim_use_gen=NO
;;
mips64*-*-*) sim_default_gen=IGEN mips64*-*-*) sim_default_gen=IGEN
sim_igen_filter="32,64,f" sim_igen_filter="32,64,f"
sim_use_gen=IGEN sim_use_gen=IGEN
@ -1966,7 +1975,9 @@ fi
case "${target}" in case "${target}" in
# start-sanitize-sky # start-sanitize-sky
mips64r59*-sky-*) mips_extra_objs='$(SIM_SKY_OBJS)' ;; mips64r59*-sky-*) mips_extra_objs='$(SIM_SKY_OBJS)' ;
SIM_SUBTARGET="-DTARGET_SKY -DWITH_DEVICES=1 -DDEVICE_INIT=1";;
# end-sanitize-sky # end-sanitize-sky
*) mips_extra_objs="" ;; *) mips_extra_objs="" ;;
esac esac
@ -1977,17 +1988,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h
do do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:1981: checking for $ac_hdr" >&5 echo "configure:1992: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 1986 "configure" #line 1997 "configure"
#include "confdefs.h" #include "confdefs.h"
#include <$ac_hdr> #include <$ac_hdr>
EOF EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:1991: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } { (eval echo configure:2002: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out` ac_err=`grep -v '^ *+' conftest.out`
if test -z "$ac_err"; then if test -z "$ac_err"; then
rm -rf conftest* rm -rf conftest*
@ -2014,7 +2025,7 @@ fi
done done
echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6 echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
echo "configure:2018: checking for fabs in -lm" >&5 echo "configure:2029: checking for fabs in -lm" >&5
ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'` ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
@ -2022,7 +2033,7 @@ else
ac_save_LIBS="$LIBS" ac_save_LIBS="$LIBS"
LIBS="-lm $LIBS" LIBS="-lm $LIBS"
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 2026 "configure" #line 2037 "configure"
#include "confdefs.h" #include "confdefs.h"
/* Override any gcc2 internal prototype to avoid an error. */ /* Override any gcc2 internal prototype to avoid an error. */
/* We use char because int might match the return type of a gcc2 /* We use char because int might match the return type of a gcc2
@ -2033,7 +2044,7 @@ int main() {
fabs() fabs()
; return 0; } ; return 0; }
EOF EOF
if { (eval echo configure:2037: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then if { (eval echo configure:2048: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
rm -rf conftest* rm -rf conftest*
eval "ac_cv_lib_$ac_lib_var=yes" eval "ac_cv_lib_$ac_lib_var=yes"
else else
@ -2063,12 +2074,12 @@ fi
for ac_func in aint anint sqrt for ac_func in aint anint sqrt
do do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:2067: checking for $ac_func" >&5 echo "configure:2078: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6 echo $ac_n "(cached) $ac_c" 1>&6
else else
cat > conftest.$ac_ext <<EOF cat > conftest.$ac_ext <<EOF
#line 2072 "configure" #line 2083 "configure"
#include "confdefs.h" #include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes, /* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */ which can conflict with char $ac_func(); below. */
@ -2091,7 +2102,7 @@ $ac_func();
; return 0; } ; return 0; }
EOF EOF
if { (eval echo configure:2095: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then if { (eval echo configure:2106: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
rm -rf conftest* rm -rf conftest*
eval "ac_cv_func_$ac_func=yes" eval "ac_cv_func_$ac_func=yes"
else else
@ -2141,7 +2152,7 @@ EOF
# Ultrix sh set writes to stderr and can't be redirected directly, # Ultrix sh set writes to stderr and can't be redirected directly,
# and sets the high bit in the cache file unless we assign to the vars. # and sets the high bit in the cache file unless we assign to the vars.
(set) 2>&1 | (set) 2>&1 |
case `(ac_space=' '; set) 2>&1 | grep ac_space` in case `(ac_space=' '; set) 2>&1` in
*ac_space=\ *) *ac_space=\ *)
# `set' does not quote correctly, so add quotes (double-quote substitution # `set' does not quote correctly, so add quotes (double-quote substitution
# turns \\\\ into \\, and sed turns \\ into \). # turns \\\\ into \\, and sed turns \\ into \).
@ -2208,7 +2219,7 @@ do
echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
-version | --version | --versio | --versi | --vers | --ver | --ve | --v) -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
echo "$CONFIG_STATUS generated by autoconf version 2.12.1" echo "$CONFIG_STATUS generated by autoconf version 2.12"
exit 0 ;; exit 0 ;;
-help | --help | --hel | --he | --h) -help | --help | --hel | --he | --h)
echo "\$ac_cs_usage"; exit 0 ;; echo "\$ac_cs_usage"; exit 0 ;;
@ -2246,7 +2257,6 @@ s%@sim_smp@%$sim_smp%g
s%@sim_stdcall@%$sim_stdcall%g s%@sim_stdcall@%$sim_stdcall%g
s%@sim_xor_endian@%$sim_xor_endian%g s%@sim_xor_endian@%$sim_xor_endian%g
s%@sim_warnings@%$sim_warnings%g s%@sim_warnings@%$sim_warnings%g
s%@SHELL@%$SHELL%g
s%@CFLAGS@%$CFLAGS%g s%@CFLAGS@%$CFLAGS%g
s%@CPPFLAGS@%$CPPFLAGS%g s%@CPPFLAGS@%$CPPFLAGS%g
s%@CXXFLAGS@%$CXXFLAGS%g s%@CXXFLAGS@%$CXXFLAGS%g

7
sim/mips/configure.in
View file

@ -66,19 +66,20 @@ SIM_AC_OPTION_ENDIAN($mips_endian,$default_endian)
# #
# Select the bitsize of the target # Select the bitsize of the target
# #
mips_addr_bitsize=
case "${target}" in case "${target}" in
# start-sanitize-tx19 # start-sanitize-tx19
mipstx19*-*-*) mips_bitsize=32 ; mips_msb=31 ;; mipstx19*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
# end-sanitize-tx19 # end-sanitize-tx19
# start-sanitize-r5900 # start-sanitize-r5900
mips64r59*-*-*) mips_bitsize=64 ; mips_msb=63 ;; mips64r59*-*-*) mips_bitsize=64 ; mips_msb=63 ; mips_addr_bitsize=32;;
# end-sanitize-r5900 # end-sanitize-r5900
mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;; mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;; mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
mips*-*-*) mips_bitsize=32 ; mips_msb=31 ;; mips*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
*) mips_bitsize=64 ; mips_msb=63 ;; *) mips_bitsize=64 ; mips_msb=63 ;;
esac esac
SIM_AC_OPTION_BITSIZE($mips_bitsize,$mips_msb) SIM_AC_OPTION_BITSIZE($mips_bitsize,$mips_msb,$mips_addr_bitsize)
@ -95,7 +96,7 @@ case "${target}" in
mips_fpu_bitsize=32 mips_fpu_bitsize=32
;; ;;
# start-sanitize-r5900 # start-sanitize-r5900
mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ;; mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
# end-sanitize-r5900 # end-sanitize-r5900
mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;; mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;; mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;;

267
sim/mips/interp.c
View file

@ -305,6 +305,7 @@ sim_open (kind, cb, abfd, argv)
/* For compatibility with the old code - under this (at level one) /* For compatibility with the old code - under this (at level one)
are the kernel spaces K0 & K1. Both of these map to a single are the kernel spaces K0 & K1. Both of these map to a single
smaller sub region */ smaller sub region */
sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
K1BASE, K0SIZE, K1BASE, K0SIZE,
MEM_SIZE, /* actual size */ MEM_SIZE, /* actual size */
@ -367,7 +368,10 @@ sim_open (kind, cb, abfd, argv)
cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE; cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
else if ((rn >= 33) && (rn <= 37)) else if ((rn >= 33) && (rn <= 37))
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) else if ((rn == SRIDX)
|| (rn == FCR0IDX)
|| (rn == FCR31IDX)
|| ((rn >= 72) && (rn <= 89)))
cpu->register_widths[rn] = 32; cpu->register_widths[rn] = 32;
else else
cpu->register_widths[rn] = 0; cpu->register_widths[rn] = 0;
@ -605,7 +609,31 @@ sim_store_register (sd,rn,memory,length)
register number is for the architecture being simulated. */ register number is for the architecture being simulated. */
if (cpu->register_widths[rn] == 0) if (cpu->register_widths[rn] == 0)
sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); {
sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
return 0;
}
/* start-sanitize-r5900 */
if (rn >= 90 && rn < 90 + 32)
{
GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
return 8;
}
switch (rn)
{
case REGISTER_SA:
SA = T2H_8(*(unsigned64*)memory);
return 8;
case 122: /* FIXME */
LO1 = T2H_8(*(unsigned64*)memory);
return 8;
case 123: /* FIXME */
HI1 = T2H_8(*(unsigned64*)memory);
return 8;
}
/* end-sanitize-r5900 */
/* start-sanitize-sky */ /* start-sanitize-sky */
#ifdef TARGET_SKY #ifdef TARGET_SKY
else if( rn > NUM_R5900_REGS ) { else if( rn > NUM_R5900_REGS ) {
@ -628,25 +656,31 @@ sim_store_register (sd,rn,memory,length)
} }
#endif #endif
/* end-sanitize-sky */ /* end-sanitize-sky */
/* start-sanitize-r5900 */
else if (rn == REGISTER_SA) if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
SA = T2H_8(*(unsigned64*)memory);
else if (rn > LAST_EMBED_REGNUM)
cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(unsigned64*)memory);
/* end-sanitize-r5900 */
else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
{ {
if (cpu->register_widths[rn] == 32) if (cpu->register_widths[rn] == 32)
cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); {
cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
return 4;
}
else else
cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory); {
cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
return 8;
}
} }
else if (cpu->register_widths[rn] == 32)
cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
else
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
return -1; if (cpu->register_widths[rn] == 32)
{
cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
return 4;
}
else
{
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
return 8;
}
} }
int int
@ -664,10 +698,34 @@ sim_fetch_register (sd,rn,memory,length)
#endif /* DEBUG */ #endif /* DEBUG */
if (cpu->register_widths[rn] == 0) if (cpu->register_widths[rn] == 0)
sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn); {
sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
return 0;
}
/* start-sanitize-r5900 */
if (rn >= 90 && rn < 90 + 32)
{
*(unsigned64*)memory = GPR1[rn - 90];
return 8;
}
switch (rn)
{
case REGISTER_SA:
*((unsigned64*)memory) = H2T_8(SA);
return 8;
case 122: /* FIXME */
*((unsigned64*)memory) = H2T_8(LO1);
return 8;
case 123: /* FIXME */
*((unsigned64*)memory) = H2T_8(HI1);
return 8;
}
/* end-sanitize-r5900 */
/* start-sanitize-sky */ /* start-sanitize-sky */
#ifdef TARGET_SKY #ifdef TARGET_SKY
else if( rn > NUM_R5900_REGS ) { if( rn > NUM_R5900_REGS ) {
rn = rn - NUM_R5900_REGS; rn = rn - NUM_R5900_REGS;
if( rn < 16 ) if( rn < 16 )
@ -684,28 +742,37 @@ sim_fetch_register (sd,rn,memory,length)
else else
sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" ); sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
} }
return -1;
} }
#endif #endif
/* end-sanitize-sky */ /* end-sanitize-sky */
/* start-sanitize-r5900 */
else if (rn == REGISTER_SA) /* Any floating point register */
*((unsigned64*)memory) = H2T_8(SA); if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
else if (rn > LAST_EMBED_REGNUM)
*((unsigned64*)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
/* end-sanitize-r5900 */
else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
{ {
if (cpu->register_widths[rn] == 32) if (cpu->register_widths[rn] == 32)
*(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]); {
*(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
return 4;
}
else else
*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]); {
*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
return 8;
}
} }
else if (cpu->register_widths[rn] == 32)
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
else /* 64bit register */
*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
return -1; if (cpu->register_widths[rn] == 32)
{
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
return 4;
}
else
{
*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
return 8;
}
} }
@ -2856,6 +2923,142 @@ SquareRoot(op,fmt)
return(result); return(result);
} }
uword64
Max (uword64 op1,
uword64 op2,
FP_formats fmt)
{
int cmp;
unsigned64 result;
#ifdef DEBUG
printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
/* The format type should already have been checked: */
switch (fmt)
{
case fmt_single:
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
cmp = sim_fpu_cmp (&wop1, &wop2);
break;
}
case fmt_double:
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
cmp = sim_fpu_cmp (&wop1, &wop2);
break;
}
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
switch (cmp)
{
case SIM_FPU_IS_SNAN:
case SIM_FPU_IS_QNAN:
result = op1;
case SIM_FPU_IS_NINF:
case SIM_FPU_IS_NNUMBER:
case SIM_FPU_IS_NDENORM:
case SIM_FPU_IS_NZERO:
result = op2; /* op1 - op2 < 0 */
case SIM_FPU_IS_PINF:
case SIM_FPU_IS_PNUMBER:
case SIM_FPU_IS_PDENORM:
case SIM_FPU_IS_PZERO:
result = op1; /* op1 - op2 > 0 */
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
#ifdef DEBUG
printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
uword64
Min (uword64 op1,
uword64 op2,
FP_formats fmt)
{
int cmp;
unsigned64 result;
#ifdef DEBUG
printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
/* The format type should already have been checked: */
switch (fmt)
{
case fmt_single:
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
cmp = sim_fpu_cmp (&wop1, &wop2);
break;
}
case fmt_double:
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
cmp = sim_fpu_cmp (&wop1, &wop2);
break;
}
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
switch (cmp)
{
case SIM_FPU_IS_SNAN:
case SIM_FPU_IS_QNAN:
result = op1;
case SIM_FPU_IS_NINF:
case SIM_FPU_IS_NNUMBER:
case SIM_FPU_IS_NDENORM:
case SIM_FPU_IS_NZERO:
result = op1; /* op1 - op2 < 0 */
case SIM_FPU_IS_PINF:
case SIM_FPU_IS_PNUMBER:
case SIM_FPU_IS_PDENORM:
case SIM_FPU_IS_PZERO:
result = op2; /* op1 - op2 > 0 */
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
#ifdef DEBUG
printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
uword64 uword64
convert (SIM_DESC sd, convert (SIM_DESC sd,
sim_cpu *cpu, sim_cpu *cpu,

194
sim/mips/mdmx.igen
View file

@ -26,7 +26,11 @@
// If valid, return the scale (log nr bits) of a vector element // If valid, return the scale (log nr bits) of a vector element
// as determined by SEL. // as determined by SEL.
:function:::int:get_scale:int sel :function:64,f::int:get_scale:int sel
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
#if 0 #if 0
switch (my_index X STATE_ARCHITECTURE) switch (my_index X STATE_ARCHITECTURE)
@ -63,7 +67,11 @@
// Fetch/Store VALUE in ELEMENT of vector register FPR. // Fetch/Store VALUE in ELEMENT of vector register FPR.
// The the of the element determined by SCALE. // The the of the element determined by SCALE.
:function:::signed:value_vr:int scale, int fpr, int el :function:64,f::signed:value_vr:int scale, int fpr, int el
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
switch (FPR_STATE[fpr]) switch (FPR_STATE[fpr])
{ {
@ -96,7 +104,11 @@
return 0; return 0;
} }
:function:::void:store_vr:int scale, int fpr, int element, signed value :function:64,f::void:store_vr:int scale, int fpr, int element, signed value
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
switch (FPR_STATE[fpr]) switch (FPR_STATE[fpr])
{ {
@ -132,7 +144,11 @@
// Select a value from onr of FGR[VT][ELEMENT], VT and GFR[VT][CONST] // Select a value from onr of FGR[VT][ELEMENT], VT and GFR[VT][CONST]
// according to SEL // according to SEL
:function:::unsigned:select_vr:int sel, int vt, int element :function:64,f::unsigned:select_vr:int sel, int vt, int element
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
switch (sel) switch (sel)
{ {
@ -182,7 +198,11 @@
// Saturate (clamp) the signed value to (8 << SCALE) bits. // Saturate (clamp) the signed value to (8 << SCALE) bits.
:function:::signed:Clamp:int scale, signed value :function:64,f::signed:Clamp:int scale, signed value
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
switch (scale) switch (scale)
{ {
@ -217,12 +237,20 @@
// Access a single bit of the floating point CC register. // Access a single bit of the floating point CC register.
:function:::void:store_cc:int i, int value :function:64,f::void:store_cc:int i, int value
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
SETFCC (i, value); SETFCC (i, value);
} }
:function:::int:value_cc:int i :function:64,f::int:value_cc:int i
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
return GETFCC (i); return GETFCC (i);
} }
@ -230,7 +258,11 @@
// Read/write the accumulator // Read/write the accumulator
:function:::signed64:value_acc:int scale, int element :function:64,f::signed64:value_acc:int scale, int element
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
signed64 value = 0; signed64 value = 0;
switch (scale) switch (scale)
@ -252,7 +284,11 @@
return value; return value;
} }
:function:::void:store_acc:int scale, int element, signed64 value :function:64,f::void:store_acc:int scale, int element, signed64 value
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
switch (scale) switch (scale)
{ {
@ -275,7 +311,11 @@
// Formatting // Formatting
:%s::::VT:int sel, int vt :%s:64,f:::VT:int sel, int vt
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
static char buf[20]; static char buf[20];
if (sel < 8) if (sel < 8)
@ -289,7 +329,11 @@
return buf; return buf;
} }
:%s::::SEL:int sel :%s:64,f:::SEL:int sel
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
switch (sel & 7) switch (sel & 7)
{ {
@ -311,7 +355,7 @@
// Vector Add. // Vector Add.
010010,5.SEL,5.VT,5.VS,5.VD,001011::::ADD.fmt 010010,5.SEL,5.VT,5.VS,5.VD,001011::64,f::ADD.fmt
"add.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "add.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -330,7 +374,7 @@
// Accumulate Vector Add // Accumulate Vector Add
010010,5.SEL,5.VT,5.VS,1,0000,110111::::ADDA.fmt 010010,5.SEL,5.VT,5.VS,1,0000,110111::64,f::ADDA.fmt
"adda.%s<SEL> v<VD>, v<VS>" "adda.%s<SEL> v<VD>, v<VS>"
*mdmx: *mdmx:
{ {
@ -346,7 +390,7 @@
// Load Vector Add // Load Vector Add
010010,5.SEL,5.VT,5.VS,0,0000,110111::::ADDA.fmt 010010,5.SEL,5.VT,5.VS,0,0000,110111::64,f::ADDA.fmt
"addl.%s<SEL> v<VD>, v<VS>" "addl.%s<SEL> v<VD>, v<VS>"
*mdmx: *mdmx:
{ {
@ -362,7 +406,11 @@
// Vector align, Constant Alignment // Vector align, Constant Alignment
:function:::void:ByteAlign:int vd, int imm, int vs, int vt :function:64,f::void:ByteAlign:int vd, int imm, int vs, int vt
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
int s = imm * 8; int s = imm * 8;
unsigned64 rs = ValueFPR (vs, fmt_long); unsigned64 rs = ValueFPR (vs, fmt_long);
@ -389,7 +437,7 @@
StoreFPR (vd, fmt_long, rd); StoreFPR (vd, fmt_long, rd);
} }
010010,00,3.IMM,5.VT,5.VS,5.VD,0110,X,0::::ALNI.fmt 010010,00,3.IMM,5.VT,5.VS,5.VD,0110,X,0::64,f::ALNI.fmt
"alni.%s<FMT#X> v<VD>, v<VS>, v<VT>, <IMM>" "alni.%s<FMT#X> v<VD>, v<VS>, v<VT>, <IMM>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -403,7 +451,7 @@
// Vector align, Variable Alignment // Vector align, Variable Alignment
010010,5.RS,5.VT,5.VS,5.VD,0110,X,1::::ALNV.fmt 010010,5.RS,5.VT,5.VS,5.VD,0110,X,1::64,f::ALNV.fmt
"alnv.%s<FMT#X> v<VD>, v<VS>, v<VT>, r<RS>" "alnv.%s<FMT#X> v<VD>, v<VS>, v<VT>, r<RS>"
*mdmx: *mdmx:
{ {
@ -414,7 +462,7 @@
// Vector And. // Vector And.
010010,5.SEL,5.VT,5.VS,5.VD,001100::::AND.fmt 010010,5.SEL,5.VT,5.VS,5.VD,001100::64,f::AND.fmt
"and.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "and.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -434,7 +482,7 @@
// Vector Compare Equal. // Vector Compare Equal.
010010,5.SEL,5.VT,5.VS,00000,000001::::C.EQ.fmt 010010,5.SEL,5.VT,5.VS,00000,000001::64,f::C.EQ.fmt
"c.EQ.%s<SEL> v<VS>, %s<VT#SEL,VT>" "c.EQ.%s<SEL> v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -453,7 +501,7 @@
// Vector Compare Less Than or Equal. // Vector Compare Less Than or Equal.
010010,5.SEL,5.VT,5.VS,00000,000101::::C.LE.fmt 010010,5.SEL,5.VT,5.VS,00000,000101::64,f::C.LE.fmt
"c.le.%s<SEL> v<VS>, %s<VT#SEL,VT>" "c.le.%s<SEL> v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -472,7 +520,7 @@
// Vector Compare Less Than. // Vector Compare Less Than.
010010,5.SEL,5.VT,5.VS,00000,000100::::C.LT.fmt 010010,5.SEL,5.VT,5.VS,00000,000100::64,f::C.LT.fmt
"c.lt.%s<SEL> v<VS>, %s<VT#SEL,VT>" "c.lt.%s<SEL> v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -491,7 +539,11 @@
// Vector Maximum. // Vector Maximum.
:function:::signed:Max:int scale, signed l, signed r :function:64,f::signed:Max:int scale, signed l, signed r
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
if (l < r) if (l < r)
return r; return r;
@ -499,7 +551,7 @@
return l; return l;
} }
010010,5.SEL,5.VT,5.VS,5.VD,000111::::MAX.fmt 010010,5.SEL,5.VT,5.VS,5.VD,000111::64,f::MAX.fmt
"max.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "max.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -519,7 +571,11 @@
// Vector Minimum. // Vector Minimum.
:function:::signed:Min:int scale, signed l, signed r :function:64,f::signed:Min:int scale, signed l, signed r
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
if (l < r) if (l < r)
return l; return l;
@ -527,7 +583,7 @@
return r; return r;
} }
010010,5.SEL,5.VT,5.VS,5.VD,000110::::MIN.fmt 010010,5.SEL,5.VT,5.VS,5.VD,000110::64,f::MIN.fmt
"min.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "min.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -547,7 +603,11 @@
// Vector Sign. // Vector Sign.
:function:::signed:Sign:int scale, signed l, signed r :function:64,f::signed:Sign:int scale, signed l, signed r
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
if (l >= 0) if (l >= 0)
return r; return r;
@ -575,7 +635,7 @@
} }
} }
010010,5.SEL,5.VT,5.VS,5.VD,000110::::MSGN.fmt 010010,5.SEL,5.VT,5.VS,5.VD,000110::64,f::MSGN.fmt
"msgn.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "msgn.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
{ {
@ -595,7 +655,7 @@
// Vector Multiply. // Vector Multiply.
010010,5.SEL,5.VT,5.VS,5.VD,110000::::MUL.fmt 010010,5.SEL,5.VT,5.VS,5.VD,110000::64,f::MUL.fmt
"mul.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "mul.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -615,7 +675,7 @@
// Accumulate Vector Multiply // Accumulate Vector Multiply
010010,5.SEL,5.VT,5.VS,00000,110011::::MULA.fmt 010010,5.SEL,5.VT,5.VS,00000,110011::64,f::MULA.fmt
"mula.%s<SEL> v<VS>, %s<VT#SEL,VT>" "mula.%s<SEL> v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -635,7 +695,7 @@
// Add Vector Multiply to Accumulator. // Add Vector Multiply to Accumulator.
010010,5.SEL,5.VT,5.VS,10000,110011::::MULL.fmt 010010,5.SEL,5.VT,5.VS,10000,110011::64,f::MULL.fmt
"mull.%s<SEL> v<VS>, %s<VT#SEL,VT>" "mull.%s<SEL> v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -654,7 +714,7 @@
// Subtract Vector Multiply from Accumulator // Subtract Vector Multiply from Accumulator
010010,5.SEL,5.VT,5.VS,00000,110010::::MULS.fmt 010010,5.SEL,5.VT,5.VS,00000,110010::64,f::MULS.fmt
"muls.%s<SEL> v<VS>, %s<VT#SEL,VT>" "muls.%s<SEL> v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -674,7 +734,7 @@
// Load Negative Vector Multiply // Load Negative Vector Multiply
010010,5.SEL,5.VT,5.VS,10000,110010::::MULSL.fmt 010010,5.SEL,5.VT,5.VS,10000,110010::64,f::MULSL.fmt
"mulsl.%s<SEL> v<VS>, %s<VT#SEL,VT>" "mulsl.%s<SEL> v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -693,7 +753,7 @@
// Vector Nor. // Vector Nor.
010010,5.SEL,5.VT,5.VS,5.VD,001111::::NOR.fmt 010010,5.SEL,5.VT,5.VS,5.VD,001111::64,f::NOR.fmt
"nor.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "nor.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -712,7 +772,7 @@
// Vector Or. // Vector Or.
010010,5.SEL,5.VT,5.VS,5.VD,001110::::OR.fmt 010010,5.SEL,5.VT,5.VS,5.VD,001110::64,f::OR.fmt
"or.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "or.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -731,7 +791,7 @@
// Select Vector Elements - False // Select Vector Elements - False
010010,5.SEL,5.VT,5.VS,5.VD,000010::::PICKF.fmt 010010,5.SEL,5.VT,5.VS,5.VD,000010::64,f::PICKF.fmt
"pickf.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "pickf.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -751,7 +811,7 @@
// Select Vector Elements - True // Select Vector Elements - True
010010,5.SEL,5.VT,5.VS,5.VD,000011::::PICKT.fmt 010010,5.SEL,5.VT,5.VS,5.VD,000011::64,f::PICKT.fmt
"pickt.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "pickt.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -771,7 +831,11 @@
// Scale, Round and Clamp Accumulator // Scale, Round and Clamp Accumulator
:%s::::RND:int rnd :%s:64,f:::RND:int rnd
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
switch (rnd) switch (rnd)
{ {
@ -792,7 +856,11 @@
} }
} }
:function:::signed:ScaleRoundClamp:int scale, int rnd, signed val, signed shift :function:64,f::signed:ScaleRoundClamp:int scale, int rnd, signed val, signed shift
*mdmx:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
{ {
int halfway = (1 << (shift - 1)); int halfway = (1 << (shift - 1));
/* must be positive */ /* must be positive */
@ -871,7 +939,7 @@
return val; return val;
} }
010010,5.SEL,5.VT,00000,5.VD,100,3.RND::::Rx.fmt 010010,5.SEL,5.VT,00000,5.VD,100,3.RND::64,f::Rx.fmt
"r%s<RND>.%s<SEL> v<VD>, v<VT>" "r%s<RND>.%s<SEL> v<VD>, v<VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -891,7 +959,7 @@
// Vector Read Accumulator Low. // Vector Read Accumulator Low.
010010,0000,1.SEL,00000,00000,5.VD,111111::::RACL.fmt 010010,0000,1.SEL,00000,00000,5.VD,111111::64,f::RACL.fmt
"racl.%s<SEL> v<VD>" "racl.%s<SEL> v<VD>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -911,7 +979,7 @@
// Vector Read Accumulator Middle. // Vector Read Accumulator Middle.
010010,0100,1.SEL,00000,00000,5.VD,111111::::RACM.fmt 010010,0100,1.SEL,00000,00000,5.VD,111111::64,f::RACM.fmt
"racm.%s<SEL> v<VD>" "racm.%s<SEL> v<VD>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -931,7 +999,7 @@
// Vector Read Accumulator High. // Vector Read Accumulator High.
010010,1000,1.SEL,00000,00000,5.VD,111111::::RACH.fmt 010010,1000,1.SEL,00000,00000,5.VD,111111::64,f::RACH.fmt
"rach.%s<SEL> v<VD>" "rach.%s<SEL> v<VD>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -951,7 +1019,7 @@
// Vector Element Shuffle. // Vector Element Shuffle.
010010,0000,0,5.VT,5.VS,5.VD,011111::::SHFL.UPUH.fmt 010010,0000,0,5.VT,5.VS,5.VD,011111::64,f::SHFL.UPUH.fmt
"shfl.upuh.%s<SEL> v<VD>, v<VS>, <VT>" "shfl.upuh.%s<SEL> v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
{ {
@ -964,7 +1032,7 @@
} }
} }
010010,0001,0,5.VT,5.VS,5.VD,011111::::SHFL.UPUL.fmt 010010,0001,0,5.VT,5.VS,5.VD,011111::64,f::SHFL.UPUL.fmt
"shfl.upul.%s<SEL> v<VD>, v<VS>, <VT>" "shfl.upul.%s<SEL> v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
{ {
@ -976,7 +1044,7 @@
} }
} }
010010,0000,0,5.VT,5.VS,5.VD,011111::::SHFL.UPSH.fmt 010010,0000,0,5.VT,5.VS,5.VD,011111::64,f::SHFL.UPSH.fmt
"shfl.upsh.%s<SEL> v<VD>, v<VS>, <VT>" "shfl.upsh.%s<SEL> v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
{ {
@ -989,7 +1057,7 @@
} }
} }
010010,0001,0,5.VT,5.VS,5.VD,011111::::SHFL.UPSL.fmt 010010,0001,0,5.VT,5.VS,5.VD,011111::64,f::SHFL.UPSL.fmt
"shfl.upsl.%s<SEL> v<VD>, v<VS>, <VT>" "shfl.upsl.%s<SEL> v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
{ {
@ -1001,7 +1069,7 @@
} }
} }
010010,0100,1.SEL,5.VT,5.VS,5.VD,011111::::SHFL.PACH.fmt 010010,0100,1.SEL,5.VT,5.VS,5.VD,011111::64,f::SHFL.PACH.fmt
"shfl.pach.%s<SEL> v<VD>, v<VS>, <VT>" "shfl.pach.%s<SEL> v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1019,7 +1087,7 @@
} }
} }
010010,0101,1.SEL,5.VT,5.VS,5.VD,011111::::SHFL.PACL.fmt 010010,0101,1.SEL,5.VT,5.VS,5.VD,011111::64,f::SHFL.PACL.fmt
"shfl.pacl.%s<SEL> v<VD>, v<VS>, <VT>" "shfl.pacl.%s<SEL> v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1037,7 +1105,7 @@
} }
} }
010010,0110,1.SEL,5.VT,5.VS,5.VD,011111::::SHFL.MIXH.fmt 010010,0110,1.SEL,5.VT,5.VS,5.VD,011111::64,f::SHFL.MIXH.fmt
"shfl.mixh.%s<SEL> v<VD>, v<VS>, <VT>" "shfl.mixh.%s<SEL> v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1055,7 +1123,7 @@
} }
} }
010010,0111,1.SEL,5.VT,5.VS,5.VD,011111::::SHFL.MIXL.fmt 010010,0111,1.SEL,5.VT,5.VS,5.VD,011111::64,f::SHFL.MIXL.fmt
"shfl.mixl.%s<SEL> v<VD>, v<VS>, <VT>" "shfl.mixl.%s<SEL> v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1073,7 +1141,7 @@
} }
} }
010010,100,01,5.VT,5.VS,5.VD,011111::::SHFL.BFLA.fmt 010010,100,01,5.VT,5.VS,5.VD,011111::64,f::SHFL.BFLA.fmt
"shfl.bfla.qh v<VD>, v<VS>, <VT>" "shfl.bfla.qh v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
{ {
@ -1087,7 +1155,7 @@
value_vr (SD_, 1, VS, 2)); value_vr (SD_, 1, VS, 2));
} }
010010,101,01,5.VT,5.VS,5.VD,011111::::SHFL.BFLB.fmt 010010,101,01,5.VT,5.VS,5.VD,011111::64,f::SHFL.BFLB.fmt
"shfl.bflb.qh v<VD>, v<VS>, <VT>" "shfl.bflb.qh v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
{ {
@ -1101,7 +1169,7 @@
value_vr (SD_, 1, VS, 0)); value_vr (SD_, 1, VS, 0));
} }
010010,101,01,5.VT,5.VS,5.VD,011111::::SHFL.REPA.fmt 010010,101,01,5.VT,5.VS,5.VD,011111::64,f::SHFL.REPA.fmt
"shfl.repa.qh v<VD>, v<VS>, <VT>" "shfl.repa.qh v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
{ {
@ -1115,7 +1183,7 @@
value_vr (SD_, 1, VS, 3)); value_vr (SD_, 1, VS, 3));
} }
010010,101,01,5.VT,5.VS,5.VD,011111::::SHFL.REPB.fmt 010010,101,01,5.VT,5.VS,5.VD,011111::64,f::SHFL.REPB.fmt
"shfl.repb.qh v<VD>, v<VS>, <VT>" "shfl.repb.qh v<VD>, v<VS>, <VT>"
*mdmx: *mdmx:
{ {
@ -1133,7 +1201,7 @@
// Vector Shift Left Logical // Vector Shift Left Logical
010010,5.SEL,5.VT,5.VS,5.VD,010000::::SLL.fmt 010010,5.SEL,5.VT,5.VS,5.VD,010000::64,f::SLL.fmt
"sll.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "sll.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1153,7 +1221,7 @@
// Vector Shift Right Arithmetic // Vector Shift Right Arithmetic
010010,5.SEL,5.VT,5.VS,5.VD,010011::::SRA.fmt 010010,5.SEL,5.VT,5.VS,5.VD,010011::64,f::SRA.fmt
"sra.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "sra.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
{ {
@ -1170,7 +1238,7 @@
// Vector Shift Right Logical. // Vector Shift Right Logical.
010010,5.SEL,5.VT,5.VS,5.VD,010010::::SRL.fmt 010010,5.SEL,5.VT,5.VS,5.VD,010010::64,f::SRL.fmt
"srl.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "srl.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1191,7 +1259,7 @@
// Vector Subtract. // Vector Subtract.
010010,5.SEL,5.VT,5.VS,5.VD,001010::::SUB.fmt 010010,5.SEL,5.VT,5.VS,5.VD,001010::64,f::SUB.fmt
"sub.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "sub.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1210,7 +1278,7 @@
// Accumulate Vector Difference // Accumulate Vector Difference
010010,5.SEL,5.VT,5.VS,0,0000,110110::::SUBA.fmt 010010,5.SEL,5.VT,5.VS,0,0000,110110::64,f::SUBA.fmt
"suba.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "suba.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
{ {
@ -1227,7 +1295,7 @@
// Load Vector Difference // Load Vector Difference
010010,5.SEL,5.VT,5.VS,1,0000,110110::::SUBL.fmt 010010,5.SEL,5.VT,5.VS,1,0000,110110::64,f::SUBL.fmt
"subl.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "subl.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
{ {
@ -1243,7 +1311,7 @@
// Write Accumulator High. // Write Accumulator High.
010010,1000,1.SEL,00000,5.VS,00000,111110::::WACH.fmt 010010,1000,1.SEL,00000,5.VS,00000,111110::64,f::WACH.fmt
"wach.%s<SEL> v<VS>" "wach.%s<SEL> v<VS>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1262,7 +1330,7 @@
// Vector Write Accumulator Low. // Vector Write Accumulator Low.
010010,0000,1.SEL,5.VT,5.VS,00000,111110::::WACL.fmt 010010,0000,1.SEL,5.VT,5.VS,00000,111110::64,f::WACL.fmt
"wacl.%s<SEL> v<VS>, <VT>" "wacl.%s<SEL> v<VS>, <VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400
@ -1282,7 +1350,7 @@
// Vector Xor. // Vector Xor.
010010,5.SEL,5.VT,5.VS,5.VD,001101::::XOR.fmt 010010,5.SEL,5.VT,5.VS,5.VD,001101::64,f::XOR.fmt
"xor.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>" "xor.%s<SEL> v<VD>, v<VS>, %s<VT#SEL,VT>"
*mdmx: *mdmx:
// start-sanitize-vr5400 // start-sanitize-vr5400

93
sim/mips/mips.igen
View file

@ -12,14 +12,14 @@
// IGEN config - mips16 // IGEN config - mips16
:option:16::insn-bit-size:16 // :option:16::insn-bit-size:16
:option:16::hi-bit-nr:15 // :option:16::hi-bit-nr:15
:option:16::insn-specifying-widths:true :option:16::insn-specifying-widths:true
:option:16::gen-delayed-branch:false :option:16::gen-delayed-branch:false
// IGEN config - mips32/64.. // IGEN config - mips32/64..
:option:32::insn-bit-size:32 // :option:32::insn-bit-size:32
:option:32::hi-bit-nr:31 // :option:32::hi-bit-nr:31
:option:32::insn-specifying-widths:true :option:32::insn-specifying-widths:true
:option:32::gen-delayed-branch:false :option:32::gen-delayed-branch:false
@ -35,17 +35,17 @@
:model:::mipsIV:mipsIV: :model:::mipsIV:mipsIV:
:model:::mips16:mips16: :model:::mips16:mips16:
// start-sanitize-r5900 // start-sanitize-r5900
:model:::r5900:r5900: :model:::r5900:mips5900:
// end-sanitize-r5900 // end-sanitize-r5900
:model:::r3900:r3900: :model:::r3900:mips3900:
// start-sanitize-tx19 // start-sanitize-tx19
:model:::tx19:tx19: :model:::tx19:tx19:
// end-sanitize-tx19 // end-sanitize-tx19
// start-sanitize-vr5400 // start-sanitize-vr5400
:model:::vr5400:vr5400: :model:::vr5400:mips5400:
:model:::mdmx:mdmx: :model:::mdmx:mdmx:
// end-sanitize-vr5400 // end-sanitize-vr5400
:model:::vr5000:vr5000: :model:::vr5000:mips5000:
@ -1258,6 +1258,25 @@
} }
:function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
{
address_word vaddr = offset + gpr_base;
address_word paddr;
int uncached;
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
{
unsigned64 memval = 0;
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
unsigned int reverse = (ReverseEndian ? mask : 0);
unsigned int bigend = (BigEndianCPU ? mask : 0);
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
byte = ((vaddr & mask) ^ bigend);
GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
}
}
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)" "lb r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV: *mipsI,mipsII,mipsIII,mipsIV:
@ -1273,6 +1292,8 @@
*tx19: *tx19:
// end-sanitize-tx19 // end-sanitize-tx19
{ {
do_load_byte (SD_, GPR[BASE], RT, OFFSET);
#if 0
unsigned32 instruction = instruction_0; unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
int destreg = ((instruction >> 16) & 0x0000001F); int destreg = ((instruction >> 16) & 0x0000001F);
@ -1298,6 +1319,7 @@
} }
} }
} }
#endif
} }
@ -3430,9 +3452,6 @@
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -3452,16 +3471,13 @@
010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>" "add.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV: *mipsI,mipsII,mipsIII,mipsIV:
*vr5000: *vr5000:
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -3494,14 +3510,22 @@
*r5900: *r5900:
// end-sanitize-r5900 // end-sanitize-r5900
{ {
TRACE_BRANCH_INPUT (PREVCOC1());
if (PREVCOC1() == TF) if (PREVCOC1() == TF)
{ {
DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2)); address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
TRACE_BRANCH_RESULT (dest);
DELAY_SLOT (dest);
} }
else if (ND) else if (ND)
{ {
TRACE_BRANCH_RESULT (0);
NULLIFY_NEXT_INSTRUCTION (); NULLIFY_NEXT_INSTRUCTION ();
} }
else
{
TRACE_BRANCH_RESULT (NIA);
}
} }
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
@ -3584,9 +3608,6 @@
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -3841,9 +3862,6 @@
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -4133,16 +4151,13 @@
// //
// FIXME: Not correct for mips* // FIXME: Not correct for mips*
// //
010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
"madd.d f<FD>, f<FR>, f<FS>, f<FT>" "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV: *mipsIV:
*vr5000: *vr5000:
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
{ {
unsigned32 instruction = instruction_0; unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F); int destreg = ((instruction >> 6) & 0x0000001F);
@ -4155,16 +4170,13 @@
} }
010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
"madd.s f<FD>, f<FR>, f<FS>, f<FT>" "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV: *mipsIV:
*vr5000: *vr5000:
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
{ {
unsigned32 instruction = instruction_0; unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F); int destreg = ((instruction >> 6) & 0x0000001F);
@ -4202,9 +4214,6 @@
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -4225,9 +4234,6 @@
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -4387,9 +4393,6 @@
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -4416,9 +4419,6 @@
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -4739,9 +4739,6 @@
// start-sanitize-vr5400 // start-sanitize-vr5400
*vr5400: *vr5400:
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900: *r3900:
// start-sanitize-tx19 // start-sanitize-tx19
*tx19: *tx19:
@ -5099,10 +5096,10 @@
// end-sanitize-r5900 // end-sanitize-r5900
:include:::m16.igen :include:16::m16.igen
// start-sanitize-vr5400 // start-sanitize-vr5400
:include::vr5400:vr5400.igen :include::vr5400:vr5400.igen
:include:::mdmx.igen :include:64,f::mdmx.igen
// end-sanitize-vr5400 // end-sanitize-vr5400
// start-sanitize-r5900 // start-sanitize-r5900
:include::r5900:r5900.igen :include::r5900:r5900.igen
@ -5206,4 +5203,4 @@
// } // }
// } // }
// start-sanitize-cygnus-never // end-sanitize-cygnus-never

147
sim/mips/sim-main.h
View file

@ -111,6 +111,8 @@ unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt)); unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt)); unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to)); unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
#define Convert(rm,op,from,to) \ #define Convert(rm,op,from,to) \
convert (SD, CPU, cia, rm, op, from, to) convert (SD, CPU, cia, rm, op, from, to)
@ -131,7 +133,7 @@ convert (SD, CPU, cia, rm, op, from, to)
#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0) #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
#if 1 #if 1
#define SizeFGR() (WITH_TARGET_WORD_BITSIZE) #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
#else #else
/* They depend on the CPU being simulated */ /* They depend on the CPU being simulated */
#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32) #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
@ -183,8 +185,55 @@ convert (SD, CPU, cia, rm, op, from, to)
SignalExceptionIntegerOverflow (); \ SignalExceptionIntegerOverflow (); \
(ANS) = ALU64_OVERFLOW_RESULT; (ANS) = ALU64_OVERFLOW_RESULT;
/* start-sanitize-r5900 */ /* start-sanitize-r5900 */
typedef struct _sim_r5900_cpu {
/* The R5900 has 32 x 128bit general purpose registers.
Fortunatly, the high 64 bits are only touched by multimedia (MMI)
instructions. The normal mips instructions just use the lower 64
bits. To avoid changing the older parts of the simulator to
handle this weirdness, the high 64 bits of each register are kept
in a separate array (registers1). The high 64 bits of any
register are by convention refered by adding a '1' to the end of
the normal register's name. So LO still refers to the low 64
bits of the LO register, LO1 refers to the high 64 bits of that
same register. */
signed_word gpr1[32];
#define GPR1 ((CPU)->r5900.gpr1)
signed_word lo1;
signed_word hi1;
#define LO1 ((CPU)->r5900.lo1)
#define HI1 ((CPU)->r5900.hi1)
/* The R5900 defines a shift amount register, that controls the
amount of certain shift instructions */
unsigned_word sa; /* the shift amount register */
#define REGISTER_SA (124) /* GET RID IF THIS! */
#define SA ((CPU)->r5900.sa)
/* The R5900, in addition to the (almost) standard floating point
registers, defines a 32 bit accumulator. This is used in
multiply/accumulate style instructions */
fp_word acc; /* floating-point accumulator */
#define ACC ((CPU)->r5900.acc)
/* See comments below about needing to count cycles between updating
and setting HI/LO registers */
int hi1access;
int lo1access;
#define HI1ACCESS ((CPU)->r5900.hi1access)
#define LO1ACCESS ((CPU)->r5900.lo1access)
#if 0
#define CHECKHILO(s) {\
if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
}
#endif
} sim_r5900_cpu;
#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word)) #define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2) #define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4) #define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
@ -228,15 +277,15 @@ GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I) #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I) #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
#define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I) #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
#define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I) #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
#define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I) #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
#define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I) #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
#define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I) #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
#define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I) #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
#define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I) #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
#define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I) #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I) #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
@ -377,9 +426,9 @@ struct _sim_cpu {
address_word target = (TARGET); \ address_word target = (TARGET); \
instruction_word delay_insn; \ instruction_word delay_insn; \
sim_events_slip (SD, 1); \ sim_events_slip (SD, 1); \
CIA = CIA + 4; \ CIA = CIA + 4; /* NOTE not mips16 */ \
STATE |= simDELAYSLOT; \ STATE |= simDELAYSLOT; \
delay_insn = IMEM (CIA); \ delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
idecode_issue (CPU_, delay_insn, (CIA)); \ idecode_issue (CPU_, delay_insn, (CIA)); \
STATE &= ~simDELAYSLOT; \ STATE &= ~simDELAYSLOT; \
NIA = target; \ NIA = target; \
@ -443,6 +492,21 @@ struct _sim_cpu {
/* end-sanitize-r5900 */ /* end-sanitize-r5900 */
#endif #endif
/* start-sanitize-sky */
#ifdef TARGET_SKY
#ifndef TM_TXVU_H
/* Number of machine registers */
#define NUM_VU_REGS 152
#define NUM_R5900_REGS 128
#undef NUM_REGS
#define NUM_REGS (NUM_R5900_REGS + 2*(NUM_VU_REGS))
#endif /* no tm-txvu.h */
#endif
/* end-sanitize-sky */
/* To keep this default simulator simple, and fast, we use a direct /* To keep this default simulator simple, and fast, we use a direct
vector of registers. The internal simulator engine then uses vector of registers. The internal simulator engine then uses
manifests to access the correct slot. */ manifests to access the correct slot. */
@ -453,9 +517,16 @@ struct _sim_cpu {
#define GPR (&REGISTERS[0]) #define GPR (&REGISTERS[0])
#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
/* While space is allocated for the floating point registers in the
main registers array, they are stored separatly. This is because
their size may not necessarily match the size of either the
general-purpose or system specific registers */
#define NR_FGR (32) #define NR_FGR (32)
#define FGRIDX (38) #define FGRIDX (38)
#define FGR (&REGISTERS[FGRIDX]) fp_word fgr[NR_FGR];
#define FGR ((CPU)->fgr)
#define LO (REGISTERS[33]) #define LO (REGISTERS[33])
#define HI (REGISTERS[34]) #define HI (REGISTERS[34])
#define PCIDX 37 #define PCIDX 37
@ -502,6 +573,7 @@ struct _sim_cpu {
#define LLBIT ((CPU)->llbit) #define LLBIT ((CPU)->llbit)
#if 0
/* The HIACCESS and LOACCESS counts are used to ensure that /* The HIACCESS and LOACCESS counts are used to ensure that
corruptions caused by using the HI or LO register to close to a corruptions caused by using the HI or LO register to close to a
following operation are spotted. */ following operation are spotted. */
@ -510,18 +582,7 @@ struct _sim_cpu {
int loaccess; int loaccess;
#define HIACCESS ((CPU)->hiaccess) #define HIACCESS ((CPU)->hiaccess)
#define LOACCESS ((CPU)->loaccess) #define LOACCESS ((CPU)->loaccess)
/* start-sanitize-r5900 */
int hi1access;
int lo1access;
#define HI1ACCESS ((CPU)->hi1access)
#define LO1ACCESS ((CPU)->lo1access)
/* end-sanitize-r5900 */
#if 1
/* The 4300 and a few other processors have interlocks on hi/lo
register reads, and hence do not have this problem. To avoid
spurious warnings, we just disable this always. */
#define CHECKHILO(s)
#else
unsigned_word HLPC; unsigned_word HLPC;
/* If either of the preceding two instructions have accessed the HI /* If either of the preceding two instructions have accessed the HI
or LO registers, then the values they see should be or LO registers, then the values they see should be
@ -532,36 +593,17 @@ struct _sim_cpu {
if ((HIACCESS != 0) || (LOACCESS != 0)) \ if ((HIACCESS != 0) || (LOACCESS != 0)) \
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\ sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
} }
/* start-sanitize-r5900 */
#undef CHECKHILO
#define CHECKHILO(s) {\
if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
}
/* end-sanitize-r5900 */
#endif #endif
#if !defined CHECKHILO
/* The 4300 and a few other processors have interlocks on hi/lo
register reads, and hence do not have this problem. To avoid
spurious warnings, we just disable this always. */
#define CHECKHILO(s)
#endif
/* start-sanitize-r5900 */ /* start-sanitize-r5900 */
/* The R5900 has 128 bit registers, but the hi 64 bits are only sim_r5900_cpu r5900;
touched by multimedia (MMI) instructions. The normal mips
instructions just use the lower 64 bits. To avoid changing the
older parts of the simulator to handle this weirdness, the high
64 bits of each register are kept in a separate array
(registers1). The high 64 bits of any register are by convention
refered by adding a '1' to the end of the normal register's name.
So LO still refers to the low 64 bits of the LO register, LO1
refers to the high 64 bits of that same register. */
signed_word registers1[LAST_EMBED_REGNUM + 1];
#define REGISTERS1 ((CPU)->registers1)
#define GPR1 (&REGISTERS1[0])
#define LO1 (REGISTERS1[32])
#define HI1 (REGISTERS1[33])
#define REGISTER_SA (124)
unsigned_word sa; /* the shift amount register */
#define SA ((CPU)->sa)
/* end-sanitize-r5900 */ /* end-sanitize-r5900 */
/* start-sanitize-vr5400 */ /* start-sanitize-vr5400 */
@ -775,7 +817,10 @@ void prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, add
prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint) prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr)); unsigned32 ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
#define IMEM(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
unsigned16 ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
#define IMEM16(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...)); void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
FILE *tracefh; FILE *tracefh;