gas/
* config/tc-mips.c (mips_oddfpreg_ok): Move further up file. Change return type to bfd_boolean. (report_bad_range, report_bad_field): New functions. (mips_arg_info): New structure. (match_const_int, convert_reg_type, check_regno, match_int_operand) (match_mapped_int_operand, match_msb_operand, match_reg_operand) (match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand) (match_addiusp_operand, match_clo_clz_dest_operand) (match_lwm_swm_list_operand, match_mdmx_imm_reg_operand) (match_pc_operand, match_tied_reg_operand, match_operand) (check_completed_insn): New functions, commented out for now.
This commit is contained in:
Richard Sandiford
parent
e077a1c8de
commit
a1d785644e
2 changed files with 855 additions and 40 deletions
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@ -1,3 +1,17 @@
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2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (mips_oddfpreg_ok): Move further up file.
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Change return type to bfd_boolean.
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(report_bad_range, report_bad_field): New functions.
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(mips_arg_info): New structure.
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(match_const_int, convert_reg_type, check_regno, match_int_operand)
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(match_mapped_int_operand, match_msb_operand, match_reg_operand)
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(match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand)
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(match_addiusp_operand, match_clo_clz_dest_operand)
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(match_lwm_swm_list_operand, match_mdmx_imm_reg_operand)
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(match_pc_operand, match_tied_reg_operand, match_operand)
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(check_completed_insn): New functions, commented out for now.
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2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (insn_insert_operand): New function.
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@ -3702,6 +3702,847 @@ fpr_write_mask (const struct mips_cl_insn *ip)
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return mask;
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}
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/* Operand OPNUM of INSN is an odd-numbered floating-point register.
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Check whether that is allowed. */
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static bfd_boolean
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mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
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{
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const char *s = insn->name;
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if (insn->pinfo == INSN_MACRO)
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/* Let a macro pass, we'll catch it later when it is expanded. */
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return TRUE;
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if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
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{
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/* Allow odd registers for single-precision ops. */
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switch (insn->pinfo & (FP_S | FP_D))
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{
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case FP_S:
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case 0:
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return TRUE;
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case FP_D:
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return FALSE;
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default:
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break;
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}
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/* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
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s = strchr (insn->name, '.');
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if (s != NULL && opnum == 2)
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s = strchr (s + 1, '.');
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return (s != NULL && (s[1] == 'w' || s[1] == 's'));
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}
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/* Single-precision coprocessor loads and moves are OK too. */
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if ((insn->pinfo & FP_S)
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&& (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
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| INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
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return TRUE;
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return FALSE;
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}
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#if 0
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/* Report that user-supplied argument ARGNUM for INSN was VAL, but should
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have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
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this operand is normally printed in hex or decimal. */
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static void
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report_bad_range (struct mips_cl_insn *insn, int argnum,
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offsetT val, int min_val, int max_val,
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bfd_boolean print_hex)
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{
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if (print_hex && val >= 0)
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as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
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" was 0x%lx."),
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argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
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else if (print_hex)
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as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
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" was %ld."),
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argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
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else
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as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
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" was %ld."),
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argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
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}
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/* Report an invalid combination of position and size operands for a bitfield
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operation. POS and SIZE are the values that were given. */
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static void
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report_bad_field (offsetT pos, offsetT size)
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{
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as_bad (_("Invalid field specification (position %ld, size %ld)"),
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(unsigned long) pos, (unsigned long) size);
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}
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/* Information about an instruction argument that we're trying to match. */
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struct mips_arg_info
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{
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/* The instruction so far. */
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struct mips_cl_insn *insn;
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/* The 1-based operand number, in terms of insn->insn_mo->args. */
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int opnum;
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/* The 1-based argument number, for error reporting. This does not
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count elided optional registers, etc.. */
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int argnum;
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/* The last OP_REG operand seen, or ILLEGAL_REG if none. */
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unsigned int last_regno;
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/* If the first operand was an OP_REG, this is the register that it
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specified, otherwise it is ILLEGAL_REG. */
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unsigned int dest_regno;
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/* The value of the last OP_INT operand. Only used for OP_MSB,
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where it gives the lsb position. */
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unsigned int last_op_int;
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/* If true, match routines should silently reject invalid arguments.
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If false, match routines can accept invalid arguments as long as
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they report an appropriate error. They still have the option of
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silently rejecting arguments, in which case a generic "Invalid operands"
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style of error will be used instead. */
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bfd_boolean soft_match;
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/* If true, the OP_INT match routine should treat plain symbolic operands
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as if a relocation operator like %lo(...) had been used. This is only
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ever true if the operand can be relocated. */
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bfd_boolean allow_nonconst;
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/* When true, the OP_INT match routine should allow unsigned N-bit
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arguments to be used where a signed N-bit operand is expected. */
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bfd_boolean lax_max;
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/* When true, the OP_REG match routine should assume that another operand
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appears after this one. It should fail the match if the register it
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sees is at the end of the argument list. */
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bfd_boolean optional_reg;
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/* True if a reference to the current AT register was seen. */
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bfd_boolean seen_at;
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};
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/* Match a constant integer at S for ARG. Return null if the match failed.
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Otherwise return the end of the matched string and store the constant value
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in *VALUE. In the latter case, use FALLBACK as the value if the match
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succeeded with an error. */
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static char *
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match_const_int (struct mips_arg_info *arg, char *s, offsetT *value,
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offsetT fallback)
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{
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expressionS ex;
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bfd_reloc_code_real_type r[3];
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int num_relocs;
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num_relocs = my_getSmallExpression (&ex, r, s);
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if (*s == '(' && ex.X_op == O_register)
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{
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/* Assume that the constant has been elided and that S is a base
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register. The rest of the match will fail if the assumption
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turns out to be wrong. */
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*value = 0;
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return s;
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}
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if (num_relocs == 0 && ex.X_op == O_constant)
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*value = ex.X_add_number;
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else
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{
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/* If we got a register rather than an expression, the default
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"Invalid operands" style of error seems more appropriate. */
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if (arg->soft_match || ex.X_op == O_register)
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return 0;
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as_bad (_("Operand %d of `%s' must be constant"),
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arg->argnum, arg->insn->insn_mo->name);
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*value = fallback;
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}
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return expr_end;
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}
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/* Return the RTYPE_* flags for a register operand of type TYPE that
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appears in instruction OPCODE. */
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static unsigned int
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convert_reg_type (const struct mips_opcode *opcode,
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enum mips_reg_operand_type type)
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{
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switch (type)
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{
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case OP_REG_GP:
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return RTYPE_NUM | RTYPE_GP;
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case OP_REG_FP:
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/* Allow vector register names for MDMX if the instruction is a 64-bit
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FPR load, store or move (including moves to and from GPRs). */
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if ((mips_opts.ase & ASE_MDMX)
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&& (opcode->pinfo & FP_D)
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&& (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
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| INSN_COPROC_MEMORY_DELAY
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| INSN_LOAD_COPROC_DELAY
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| INSN_LOAD_MEMORY_DELAY
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| INSN_STORE_MEMORY)))
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return RTYPE_FPU | RTYPE_VEC;
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return RTYPE_FPU;
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case OP_REG_CCC:
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if (opcode->pinfo & (FP_D | FP_S))
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return RTYPE_CCC | RTYPE_FCC;
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return RTYPE_CCC;
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case OP_REG_VEC:
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if (opcode->membership & INSN_5400)
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return RTYPE_FPU;
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return RTYPE_FPU | RTYPE_VEC;
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case OP_REG_ACC:
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return RTYPE_ACC;
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case OP_REG_COPRO:
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if (opcode->name[strlen (opcode->name) - 1] == '0')
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return RTYPE_NUM | RTYPE_CP0;
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return RTYPE_NUM;
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case OP_REG_HW:
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return RTYPE_NUM;
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}
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abort ();
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}
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/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
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static void
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check_regno (struct mips_arg_info *arg,
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enum mips_reg_operand_type type, unsigned int regno)
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{
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if (AT && type == OP_REG_GP && regno == AT)
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arg->seen_at = TRUE;
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if (type == OP_REG_FP
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&& (regno & 1) != 0
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&& HAVE_32BIT_FPRS
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&& !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
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as_warn (_("Float register should be even, was %d"), regno);
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if (type == OP_REG_CCC)
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{
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const char *name;
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size_t length;
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name = arg->insn->insn_mo->name;
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length = strlen (name);
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if ((regno & 1) != 0
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&& ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
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|| (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
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as_warn (_("Condition code register should be even for %s, was %d"),
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name, regno);
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if ((regno & 3) != 0
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&& (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
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as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
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name, regno);
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}
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}
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/* OP_INT matcher. */
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static char *
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match_int_operand (struct mips_arg_info *arg,
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const struct mips_operand *operand_base, char *s)
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{
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const struct mips_int_operand *operand;
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unsigned int uval, mask;
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int min_val, max_val, factor;
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offsetT sval;
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bfd_boolean print_hex;
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operand = (const struct mips_int_operand *) operand_base;
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factor = 1 << operand->shift;
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mask = (1 << operand_base->size) - 1;
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max_val = (operand->max_val + operand->bias) << operand->shift;
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min_val = max_val - (mask << operand->shift);
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if (arg->lax_max)
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max_val = mask << operand->shift;
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if (operand_base->lsb == 0
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&& operand_base->size == 16
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&& operand->shift == 0
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&& operand->bias == 0
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&& (operand->max_val == 32767 || operand->max_val == 65535))
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{
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/* The operand can be relocated. */
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offset_reloc[0] = BFD_RELOC_LO16;
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offset_reloc[1] = BFD_RELOC_UNUSED;
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offset_reloc[2] = BFD_RELOC_UNUSED;
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if (my_getSmallExpression (&offset_expr, offset_reloc, s) > 0)
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/* Relocation operators were used. Accept the arguent and
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leave the relocation value in offset_expr and offset_relocs
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for the caller to process. */
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return expr_end;
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if (*s == '(' && offset_expr.X_op == O_register)
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/* Assume that the constant has been elided and that S is a base
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register. The rest of the match will fail if the assumption
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turns out to be wrong. */
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sval = 0;
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else
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{
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s = expr_end;
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if (offset_expr.X_op != O_constant)
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/* If non-constant operands are allowed then leave them for
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the caller to process, otherwise fail the match. */
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return arg->allow_nonconst ? s : 0;
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sval = offset_expr.X_add_number;
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}
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/* Clear the global state; we're going to install the operand
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ourselves. */
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offset_reloc[0] = BFD_RELOC_UNUSED;
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offset_expr.X_op = O_absent;
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}
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else
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{
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s = match_const_int (arg, s, &sval, min_val);
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if (!s)
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return 0;
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}
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arg->last_op_int = sval;
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/* Check the range. If there's a problem, record the lowest acceptable
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value in arg->last_op_int in order to prevent an unhelpful error
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from OP_MSB too.
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Bit counts have traditionally been printed in hex by the disassembler
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but printed as decimal in error messages. Only resort to hex if
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the operand is bigger than 6 bits. */
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print_hex = operand->print_hex && operand_base->size > 6;
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if (sval < min_val || sval > max_val)
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{
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if (arg->soft_match)
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return 0;
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report_bad_range (arg->insn, arg->argnum, sval, min_val, max_val,
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print_hex);
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arg->last_op_int = min_val;
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}
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else if (sval % factor)
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{
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if (arg->soft_match)
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return 0;
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as_bad (print_hex && sval >= 0
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? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
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: _("Operand %d of `%s' must be a factor of %d, was %ld."),
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arg->argnum, arg->insn->insn_mo->name, factor,
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(unsigned long) sval);
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arg->last_op_int = min_val;
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}
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uval = (unsigned int) sval >> operand->shift;
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uval -= operand->bias;
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/* Handle -mfix-cn63xxp1. */
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if (arg->opnum == 1
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&& mips_fix_cn63xxp1
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&& !mips_opts.micromips
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&& strcmp ("pref", arg->insn->insn_mo->name) == 0)
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switch (uval)
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{
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case 5:
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case 25:
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case 26:
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case 27:
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case 28:
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case 29:
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case 30:
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case 31:
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/* These are ok. */
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break;
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default:
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/* The rest must be changed to 28. */
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uval = 28;
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break;
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}
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insn_insert_operand (arg->insn, operand_base, uval);
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return s;
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}
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/* OP_MAPPED_INT matcher. */
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static char *
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match_mapped_int_operand (struct mips_arg_info *arg,
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const struct mips_operand *operand_base, char *s)
|
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{
|
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const struct mips_mapped_int_operand *operand;
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unsigned int uval, num_vals;
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offsetT sval;
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operand = (const struct mips_mapped_int_operand *) operand_base;
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s = match_const_int (arg, s, &sval, operand->int_map[0]);
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if (!s)
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return 0;
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num_vals = 1 << operand_base->size;
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for (uval = 0; uval < num_vals; uval++)
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if (operand->int_map[uval] == sval)
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break;
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if (uval == num_vals)
|
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return 0;
|
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|
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insn_insert_operand (arg->insn, operand_base, uval);
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return s;
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}
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/* OP_MSB matcher. */
|
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static char *
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match_msb_operand (struct mips_arg_info *arg,
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const struct mips_operand *operand_base, char *s)
|
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{
|
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const struct mips_msb_operand *operand;
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int min_val, max_val, max_high;
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offsetT size, sval, high;
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operand = (const struct mips_msb_operand *) operand_base;
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min_val = operand->bias;
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max_val = min_val + (1 << operand_base->size) - 1;
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max_high = operand->opsize;
|
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s = match_const_int (arg, s, &size, 1);
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if (!s)
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return 0;
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high = size + arg->last_op_int;
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sval = operand->add_lsb ? high : size;
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|
||||
if (size < 0 || high > max_high || sval < min_val || sval > max_val)
|
||||
{
|
||||
if (arg->soft_match)
|
||||
return 0;
|
||||
report_bad_field (arg->last_op_int, size);
|
||||
sval = min_val;
|
||||
}
|
||||
insn_insert_operand (arg->insn, operand_base, sval - min_val);
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_REG matcher. */
|
||||
|
||||
static char *
|
||||
match_reg_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand_base, char *s)
|
||||
{
|
||||
const struct mips_reg_operand *operand;
|
||||
unsigned int regno, uval, num_vals, types;
|
||||
|
||||
operand = (const struct mips_reg_operand *) operand_base;
|
||||
types = convert_reg_type (arg->insn->insn_mo, operand->reg_type);
|
||||
if (!reg_lookup (&s, types, ®no))
|
||||
return 0;
|
||||
|
||||
SKIP_SPACE_TABS (s);
|
||||
if (arg->optional_reg && *s == 0)
|
||||
return 0;
|
||||
|
||||
if (operand->reg_map)
|
||||
{
|
||||
num_vals = 1 << operand->root.size;
|
||||
for (uval = 0; uval < num_vals; uval++)
|
||||
if (operand->reg_map[uval] == regno)
|
||||
break;
|
||||
if (num_vals == uval)
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
uval = regno;
|
||||
|
||||
check_regno (arg, operand->reg_type, regno);
|
||||
arg->last_regno = regno;
|
||||
if (arg->opnum == 1)
|
||||
arg->dest_regno = regno;
|
||||
insn_insert_operand (arg->insn, operand_base, uval);
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_REG_PAIR matcher. */
|
||||
|
||||
static char *
|
||||
match_reg_pair_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand_base, char *s)
|
||||
{
|
||||
const struct mips_reg_pair_operand *operand;
|
||||
unsigned int regno1, regno2, uval, num_vals, types;
|
||||
|
||||
operand = (const struct mips_reg_pair_operand *) operand_base;
|
||||
types = convert_reg_type (arg->insn->insn_mo, operand->reg_type);
|
||||
|
||||
if (!reg_lookup (&s, types, ®no1))
|
||||
return 0;
|
||||
|
||||
SKIP_SPACE_TABS (s);
|
||||
if (*s++ != ',')
|
||||
return 0;
|
||||
arg->argnum += 1;
|
||||
|
||||
if (!reg_lookup (&s, types, ®no2))
|
||||
return 0;
|
||||
|
||||
num_vals = 1 << operand_base->size;
|
||||
for (uval = 0; uval < num_vals; uval++)
|
||||
if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
|
||||
break;
|
||||
if (uval == num_vals)
|
||||
return 0;
|
||||
|
||||
check_regno (arg, operand->reg_type, regno1);
|
||||
check_regno (arg, operand->reg_type, regno2);
|
||||
insn_insert_operand (arg->insn, operand_base, uval);
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_PCREL matcher. The caller chooses the relocation type. */
|
||||
|
||||
static char *
|
||||
match_pcrel_operand (char *s)
|
||||
{
|
||||
my_getExpression (&offset_expr, s);
|
||||
return expr_end;
|
||||
}
|
||||
|
||||
/* OP_PERF_REG matcher. */
|
||||
|
||||
static char *
|
||||
match_perf_reg_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand, char *s)
|
||||
{
|
||||
offsetT sval;
|
||||
|
||||
s = match_const_int (arg, s, &sval, 0);
|
||||
if (!s)
|
||||
return 0;
|
||||
|
||||
if (sval != 0
|
||||
&& (sval != 1
|
||||
|| (mips_opts.arch == CPU_R5900
|
||||
&& (strcmp (arg->insn->insn_mo->name, "mfps") == 0
|
||||
|| strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
|
||||
{
|
||||
if (arg->soft_match)
|
||||
return 0;
|
||||
as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval);
|
||||
}
|
||||
|
||||
insn_insert_operand (arg->insn, operand, sval);
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_ADDIUSP matcher. */
|
||||
|
||||
static char *
|
||||
match_addiusp_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand, char *s)
|
||||
{
|
||||
offsetT sval;
|
||||
unsigned int uval;
|
||||
|
||||
s = match_const_int (arg, s, &sval, -256);
|
||||
if (!s)
|
||||
return 0;
|
||||
|
||||
if (sval % 4)
|
||||
return 0;
|
||||
|
||||
sval /= 4;
|
||||
if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
|
||||
return 0;
|
||||
|
||||
uval = (unsigned int) sval;
|
||||
uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
|
||||
insn_insert_operand (arg->insn, operand, uval);
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_CLO_CLZ_DEST matcher. */
|
||||
|
||||
static char *
|
||||
match_clo_clz_dest_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand, char *s)
|
||||
{
|
||||
unsigned int regno;
|
||||
|
||||
if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
|
||||
return 0;
|
||||
|
||||
check_regno (arg, OP_REG_GP, regno);
|
||||
insn_insert_operand (arg->insn, operand, regno | (regno << 5));
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_LWM_SWM_LIST matcher. */
|
||||
|
||||
static char *
|
||||
match_lwm_swm_list_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand, char *s)
|
||||
{
|
||||
unsigned int reglist, sregs, ra;
|
||||
|
||||
if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
|
||||
return 0;
|
||||
|
||||
if (operand->size == 2)
|
||||
{
|
||||
/* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
|
||||
|
||||
s0, ra
|
||||
s0, s1, ra, s2, s3
|
||||
s0-s2, ra
|
||||
|
||||
and any permutations of these. */
|
||||
if ((reglist & 0xfff1ffff) != 0x80010000)
|
||||
return 0;
|
||||
|
||||
sregs = (reglist >> 17) & 7;
|
||||
ra = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The list must include at least one of ra and s0-sN,
|
||||
for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
|
||||
which are $23 and $30 respectively.) E.g.:
|
||||
|
||||
ra
|
||||
s0
|
||||
ra, s0, s1, s2
|
||||
s0-s8
|
||||
s0-s5, ra
|
||||
|
||||
and any permutations of these. */
|
||||
if ((reglist & 0x3f00ffff) != 0)
|
||||
return 0;
|
||||
|
||||
ra = (reglist >> 27) & 0x10;
|
||||
sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
|
||||
}
|
||||
sregs += 1;
|
||||
if ((sregs & -sregs) != sregs)
|
||||
return 0;
|
||||
|
||||
insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_MDMX_IMM_REG matcher. */
|
||||
|
||||
static char *
|
||||
match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand, char *s)
|
||||
{
|
||||
unsigned int regno, uval, types;
|
||||
bfd_boolean is_qh;
|
||||
const struct mips_opcode *opcode;
|
||||
|
||||
/* The mips_opcode records whether this is an octobyte or quadhalf
|
||||
instruction. Start out with that bit in place. */
|
||||
opcode = arg->insn->insn_mo;
|
||||
uval = mips_extract_operand (operand, opcode->match);
|
||||
is_qh = (uval != 0);
|
||||
|
||||
types = convert_reg_type (arg->insn->insn_mo, OP_REG_VEC);
|
||||
if (reg_lookup (&s, types, ®no))
|
||||
{
|
||||
if ((opcode->membership & INSN_5400)
|
||||
&& strcmp (opcode->name, "rzu.ob") == 0)
|
||||
{
|
||||
if (arg->soft_match)
|
||||
return 0;
|
||||
as_bad (_("Operand %d of `%s' must be an immediate"),
|
||||
arg->argnum, opcode->name);
|
||||
}
|
||||
|
||||
/* Check whether this is a vector register or a broadcast of
|
||||
a single element. */
|
||||
SKIP_SPACE_TABS (s);
|
||||
if (*s == '[')
|
||||
{
|
||||
/* Read the element number. */
|
||||
expressionS value;
|
||||
|
||||
++s;
|
||||
SKIP_SPACE_TABS (s);
|
||||
my_getExpression (&value, s);
|
||||
s = expr_end;
|
||||
if (value.X_op != O_constant
|
||||
|| value.X_add_number < 0
|
||||
|| value.X_add_number > (is_qh ? 3 : 7))
|
||||
{
|
||||
if (arg->soft_match)
|
||||
return 0;
|
||||
as_bad (_("Invalid element selector"));
|
||||
value.X_add_number = 0;
|
||||
}
|
||||
uval |= (unsigned int) value.X_add_number << (is_qh ? 2 : 1) << 5;
|
||||
SKIP_SPACE_TABS (s);
|
||||
if (*s == ']')
|
||||
++s;
|
||||
else
|
||||
{
|
||||
if (arg->soft_match)
|
||||
return 0;
|
||||
as_bad (_("Expecting ']' found '%s'"), s);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* A full vector. */
|
||||
if ((opcode->membership & INSN_5400)
|
||||
&& (strcmp (opcode->name, "sll.ob") == 0
|
||||
|| strcmp (opcode->name, "srl.ob") == 0))
|
||||
{
|
||||
if (arg->soft_match)
|
||||
return 0;
|
||||
as_bad (_("Operand %d of `%s' must be scalar"),
|
||||
arg->argnum, opcode->name);
|
||||
}
|
||||
|
||||
if (is_qh)
|
||||
uval |= MDMX_FMTSEL_VEC_QH << 5;
|
||||
else
|
||||
uval |= MDMX_FMTSEL_VEC_OB << 5;
|
||||
}
|
||||
check_regno (arg, OP_REG_FP, regno);
|
||||
uval |= regno;
|
||||
}
|
||||
else
|
||||
{
|
||||
offsetT sval;
|
||||
|
||||
s = match_const_int (arg, s, &sval, 0);
|
||||
if (!s)
|
||||
return 0;
|
||||
if (sval < 0 || sval > 31)
|
||||
{
|
||||
if (arg->soft_match)
|
||||
return 0;
|
||||
report_bad_range (arg->insn, arg->argnum, sval, 0, 31, FALSE);
|
||||
}
|
||||
uval |= (sval & 31);
|
||||
if (is_qh)
|
||||
uval |= MDMX_FMTSEL_IMM_QH << 5;
|
||||
else
|
||||
uval |= MDMX_FMTSEL_IMM_OB << 5;
|
||||
}
|
||||
insn_insert_operand (arg->insn, operand, uval);
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_PC matcher. */
|
||||
|
||||
static char *
|
||||
match_pc_operand (char *s)
|
||||
{
|
||||
if (strncmp (s, "$pc", 3) != 0)
|
||||
return 0;
|
||||
s += 3;
|
||||
SKIP_SPACE_TABS (s);
|
||||
return s;
|
||||
}
|
||||
|
||||
/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
|
||||
register that we need to match. */
|
||||
|
||||
static char *
|
||||
match_tied_reg_operand (struct mips_arg_info *arg, char *s,
|
||||
unsigned int other_regno)
|
||||
{
|
||||
unsigned int regno;
|
||||
|
||||
if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)
|
||||
|| regno != other_regno)
|
||||
return 0;
|
||||
SKIP_SPACE_TABS (s);
|
||||
if (arg->optional_reg && *s == 0)
|
||||
return 0;
|
||||
return s;
|
||||
}
|
||||
|
||||
/* S is the text seen for ARG. Match it against OPERAND. Return the end
|
||||
of the argument text if the match is successful, otherwise return null. */
|
||||
|
||||
static char *
|
||||
match_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand, char *s)
|
||||
{
|
||||
switch (operand->type)
|
||||
{
|
||||
case OP_INT:
|
||||
return match_int_operand (arg, operand, s);
|
||||
|
||||
case OP_MAPPED_INT:
|
||||
return match_mapped_int_operand (arg, operand, s);
|
||||
|
||||
case OP_MSB:
|
||||
return match_msb_operand (arg, operand, s);
|
||||
|
||||
case OP_REG:
|
||||
return match_reg_operand (arg, operand, s);
|
||||
|
||||
case OP_REG_PAIR:
|
||||
return match_reg_pair_operand (arg, operand, s);
|
||||
|
||||
case OP_PCREL:
|
||||
return match_pcrel_operand (s);
|
||||
|
||||
case OP_PERF_REG:
|
||||
return match_perf_reg_operand (arg, operand, s);
|
||||
|
||||
case OP_ADDIUSP_INT:
|
||||
return match_addiusp_operand (arg, operand, s);
|
||||
|
||||
case OP_CLO_CLZ_DEST:
|
||||
return match_clo_clz_dest_operand (arg, operand, s);
|
||||
|
||||
case OP_LWM_SWM_LIST:
|
||||
return match_lwm_swm_list_operand (arg, operand, s);
|
||||
|
||||
case OP_ENTRY_EXIT_LIST:
|
||||
case OP_SAVE_RESTORE_LIST:
|
||||
abort ();
|
||||
|
||||
case OP_MDMX_IMM_REG:
|
||||
return match_mdmx_imm_reg_operand (arg, operand, s);
|
||||
|
||||
case OP_REPEAT_DEST_REG:
|
||||
return match_tied_reg_operand (arg, s, arg->dest_regno);
|
||||
|
||||
case OP_REPEAT_PREV_REG:
|
||||
return match_tied_reg_operand (arg, s, arg->last_regno);
|
||||
|
||||
case OP_PC:
|
||||
return match_pc_operand (s);
|
||||
}
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* ARG is the state after successfully matching an instruction.
|
||||
Issue any queued-up warnings. */
|
||||
|
||||
static void
|
||||
check_completed_insn (struct mips_arg_info *arg)
|
||||
{
|
||||
if (arg->seen_at)
|
||||
{
|
||||
if (AT == ATREG)
|
||||
as_warn (_("Used $at without \".set noat\""));
|
||||
else
|
||||
as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Classify an instruction according to the FIX_VR4120_* enumeration.
|
||||
Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
|
||||
by VR4120 errata. */
|
||||
|
|
@ -10676,46 +11517,6 @@ static const struct mips_immed mips_immed[] = {
|
|||
{ 0,0,0,0 }
|
||||
};
|
||||
|
||||
/* Check whether an odd floating-point register is allowed. */
|
||||
static int
|
||||
mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
|
||||
{
|
||||
const char *s = insn->name;
|
||||
|
||||
if (insn->pinfo == INSN_MACRO)
|
||||
/* Let a macro pass, we'll catch it later when it is expanded. */
|
||||
return 1;
|
||||
|
||||
if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
|
||||
{
|
||||
/* Allow odd registers for single-precision ops. */
|
||||
switch (insn->pinfo & (FP_S | FP_D))
|
||||
{
|
||||
case FP_S:
|
||||
case 0:
|
||||
return 1; /* both single precision - ok */
|
||||
case FP_D:
|
||||
return 0; /* both double precision - fail */
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
|
||||
s = strchr (insn->name, '.');
|
||||
if (argnum == 2)
|
||||
s = s != NULL ? strchr (s + 1, '.') : NULL;
|
||||
return (s != NULL && (s[1] == 'w' || s[1] == 's'));
|
||||
}
|
||||
|
||||
/* Single-precision coprocessor loads and moves are OK too. */
|
||||
if ((insn->pinfo & FP_S)
|
||||
&& (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
|
||||
| INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
|
||||
taking bits from BIT up. */
|
||||
static int
|
||||
|
|
|
|||
Loading…
Reference in a new issue