Allow assembler to make parallel instructions where there the seconds
(latter) outputs intersect with the first (earlier) inputs.
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2 changed files with 20 additions and 10 deletions
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@ -1,3 +1,8 @@
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Fri Oct 10 16:09:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* config/tc-d10v.c (parallel_ok): Allow parallel instruction issue
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when second instruction is writing to first instructions inputs.
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Mon Oct 13 15:27:17 1997 Richard Henderson <rth@cygnus.com>
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* ecoff.c (PAGE_SIZE): Double to 8k as a hack to allow some C++
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@ -808,15 +808,20 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
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if (exec_type == 0 && (op1->exec_type & BRANCH) != 0)
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return 0;
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/* The idea here is to create two sets of bitmasks (mod and used) */
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/* which indicate which registers are modified or used by each instruction. */
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/* The operation can only be done in parallel if instruction 1 and instruction 2 */
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/* modify different registers, and neither instruction modifies any registers */
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/* the other is using. Accesses to control registers, PSW, and memory are treated */
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/* as accesses to a single register. So if both instructions write memory or one */
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/* instruction writes memory and the other reads, then they cannot be done in parallel. */
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/* Likewise, if one instruction mucks with the psw and the other reads the PSW */
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/* (which includes C, F0, and F1), then they cannot operate safely in parallel. */
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/* The idea here is to create two sets of bitmasks (mod and used)
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which indicate which registers are modified or used by each
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instruction. The operation can only be done in parallel if
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instruction 1 and instruction 2 modify different registers, and
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the first instruction does not modify registers that the second
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is using (The second instruction can modify registers that the
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first is using as they are only written back after the first
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instruction has completed). Accesses to control registers, PSW,
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and memory are treated as accesses to a single register. So if
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both instructions write memory or if the first instruction writes
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memory and the second reads, then they cannot be done in
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parallel. Likewise, if the first instruction mucks with the psw
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and the second reads the PSW (which includes C, F0, and F1), then
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they cannot operate safely in parallel. */
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/* the bitmasks (mod and used) look like this (bit 31 = MSB) */
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/* r0-r15 0-15 */
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@ -898,7 +903,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
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else if (op->exec_type & WCAR)
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mod[j] |= 1 << 19;
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}
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if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0 && (mod[1] & used[0]) == 0)
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if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
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return 1;
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return 0;
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}
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