Allow reads/writes to C0_CONFIG register.
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3 changed files with 40 additions and 13 deletions
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@ -1,3 +1,9 @@
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Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-main.h (Config): New register.
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* interp.c (decode_coproc): Allow access to Config register.
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Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
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* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
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@ -2065,12 +2065,16 @@ store_fpr(sd,cia,fpr,fmt,value)
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if (SizeFGR() == 64) {
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switch (fmt) {
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case fmt_uninterpreted_32:
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fmt = fmt_uninterpreted;
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case fmt_single :
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case fmt_word :
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FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
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FPR_STATE[fpr] = fmt;
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break;
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case fmt_uninterpreted_64:
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fmt = fmt_uninterpreted;
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case fmt_uninterpreted:
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case fmt_double :
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case fmt_long :
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@ -2085,12 +2089,16 @@ store_fpr(sd,cia,fpr,fmt,value)
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}
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} else {
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switch (fmt) {
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case fmt_uninterpreted_32:
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fmt = fmt_uninterpreted;
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case fmt_single :
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case fmt_word :
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FGR[fpr] = (value & 0xFFFFFFFF);
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FPR_STATE[fpr] = fmt;
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break;
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case fmt_uninterpreted_64:
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fmt = fmt_uninterpreted;
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case fmt_uninterpreted:
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case fmt_double :
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case fmt_long :
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@ -3019,6 +3027,12 @@ decode_coproc(sd,cia,instruction)
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break;
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#else
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/* 16 = Config R4000 VR4100 VR4300 */
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case 16:
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if (code == 0x00)
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GPR[rt] = C0_CONFIG;
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else
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C0_CONFIG = GPR[rt];
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break;
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#endif
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#ifdef SUBTARGET_R3900
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/* 17 = Debug */
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@ -3239,18 +3253,8 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
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[NOTE: pipeline_count has been replaced the event queue] */
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#if defined(HASFPU)
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/* Set previous flag, depending on current: */
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if (STATE & simPCOC0)
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STATE |= simPCOC1;
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else
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STATE &= ~simPCOC1;
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/* and update the current value: */
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if (GETFCC(0))
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STATE |= simPCOC0;
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else
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STATE &= ~simPCOC0;
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#endif /* HASFPU */
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/* shuffle the floating point status pipeline state */
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ENGINE_ISSUE_PREFIX_HOOK();
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/* NOTE: For multi-context simulation environments the "instruction"
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variable should be local to this routine. */
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@ -97,6 +97,8 @@ typedef enum {
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range, and are used in the register status vector. */
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fmt_unknown = 0x10000000,
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fmt_uninterpreted = 0x20000000,
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fmt_uninterpreted_32 = 0x40000000,
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fmt_uninterpreted_64 = 0x80000000,
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} FP_formats;
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unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
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@ -339,7 +341,19 @@ struct _sim_cpu {
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#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
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#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
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#define ENGINE_ISSUE_PREFIX_HOOK() \
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{ \
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/* Set previous flag, depending on current: */ \
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if (STATE & simPCOC0) \
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STATE |= simPCOC1; \
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else \
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STATE &= ~simPCOC1; \
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/* and update the current value: */ \
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if (GETFCC(0)) \
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STATE |= simPCOC0; \
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else \
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STATE &= ~simPCOC0; \
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}
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/* This is nasty, since we have to rely on matching the register
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@ -385,6 +399,9 @@ struct _sim_cpu {
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#define EPC (REGISTERS[88])
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#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
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unsigned_word c0_config_reg;
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#define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg)
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/* The following are pseudonyms for standard registers */
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#define ZERO (REGISTERS[0])
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#define V0 (REGISTERS[2])
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