Support Intel SHA

gas/

2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* config/tc-i386.c (cpu_arch): Add .sha.
	* doc/c-i386.texi: Document sha/.sha.

gas/testsuite/

2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* gas/i386/sha.d: New.
	* gas/i386/sha.s: New.
	* gas/i386/x86-64-sha.d: New.
	* gas/i386/x86-64-sha.s: New.
	* gas/i386/i386.exp: Run new SHA tests.

opcodes/

2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
	PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
	PREFIX_0F3ACC.
	(prefix_table): Updated.
	(three_byte_table): Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
	(cpu_flags): Add CpuSHA.
	(i386_cpu_flags): Add cpusha.
	* i386-init.h: Regenerate.
	* i386-opc.h (CpuSHA): New.
	(CpuUnused): Restored.
	(i386_cpu_flags): Add cpusha.
	* i386-opc.tbl: Add SHA instructions.
	* i386-tbl.h: Regenerate.

gas/ChangeLog

@@ -1,3 +1,8 @@
+2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Add .sha.
+	* doc/c-i386.texi: Document sha/.sha.
+
 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 	    Kirill Yukhin  <kirill.yukhin@intel.com>
 	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

gas/config/tc-i386.c

@@ -790,6 +790,8 @@ static const arch_entry cpu_arch[] =
     CPU_SMAP_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
     CPU_MPX_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
+    CPU_SHA_FLAGS, 0, 0 },
 };
 
 #ifdef I386COFF

gas/doc/c-i386.texi

@@ -151,6 +151,7 @@ accept various extension mnemonics.  For example,
 @code{prfchw},
 @code{smap},
 @code{mpx},
+@code{sha},
 @code{noavx},
 @code{vmx},
 @code{vmfunc},
@@ -1036,6 +1037,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
 @item @samp{.smap} @tab @samp{.mpx}
+@item @samp{.smap} @tab @samp{.sha}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}

gas/testsuite/ChangeLog

@@ -1,3 +1,11 @@
+2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* gas/i386/sha.d: New.
+	* gas/i386/sha.s: New.
+	* gas/i386/x86-64-sha.d: New.
+	* gas/i386/x86-64-sha.s: New.
+	* gas/i386/i386.exp: Run new SHA tests.
+
 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 	    Kirill Yukhin  <kirill.yukhin@intel.com>
 	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

gas/testsuite/gas/i386/i386.exp

@@ -248,6 +248,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "mpx"
     run_list_test "mpx-inval-1" "-al"
     run_dump_test "mpx-add-bnd-prefix"
+    run_dump_test "sha"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -514,6 +515,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_list_test "x86-64-mpx-inval-2" "-al"
     run_dump_test "x86-64-mpx-addr32"
     run_dump_test "x86-64-mpx-add-bnd-prefix"
+    run_dump_test "x86-64-sha"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]

gas/testsuite/gas/i386/sha.d

@@ -0,0 +1,72 @@
+#objdump: -dw
+#name: i386 SHA
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	0f 3a cc ca 09       	sha1rnds4 \$0x9,%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 3a cc 10 07       	sha1rnds4 \$0x7,\(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 3a cc 58 12 05    	sha1rnds4 \$0x5,0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 3a cc 24 58 01    	sha1rnds4 \$0x1,\(%eax,%ebx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 c8 ca          	sha1nexte %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c8 08          	sha1nexte \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c8 48 12       	sha1nexte 0x12\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c8 0c 58       	sha1nexte \(%eax,%ebx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c9 ca          	sha1msg1 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c9 08          	sha1msg1 \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c9 48 12       	sha1msg1 0x12\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c9 0c 58       	sha1msg1 \(%eax,%ebx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 ca ca          	sha1msg2 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 ca 08          	sha1msg2 \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 ca 48 12       	sha1msg2 0x12\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 ca 0c 58       	sha1msg2 \(%eax,%ebx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb ca          	sha256rnds2 (%xmm0,)?%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 08          	sha256rnds2 (%xmm0,)?\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 48 12       	sha256rnds2 (%xmm0,)?0x12\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 0c 58       	sha256rnds2 (%xmm0,)?\(%eax,%ebx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb ca          	sha256rnds2 (%xmm0,)?%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 08          	sha256rnds2 (%xmm0,)?\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 48 12       	sha256rnds2 (%xmm0,)?0x12\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 0c 58       	sha256rnds2 (%xmm0,)?\(%eax,%ebx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc ca          	sha256msg1 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc 08          	sha256msg1 \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc 48 12       	sha256msg1 0x12\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc 0c 58       	sha256msg1 \(%eax,%ebx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd ca          	sha256msg2 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd 08          	sha256msg2 \(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd 48 12       	sha256msg2 0x12\(%eax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd 0c 58       	sha256msg2 \(%eax,%ebx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 3a cc ca 09       	sha1rnds4 \$0x9,%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 3a cc 10 07       	sha1rnds4 \$0x7,\(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 3a cc 58 12 05    	sha1rnds4 \$0x5,0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 3a cc 24 58 01    	sha1rnds4 \$0x1,\(%eax,%ebx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 c8 ca          	sha1nexte %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c8 10          	sha1nexte \(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 c8 58 12       	sha1nexte 0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 c8 24 58       	sha1nexte \(%eax,%ebx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 c9 ca          	sha1msg1 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c9 10          	sha1msg1 \(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 c9 58 12       	sha1msg1 0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 c9 24 58       	sha1msg1 \(%eax,%ebx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 ca ca          	sha1msg2 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 ca 10          	sha1msg2 \(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 ca 58 12       	sha1msg2 0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 ca 24 58       	sha1msg2 \(%eax,%ebx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 cb ca          	sha256rnds2 (%xmm0,)?%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 10          	sha256rnds2 (%xmm0,)?\(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 cb 58 12       	sha256rnds2 (%xmm0,)?0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 cb 24 58       	sha256rnds2 (%xmm0,)?\(%eax,%ebx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 cb ca          	sha256rnds2 (%xmm0,)?%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 10          	sha256rnds2 (%xmm0,)?\(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 cb 58 12       	sha256rnds2 (%xmm0,)?0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 cb 24 58       	sha256rnds2 (%xmm0,)?\(%eax,%ebx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 cc ca          	sha256msg1 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc 10          	sha256msg1 \(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 cc 58 12       	sha256msg1 0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 cc 24 58       	sha256msg1 \(%eax,%ebx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 cd ca          	sha256msg2 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd 10          	sha256msg2 \(%eax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 cd 58 12       	sha256msg2 0x12\(%eax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 cd 24 58       	sha256msg2 \(%eax,%ebx,2\),%xmm4

gas/testsuite/gas/i386/sha.s

@@ -0,0 +1,72 @@
+# Check SHA instructions
+
+	.allow_index_reg
+	.text
+_start:
+	sha1rnds4 $9, %xmm2, %xmm1
+	sha1rnds4 $7, (%eax), %xmm2
+	sha1rnds4 $5, 0x12(%eax), %xmm3
+	sha1rnds4 $1, (%eax,%ebx,2), %xmm4
+	sha1nexte %xmm2, %xmm1
+	sha1nexte (%eax), %xmm1
+	sha1nexte 0x12(%eax), %xmm1
+	sha1nexte (%eax,%ebx,2), %xmm1
+	sha1msg1 %xmm2, %xmm1
+	sha1msg1 (%eax), %xmm1
+	sha1msg1 0x12(%eax), %xmm1
+	sha1msg1 (%eax,%ebx,2), %xmm1
+	sha1msg2 %xmm2, %xmm1
+	sha1msg2 (%eax), %xmm1
+	sha1msg2 0x12(%eax), %xmm1
+	sha1msg2 (%eax,%ebx,2), %xmm1
+	sha256rnds2 %xmm2, %xmm1
+	sha256rnds2 (%eax), %xmm1
+	sha256rnds2 0x12(%eax), %xmm1
+	sha256rnds2 (%eax,%ebx,2), %xmm1
+	sha256rnds2 %xmm0, %xmm2, %xmm1
+	sha256rnds2 %xmm0, (%eax), %xmm1
+	sha256rnds2 %xmm0, 0x12(%eax), %xmm1
+	sha256rnds2 %xmm0, (%eax,%ebx,2), %xmm1
+	sha256msg1 %xmm2, %xmm1
+	sha256msg1 (%eax), %xmm1
+	sha256msg1 0x12(%eax), %xmm1
+	sha256msg1 (%eax,%ebx,2), %xmm1
+	sha256msg2 %xmm2, %xmm1
+	sha256msg2 (%eax), %xmm1
+	sha256msg2 0x12(%eax), %xmm1
+	sha256msg2 (%eax,%ebx,2), %xmm1
+
+	.intel_syntax noprefix
+
+	sha1rnds4 xmm1, xmm2, 9
+	sha1rnds4 xmm2, XMMWORD PTR [eax], 7
+	sha1rnds4 xmm3, XMMWORD PTR [eax+0x12], 5
+	sha1rnds4 xmm4, XMMWORD PTR [eax+ebx*2], 1
+	sha1nexte xmm1, xmm2
+	sha1nexte xmm2, XMMWORD PTR [eax]
+	sha1nexte xmm3, XMMWORD PTR [eax+0x12]
+	sha1nexte xmm4, XMMWORD PTR [eax+ebx*2]
+	sha1msg1 xmm1, xmm2
+	sha1msg1 xmm2, XMMWORD PTR [eax]
+	sha1msg1 xmm3, XMMWORD PTR [eax+0x12]
+	sha1msg1 xmm4, XMMWORD PTR [eax+ebx*2]
+	sha1msg2 xmm1, xmm2
+	sha1msg2 xmm2, XMMWORD PTR [eax]
+	sha1msg2 xmm3, XMMWORD PTR [eax+0x12]
+	sha1msg2 xmm4, XMMWORD PTR [eax+ebx*2]
+	sha256rnds2 xmm1, xmm2
+	sha256rnds2 xmm2, XMMWORD PTR [eax]
+	sha256rnds2 xmm3, XMMWORD PTR [eax+0x12]
+	sha256rnds2 xmm4, XMMWORD PTR [eax+ebx*2]
+	sha256rnds2 xmm1, xmm2, xmm0
+	sha256rnds2 xmm2, XMMWORD PTR [eax], xmm0
+	sha256rnds2 xmm3, XMMWORD PTR [eax+0x12], xmm0
+	sha256rnds2 xmm4, XMMWORD PTR [eax+ebx*2], xmm0
+	sha256msg1 xmm1, xmm2
+	sha256msg1 xmm2, XMMWORD PTR [eax]
+	sha256msg1 xmm3, XMMWORD PTR [eax+0x12]
+	sha256msg1 xmm4, XMMWORD PTR [eax+ebx*2]
+	sha256msg2 xmm1, xmm2
+	sha256msg2 xmm2, XMMWORD PTR [eax]
+	sha256msg2 xmm3, XMMWORD PTR [eax+0x12]
+	sha256msg2 xmm4, XMMWORD PTR [eax+ebx*2]

gas/testsuite/gas/i386/x86-64-sha.d

@@ -0,0 +1,72 @@
+#objdump: -dw
+#name: x86-64 SHA
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	0f 3a cc ca 09       	sha1rnds4 \$0x9,%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 3a cc 10 07       	sha1rnds4 \$0x7,\(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 3a cc 58 12 05    	sha1rnds4 \$0x5,0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 3a cc 24 58 01    	sha1rnds4 \$0x1,\(%rax,%rbx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 c8 fa          	sha1nexte %xmm2,%xmm7
+[ 	]*[a-f0-9]+:	44 0f 38 c8 00       	sha1nexte \(%rax\),%xmm8
+[ 	]*[a-f0-9]+:	44 0f 38 c8 48 12    	sha1nexte 0x12\(%rax\),%xmm9
+[ 	]*[a-f0-9]+:	44 0f 38 c8 14 58    	sha1nexte \(%rax,%rbx,2\),%xmm10
+[ 	]*[a-f0-9]+:	0f 38 c9 fa          	sha1msg1 %xmm2,%xmm7
+[ 	]*[a-f0-9]+:	44 0f 38 c9 00       	sha1msg1 \(%rax\),%xmm8
+[ 	]*[a-f0-9]+:	44 0f 38 c9 48 12    	sha1msg1 0x12\(%rax\),%xmm9
+[ 	]*[a-f0-9]+:	44 0f 38 c9 14 58    	sha1msg1 \(%rax,%rbx,2\),%xmm10
+[ 	]*[a-f0-9]+:	0f 38 ca fa          	sha1msg2 %xmm2,%xmm7
+[ 	]*[a-f0-9]+:	44 0f 38 ca 00       	sha1msg2 \(%rax\),%xmm8
+[ 	]*[a-f0-9]+:	44 0f 38 ca 48 12    	sha1msg2 0x12\(%rax\),%xmm9
+[ 	]*[a-f0-9]+:	44 0f 38 ca 14 58    	sha1msg2 \(%rax,%rbx,2\),%xmm10
+[ 	]*[a-f0-9]+:	0f 38 cb ca          	sha256rnds2 (%xmm0,)?%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 08          	sha256rnds2 (%xmm0,)?\(%rax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 48 12       	sha256rnds2 (%xmm0,)?0x12\(%rax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 0c 58       	sha256rnds2 (%xmm0,)?\(%rax,%rbx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb ca          	sha256rnds2 (%xmm0,)?%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 08          	sha256rnds2 (%xmm0,)?\(%rax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 48 12       	sha256rnds2 (%xmm0,)?0x12\(%rax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 0c 58       	sha256rnds2 (%xmm0,)?\(%rax,%rbx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc ca          	sha256msg1 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc 08          	sha256msg1 \(%rax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc 48 12       	sha256msg1 0x12\(%rax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc 0c 58       	sha256msg1 \(%rax,%rbx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd ca          	sha256msg2 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd 08          	sha256msg2 \(%rax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd 48 12       	sha256msg2 0x12\(%rax\),%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd 0c 58       	sha256msg2 \(%rax,%rbx,2\),%xmm1
+[ 	]*[a-f0-9]+:	0f 3a cc ca 09       	sha1rnds4 \$0x9,%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 3a cc 10 07       	sha1rnds4 \$0x7,\(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 3a cc 58 12 05    	sha1rnds4 \$0x5,0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 3a cc 24 58 01    	sha1rnds4 \$0x1,\(%rax,%rbx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 c8 ca          	sha1nexte %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c8 10          	sha1nexte \(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 c8 58 12       	sha1nexte 0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 c8 24 58       	sha1nexte \(%rax,%rbx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 c9 ca          	sha1msg1 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 c9 10          	sha1msg1 \(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 c9 58 12       	sha1msg1 0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 c9 24 58       	sha1msg1 \(%rax,%rbx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 ca ca          	sha1msg2 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 ca 10          	sha1msg2 \(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 ca 58 12       	sha1msg2 0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 ca 24 58       	sha1msg2 \(%rax,%rbx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 cb ca          	sha256rnds2 (%xmm0,)?%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 10          	sha256rnds2 (%xmm0,)?\(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 cb 58 12       	sha256rnds2 (%xmm0,)?0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 cb 24 58       	sha256rnds2 (%xmm0,)?\(%rax,%rbx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 cb ca          	sha256rnds2 (%xmm0,)?%xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cb 10          	sha256rnds2 (%xmm0,)?\(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 cb 58 12       	sha256rnds2 (%xmm0,)?0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 cb 24 58       	sha256rnds2 (%xmm0,)?\(%rax,%rbx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 cc ca          	sha256msg1 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cc 10          	sha256msg1 \(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 cc 58 12       	sha256msg1 0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 cc 24 58       	sha256msg1 \(%rax,%rbx,2\),%xmm4
+[ 	]*[a-f0-9]+:	0f 38 cd ca          	sha256msg2 %xmm2,%xmm1
+[ 	]*[a-f0-9]+:	0f 38 cd 10          	sha256msg2 \(%rax\),%xmm2
+[ 	]*[a-f0-9]+:	0f 38 cd 58 12       	sha256msg2 0x12\(%rax\),%xmm3
+[ 	]*[a-f0-9]+:	0f 38 cd 24 58       	sha256msg2 \(%rax,%rbx,2\),%xmm4

gas/testsuite/gas/i386/x86-64-sha.s

@@ -0,0 +1,73 @@
+# Check SHA instructions
+
+	.allow_index_reg
+	.text
+_start:
+	sha1rnds4 $9, %xmm2, %xmm1
+	sha1rnds4 $7, (%rax), %xmm2
+	sha1rnds4 $5, 0x12(%rax), %xmm3
+	sha1rnds4 $1, (%rax,%rbx,2), %xmm4
+	sha1nexte %xmm2, %xmm7
+	sha1nexte (%rax), %xmm8
+	sha1nexte 0x12(%rax), %xmm9
+	sha1nexte (%rax,%rbx,2), %xmm10
+	sha1msg1 %xmm2, %xmm7
+	sha1msg1 (%rax), %xmm8
+	sha1msg1 0x12(%rax), %xmm9
+	sha1msg1 (%rax,%rbx,2), %xmm10
+	sha1msg2 %xmm2, %xmm7
+	sha1msg2 (%rax), %xmm8
+	sha1msg2 0x12(%rax), %xmm9
+	sha1msg2 (%rax,%rbx,2), %xmm10
+	sha256rnds2 %xmm2, %xmm1
+	sha256rnds2 (%rax), %xmm1
+	sha256rnds2 0x12(%rax), %xmm1
+	sha256rnds2 (%rax,%rbx,2), %xmm1
+	sha256rnds2 %xmm0, %xmm2, %xmm1
+	sha256rnds2 %xmm0, (%rax), %xmm1
+	sha256rnds2 %xmm0, 0x12(%rax), %xmm1
+	sha256rnds2 %xmm0, (%rax,%rbx,2), %xmm1
+	sha256msg1 %xmm2, %xmm1
+	sha256msg1 (%rax), %xmm1
+	sha256msg1 0x12(%rax), %xmm1
+	sha256msg1 (%rax,%rbx,2), %xmm1
+	sha256msg2 %xmm2, %xmm1
+	sha256msg2 (%rax), %xmm1
+	sha256msg2 0x12(%rax), %xmm1
+	sha256msg2 (%rax,%rbx,2), %xmm1
+
+	.intel_syntax noprefix
+
+	sha1rnds4 xmm1, xmm2, 9
+	sha1rnds4 xmm2, XMMWORD PTR [rax], 7
+	sha1rnds4 xmm3, XMMWORD PTR [rax+0x12], 5
+	sha1rnds4 xmm4, XMMWORD PTR [rax+rbx*2], 1
+	sha1nexte xmm1, xmm2
+	sha1nexte xmm2, XMMWORD PTR [rax]
+	sha1nexte xmm3, XMMWORD PTR [rax+0x12]
+	sha1nexte xmm4, XMMWORD PTR [rax+rbx*2]
+	sha1msg1 xmm1, xmm2
+	sha1msg1 xmm2, XMMWORD PTR [rax]
+	sha1msg1 xmm3, XMMWORD PTR [rax+0x12]
+	sha1msg1 xmm4, XMMWORD PTR [rax+rbx*2]
+	sha1msg2 xmm1, xmm2
+	sha1msg2 xmm2, XMMWORD PTR [rax]
+	sha1msg2 xmm3, XMMWORD PTR [rax+0x12]
+	sha1msg2 xmm4, XMMWORD PTR [rax+rbx*2]
+	sha256rnds2 xmm1, xmm2
+	sha256rnds2 xmm2, XMMWORD PTR [rax]
+	sha256rnds2 xmm3, XMMWORD PTR [rax+0x12]
+	sha256rnds2 xmm4, XMMWORD PTR [rax+rbx*2]
+	sha256rnds2 xmm1, xmm2, xmm0
+	sha256rnds2 xmm2, XMMWORD PTR [rax], xmm0
+	sha256rnds2 xmm3, XMMWORD PTR [rax+0x12], xmm0
+	sha256rnds2 xmm4, XMMWORD PTR [rax+rbx*2], xmm0
+	sha256msg1 xmm1, xmm2
+	sha256msg1 xmm2, XMMWORD PTR [rax]
+	sha256msg1 xmm3, XMMWORD PTR [rax+0x12]
+	sha256msg1 xmm4, XMMWORD PTR [rax+rbx*2]
+	sha256msg2 xmm1, xmm2
+	sha256msg2 xmm2, XMMWORD PTR [rax]
+	sha256msg2 xmm3, XMMWORD PTR [rax+0x12]
+	sha256msg2 xmm4, XMMWORD PTR [rax+rbx*2]
+

opcodes/ChangeLog

@@ -1,3 +1,20 @@
+2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
+	PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
+	PREFIX_0F3ACC.
+	(prefix_table): Updated.
+	(three_byte_table): Likewise.
+	* i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
+	(cpu_flags): Add CpuSHA.
+	(i386_cpu_flags): Add cpusha.
+	* i386-init.h: Regenerate.
+	* i386-opc.h (CpuSHA): New.
+	(CpuUnused): Restored.
+	(i386_cpu_flags): Add cpusha.
+	* i386-opc.tbl: Add SHA instructions.
+	* i386-tbl.h: Regenerate.
+
 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 	    Kirill Yukhin  <kirill.yukhin@intel.com>
 	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

opcodes/i386-dis.c

@@ -861,6 +861,12 @@ enum
   PREFIX_0F3880,
   PREFIX_0F3881,
   PREFIX_0F3882,
+  PREFIX_0F38C8,
+  PREFIX_0F38C9,
+  PREFIX_0F38CA,
+  PREFIX_0F38CB,
+  PREFIX_0F38CC,
+  PREFIX_0F38CD,
   PREFIX_0F38DB,
   PREFIX_0F38DC,
   PREFIX_0F38DD,
@@ -891,6 +897,7 @@ enum
   PREFIX_0F3A61,
   PREFIX_0F3A62,
   PREFIX_0F3A63,
+  PREFIX_0F3ACC,
   PREFIX_0F3ADF,
   PREFIX_VEX_0F10,
   PREFIX_VEX_0F11,
@@ -3495,6 +3502,36 @@ static const struct dis386 prefix_table[][4] = {
     { "invpcid", { Gm, M } },
   },
 
+  /* PREFIX_0F38C8 */
+  {
+    { "sha1nexte", { XM, EXxmm } },
+  },
+
+  /* PREFIX_0F38C9 */
+  {
+    { "sha1msg1", { XM, EXxmm } },
+  },
+
+  /* PREFIX_0F38CA */
+  {
+    { "sha1msg2", { XM, EXxmm } },
+  },
+
+  /* PREFIX_0F38CB */
+  {
+    { "sha256rnds2", { XM, EXxmm, XMM0 } },
+  },
+
+  /* PREFIX_0F38CC */
+  {
+    { "sha256msg1", { XM, EXxmm } },
+  },
+
+  /* PREFIX_0F38CD */
+  {
+    { "sha256msg2", { XM, EXxmm } },
+  },
+
   /* PREFIX_0F38DB */
   {
     { Bad_Opcode },
@@ -3708,6 +3745,11 @@ static const struct dis386 prefix_table[][4] = {
     { "pcmpistri", { XM, EXx, Ib } },
   },
 
+  /* PREFIX_0F3ACC */
+  {
+    { "sha1rnds4", { XM, EXxmm, Ib } },
+  },
+
   /* PREFIX_0F3ADF */
   {
     { Bad_Opcode },
@@ -6073,12 +6115,12 @@ static const struct dis386 three_byte_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* c8 */
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38C8) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38C9) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38CA) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38CB) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38CC) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38CD) },
     { Bad_Opcode },
     { Bad_Opcode },
     /* d0 */
@@ -6368,7 +6410,7 @@ static const struct dis386 three_byte_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F3ACC) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },

opcodes/i386-gen.c

@@ -210,6 +210,8 @@ static initializer cpu_flag_init[] =
     "CpuSMAP" },
   { "CPU_MPX_FLAGS",
     "CpuMPX" },
+  { "CPU_SHA_FLAGS",
+    "CpuSHA" },
 };
 
 static initializer operand_type_init[] =
@@ -386,6 +388,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuADX),
   BITFIELD (CpuPRFCHW),
   BITFIELD (CpuSMAP),
+  BITFIELD (CpuSHA),
   BITFIELD (Cpu64),
   BITFIELD (CpuNo64),
   BITFIELD (CpuMPX),

opcodes/i386-init.h

@@ -23,505 +23,511 @@
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1,  \
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
-      1, 1, 0, 1 } }
+      1, 1, 1, 0, 1, 1 } }
 
 #define CPU_GENERIC32_FLAGS \
   { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_GENERIC64_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_NONE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_I186_FLAGS \
   { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_I286_FLAGS \
   { { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_I386_FLAGS \
   { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_I486_FLAGS \
   { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_I586_FLAGS \
   { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_I686_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_PENTIUMPRO_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_P2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_P3_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_P4_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_NOCONA_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_CORE_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_CORE2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_COREI7_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_K6_FLAGS \
   { { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_K6_2_FLAGS \
   { { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_ATHLON_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_K8_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_AMDFAM10_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
       0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_BDVER1_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1,  \
       1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      1, 0, 0, 0 } }
+      1, 0, 0, 0, 0, 0 } }
 
 #define CPU_BDVER2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,  \
       1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      1, 0, 0, 0 } }
+      1, 0, 0, 0, 0, 0 } }
 
 #define CPU_BDVER3_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1,  \
       1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      1, 0, 0, 0 } }
+      1, 0, 0, 0, 0, 0 } }
 
 #define CPU_BTVER1_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      1, 0, 0, 0 } }
+      1, 0, 0, 0, 0, 0 } }
 
 #define CPU_BTVER2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,  \
       0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0,  \
       0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0,  \
-      1, 0, 0, 0 } }
+      1, 0, 0, 0, 0, 0 } }
 
 #define CPU_8087_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_287_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_387_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_ANY87_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_CLFLUSH_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_NOP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SYSCALL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_MMX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SSE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SSE2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SSE3_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SSSE3_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SSE4_1_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SSE4_2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SSE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_VMX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SMX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_XSAVE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_XSAVEOPT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_AES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_PCLMUL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_FMA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_FMA4_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_XOP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_LWP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_BMI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_TBM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_MOVBE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_CX16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_RDTSCP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_EPT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_FSGSBASE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_RDRND_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_F16C_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_BMI2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_LZCNT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_HLE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_RTM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_INVPCID_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_VMFUNC_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_3DNOW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_3DNOWA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_PADLOCK_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SVME_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_SSE4A_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_ABM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_AVX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_AVX2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1,  \
       0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_L1OM_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
-      1, 1, 0, 1 } }
+      1, 1, 1, 0, 1, 1 } }
 
 #define CPU_K1OM_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
-      1, 1, 0, 1 } }
+      1, 1, 1, 0, 1, 1 } }
 
 #define CPU_ADX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_RDSEED_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
 
 #define CPU_PRFCHW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      1, 0, 0, 0 } }
+      1, 0, 0, 0, 0, 0 } }
 
 #define CPU_SMAP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
-      0, 1, 0, 0 } }
+      0, 1, 0, 0, 0, 0 } }
 
 #define CPU_MPX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,  \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0 } }
+
+#define CPU_SHA_FLAGS \
+  { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
+      0, 0, 1, 0, 0, 0 } }
 
 
 #define OPERAND_TYPE_NONE \

opcodes/i386-opc.h

@@ -156,6 +156,8 @@ enum
   CpuPRFCHW,
   /* SMAP instructions required.  */
   CpuSMAP,
+  /* SHA instructions required.  */
+  CpuSHA,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -171,7 +173,7 @@ enum
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
-/* #define CpuUnused	(CpuMax + 1) */
+#define CpuUnused	(CpuMax + 1)
 
 /* We can check if an instruction is available with array instead
    of bitfield. */
@@ -241,6 +243,7 @@ typedef union i386_cpu_flags
       unsigned int cpuadx:1;
       unsigned int cpuprfchw:1;
       unsigned int cpusmap:1;
+      unsigned int cpusha:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused

opcodes/i386-opc.tbl

@@ -3069,3 +3069,13 @@ bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No
 bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
 bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+
+// SHA instructions.
+sha1rnds4, 3, 0xf3acc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+sha1nexte, 2, 0xf38c8, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+sha1msg1, 2, 0xf38c9, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+sha1msg2, 2, 0xf38ca, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+sha256rnds2, 3, 0xf38cb, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+sha256rnds2, 2, 0xf38cb, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+sha256msg1, 2, 0xf38cc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+sha256msg2, 2, 0xf38cd, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }