MIPS/opcodes: Address issues with NAL disassembly

Address issues with the disassembly of the NAL assembly idiom and R6
instruction introduced with commit 7361da2c95 ("Add support for MIPS
R6.") and then further tweaked with commit b9121b573e ("Add in a JALRC
alias and fix the NAL instruction.").  As from R6 this instruction has
replaced the encoding of `bltzal $0, . + 4' as the solely supported form
of the former BLTZAL instruction for the regular MIPS ISA.

The instruction is marked as an alias only in our regular MIPS opcode
table, making it fail to disassemble in R6 code if the `no-aliases'
machine option has been passed to `objdump':

$ cat test.s
	.text
foo:
	nal
$ as -mips64r6 -o test.o test.s
$ objdump -dr --prefix-addresses --show-raw-insn -M no-aliases test.o

nal.o:     file format elf32-tradbigmips

Disassembly of section .text:
00000000 <foo> 04100000 	0x4100000
	...
$

This is because the `bltzal' entry has been marked as pre-R6 only in the
opcode table and there is no other opcode pattern to match.

Additionally the changes referred made NAL replace the equivalent
`bltzal $0, . + 4' instruction in disassembly, unless the `no-aliases'
machine option has been used, in legacy code.  Seeing NAL, especially in
its updated form lacking the branch target argument, in the disassembly
of such code may be confusing to people.  This is because unlike with
EHB only used in R2 and newer code -- the machine encoding of which we
anyway always disassemble to its corresponding current architecture's
mnemonic rather than its legacy meaning of `sll $0, $0, 3' -- BLTZAL has
been indeed used in legacy code.  Even though `bltzal $0, . + 8' and its
machine code encoding (0x04100001) -- which is not equivalent to NAL and
still disassembles as BLTZAL -- has been the predominant form as opposed
to NAL's `bltzal $0, . + 4' (0x04100000), it makes sense to always keep
the old form in disassembly, while still accepting `nal' in assembly.

Remove the alias marking then from the the `nal' instruction pattern,
making it always match for R6 code, even with the `no-aliases' option.
And move the entry beyond the `bltzal' entry, making the latter one take
precedence for legacy binary code, while letting the former still match
any `nal' mnemonic in source code assembled for a legacy target.

Add a suitable test case to the GAS test suite.  While the change
affects the disassembler more than the assembler, so placing the test
case in the binutils test suite might be more appropriate, the intent is
also to verify that `nal' is still accepted by GAS for legacy targets,
plus we have test infrastructure available in the GAS test suite for
automatic multiple ISA level testing, which we lack from the binutils
framework.

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
	annotation from the "nal" entry and reorder it beyond "bltzal".

	gas/
	* testsuite/gas/mips/nal-1.d: New test.
	* testsuite/gas/mips/mipsr6@nal-1.d: New test.
	* testsuite/gas/mips/nal-2.d: New test.
	* testsuite/gas/mips/mipsr6@nal-2.d: New test.
	* testsuite/gas/mips/nal.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

gas/ChangeLog

@@ -1,3 +1,12 @@
+2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* testsuite/gas/mips/nal-1.d: New test.
+	* testsuite/gas/mips/mipsr6@nal-1.d: New test.
+	* testsuite/gas/mips/nal-2.d: New test.
+	* testsuite/gas/mips/mipsr6@nal-2.d: New test.
+	* testsuite/gas/mips/nal.s: New test source.
+	* testsuite/gas/mips/mips.exp: Run the new tests.
+
 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* testsuite/gas/sparc/ldtxa.s: New file.

gas/testsuite/gas/mips/mips.exp

@@ -612,6 +612,9 @@ if { [istarget mips*-*-vxworks*] } {
 	run_dump_test "branch-local-n64-1"
     }
 
+    run_dump_test_arches "nal-1" [mips_arch_list_matching mips1 !micromips]
+    run_dump_test_arches "nal-2" [mips_arch_list_matching mips1 !micromips]
+
     run_dump_test "compact-eh-eb-1"
     run_dump_test "compact-eh-eb-2"
     run_dump_test "compact-eh-eb-3"

gas/testsuite/gas/mips/mipsr6@nal-1.d

@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS NAL instruction/idiom 1
+#as: -32
+#source: nal.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 04100000 	nal
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 03e00009 	jr	ra
+[0-9a-f]+ <[^>]*> 00000000 	nop
+	\.\.\.

gas/testsuite/gas/mips/mipsr6@nal-2.d

@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M no-aliases
+#name: MIPS NAL instruction/idiom 2
+#as: -32
+#source: nal.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 04100000 	nal
+[0-9a-f]+ <[^>]*> 00000000 	sll	zero,zero,0x0
+[0-9a-f]+ <[^>]*> 03e00009 	jalr	zero,ra
+[0-9a-f]+ <[^>]*> 00000000 	sll	zero,zero,0x0
+	\.\.\.

gas/testsuite/gas/mips/nal-1.d

@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS NAL instruction/idiom 1
+#as: -32
+#source: nal.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 04100000 	bltzal	zero,00000004 <foo\+0x4>
+[0-9a-f]+ <[^>]*> 00000000 	nop
+[0-9a-f]+ <[^>]*> 03e00008 	jr	ra
+[0-9a-f]+ <[^>]*> 00000000 	nop
+	\.\.\.

gas/testsuite/gas/mips/nal-2.d

@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M no-aliases
+#name: MIPS NAL instruction/idiom 2
+#as: -32
+#source: nal.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 04100000 	bltzal	zero,00000004 <foo\+0x4>
+[0-9a-f]+ <[^>]*> 00000000 	sll	zero,zero,0x0
+[0-9a-f]+ <[^>]*> 03e00008 	jr	ra
+[0-9a-f]+ <[^>]*> 00000000 	sll	zero,zero,0x0
+	\.\.\.

gas/testsuite/gas/mips/nal.s

@@ -0,0 +1,11 @@
+	.text
+	.globl	foo
+	.ent	foo
+foo:
+	nal
+	jr	$ra
+	.end	foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	4, 0
+	.space	16

opcodes/ChangeLog

@@ -1,3 +1,8 @@
+2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
+	annotation from the "nal" entry and reorder it beyond "bltzal".
+
 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* sparc-opc.c (ldtxa): New macro.

opcodes/mips-opc.c

@@ -431,7 +431,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"move",		"d,s",		0x00000021, 0xfc1f07ff, WR_1|RD_2,		INSN2_ALIAS,	I1,		0,	0 },/* addu */
 {"b",			"p",		0x10000000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 },/* beq 0,0 */
 {"b",			"p",		0x04010000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 },/* bgez 0 */
-{"nal",			"",		0x04100000, 0xffffffff,	WR_31|CBD,		INSN2_ALIAS,	I1,		0,	0 },/* bltzal 0 */
 {"bal",			"p",		0x04110000, 0xffff0000,	WR_31|UBD,		INSN2_ALIAS,	I1,		0,	0 },/* bgezal 0*/
 {"bc",			"+'",		0xc8000000, 0xfc000000,	NODS,			0,		I37,		0,	0 },
 {"balc",		"+'",		0xe8000000, 0xfc000000,	WR_31|NODS,		0,		I37,		0,	0 },
@@ -750,6 +749,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bltz",		"s,p",		0x04000000, 0xfc1f0000,	RD_1|CBD,		0,		I1,		0,	0 },
 {"bltzl",		"s,p",		0x04020000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	I37 },
 {"bltzal",		"s,p",		0x04100000, 0xfc1f0000,	RD_1|WR_31|CBD,		0,		I1,		0,	I37 },
+{"nal",			"",		0x04100000, 0xffffffff,	WR_31|CBD,		0,		I1,		0,	0 }, /* bltzal 0,.+4 */
 {"bltzall",		"s,p",		0x04120000, 0xfc1f0000,	RD_1|WR_31|CBL,		0,		I2|T3,		0,	I37 },
 {"bnez",		"s,p",		0x14000000, 0xfc1f0000,	RD_1|CBD,		0,		I1,		0,	0 },
 {"bnezl",		"s,p",		0x54000000, 0xfc1f0000,	RD_1|CBL,		0,		I2|T3,		0,	I37 },