* gas/mips/sync.d: Pass -mips2 to the assembler.
* gas/mips/elf_e_flags.s: Tweak code so that the tests pass for mips-elf target as well as mips64-elf target. * gas/mips/elf_e_flags1.d: Corresponding changes. * gas/mips/elf_e_flags2.d: Likewise. * gas/mips/elf_e_flags3.d: Likewise. * gas/mips/elf_e_flags4.d: Likewise. * gas/elf/elf.exp: Add setup_xfail for mips*-*-*. * gas/all/itbl-test.c (main): Update itbl_get_reg_val call for new parameter.
This commit is contained in:
Ian Lance Taylor
parent
a22b281cd7
commit
8ee99f93eb
10 changed files with 54 additions and 26 deletions
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@ -1,3 +1,19 @@
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1999-06-10 Ian Lance Taylor <ian@zembu.com>
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* gas/mips/sync.d: Pass -mips2 to the assembler.
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* gas/mips/elf_e_flags.s: Tweak code so that the tests pass for
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mips-elf target as well as mips64-elf target.
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* gas/mips/elf_e_flags1.d: Corresponding changes.
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* gas/mips/elf_e_flags2.d: Likewise.
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* gas/mips/elf_e_flags3.d: Likewise.
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* gas/mips/elf_e_flags4.d: Likewise.
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* gas/elf/elf.exp: Add setup_xfail for mips*-*-*.
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* gas/all/itbl-test.c (main): Update itbl_get_reg_val call for new
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parameter.
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1999-06-10 Jakub Jelinek <jj@ultra.linux.cz>
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* gas/sparc/synth64.s: Add checks for single register signx/clruw.
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@ -118,8 +118,8 @@ test_reg (e_processor processor, e_type type, char *name,
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n, processor, type, val);
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/* We require that names be unique amoung processors and types. */
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v = itbl_get_reg_val (name);
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if (!v || v != val)
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if (! itbl_get_reg_val (name, &v)
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|| v != val)
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printf ("Error - reg val not found for processor=%d, type=%d, name=%s\n",
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processor, type, name);
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else
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@ -8,7 +8,11 @@ if { [istarget "*-elf*"]
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|| [istarget "sparc*-*-solaris*"]
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|| [istarget "mips*-*-irix6*"] } then {
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# FIXME: This doesn't work for MIPS targets because of the .reginfo
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# and .mdebug sections.
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setup_xfail mips*-*-*
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run_dump_test "section0"
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run_dump_test "section1"
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setup_xfail mips*-*-*
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run_dump_test "section1"
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}
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@ -9,7 +9,11 @@
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We use the -m4650 flag to get the 4650-specific 'mul' instruction
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in there; the test suite wants to be sure that GAS's -m4650 flag
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will indeed cause it to generate the 4650 mul instruction, and not
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expand it as a macro. */
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expand it as a macro.
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Ian 10 June 1999: I tweaked the resulting assembler file so that it
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would generate the same code when gas was configured for mips-elf
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and for mips64-elf. */
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int
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foo (int a, int b)
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@ -28,11 +28,11 @@ main:
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.mask 0x80000000,-8
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.fmask 0x00000000,0
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subu $sp,$sp,40
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sd $31,32($sp)
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sw $31,32($sp)
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jal __gccmain
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move $2,$0
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ld $31,32($sp)
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#nop
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lw $31,32($sp)
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nop
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.set noreorder
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.set nomacro
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j $31
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@ -3,7 +3,7 @@
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# objdump: -fd
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.*:.*file format.*mips.*
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architecture: mips:4000, flags 0x00000011:
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architecture: mips:[34]000, flags 0x00000011:
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HAS_RELOC, HAS_SYMS
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start address 0x0000000000000000
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@ -17,10 +17,11 @@ Disassembly of section .text:
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0000000000000010 <main>:
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10: 27bdffd8 addiu \$sp,\$sp,-40
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14: ffbf0020 sd \$ra,32\(\$sp\)
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14: afbf0020 sw \$ra,32\(\$sp\)
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18: 0c000000 jal 0 <foo>
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1c: 00000000 nop
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20: 0000102d move \$v0,\$zero
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24: dfbf0020 ld \$ra,32\(\$sp\)
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28: 03e00008 jr \$ra
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2c: 27bd0028 addiu \$sp,\$sp,40
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20: 0000102[1d] move \$v0,\$zero
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24: 8fbf0020 lw \$ra,32\(\$sp\)
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28: 00000000 nop
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2c: 03e00008 jr \$ra
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30: 27bd0028 addiu \$sp,\$sp,40
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@ -17,10 +17,11 @@ Disassembly of section .text:
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000000000000000c <main>:
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c: 27bdffd8 addiu \$sp,\$sp,-40
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10: ffbf0020 sd \$ra,32\(\$sp\)
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10: afbf0020 sw \$ra,32\(\$sp\)
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14: 0c000000 jal 0 <foo>
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18: 00000000 nop
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1c: 0000102d move \$v0,\$zero
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20: dfbf0020 ld \$ra,32\(\$sp\)
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24: 03e00008 jr \$ra
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28: 27bd0028 addiu \$sp,\$sp,40
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20: 8fbf0020 lw \$ra,32\(\$sp\)
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24: 00000000 nop
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28: 03e00008 jr \$ra
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2c: 27bd0028 addiu \$sp,\$sp,40
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@ -17,10 +17,11 @@ Disassembly of section .text:
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000000000000000c <main>:
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c: 27bdffd8 addiu \$sp,\$sp,-40
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10: ffbf0020 sd \$ra,32\(\$sp\)
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10: afbf0020 sw \$ra,32\(\$sp\)
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14: 0c000000 jal 0 <foo>
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18: 00000000 nop
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1c: 0000102d move \$v0,\$zero
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20: dfbf0020 ld \$ra,32\(\$sp\)
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24: 03e00008 jr \$ra
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28: 27bd0028 addiu \$sp,\$sp,40
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20: 8fbf0020 lw \$ra,32\(\$sp\)
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24: 00000000 nop
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28: 03e00008 jr \$ra
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2c: 27bd0028 addiu \$sp,\$sp,40
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@ -17,10 +17,11 @@ Disassembly of section .text:
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000000000000000c <main>:
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c: 27bdffd8 addiu \$sp,\$sp,-40
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10: ffbf0020 sd \$ra,32\(\$sp\)
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10: afbf0020 sw \$ra,32\(\$sp\)
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14: 0c000000 jal 0 <foo>
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18: 00000000 nop
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1c: 0000102d move \$v0,\$zero
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20: dfbf0020 ld \$ra,32\(\$sp\)
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24: 03e00008 jr \$ra
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28: 27bd0028 addiu \$sp,\$sp,40
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20: 8fbf0020 lw \$ra,32\(\$sp\)
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24: 00000000 nop
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28: 03e00008 jr \$ra
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2c: 27bd0028 addiu \$sp,\$sp,40
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@ -1,6 +1,6 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: sync instructions
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#as:
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#as: -mips2
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.*: +file format .*mips.*
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