* config/tc-alpha.c (load_expression): Disable the sym+const .got
optimization to reduce the alignment surprises for gcc.
This commit is contained in:
Richard Henderson
parent
8ac26d165e
commit
8a8a91a5b7
2 changed files with 94 additions and 60 deletions
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@ -1,3 +1,8 @@
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Wed Oct 8 16:28:53 1997 Richard Henderson <rth@cygnus.com>
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* config/tc-alpha.c (load_expression): Disable the sym+const .got
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optimization to reduce the alignment surprises for gcc.
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Wed Oct 8 16:11:15 1997 Doug Evans <dje@canuck.cygnus.com>
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* config/obj-coff.h (TC_SPARC): Don't define TARGET_FORMAT.
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@ -401,6 +401,45 @@ static int alpha_flag_show_after_trunc = 0; /* -H */
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static int alpha_basereg_clobbered;
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#endif
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/* A table of CPU names and opcode sets. */
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static const struct cpu_type
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{
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const char *name;
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unsigned flags;
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} cpu_types[] =
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{
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/* Ad hoc convention: cpu number gets palcode, process code doesn't.
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This supports usage under DU 4.0b that does ".arch ev4", and
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usage in MILO that does -m21064. Probably something more
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specific like -m21064-pal should be used, but oh well. */
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{ "21064", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "21064a", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "21066", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "21068", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "21164", AXP_OPCODE_BASE|AXP_OPCODE_EV5 },
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/* Do we have CIX extension here? */
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{ "21164a", AXP_OPCODE_BASE|AXP_OPCODE_EV5|AXP_OPCODE_BWX },
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/* Still same PALcodes? */
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{ "21164pc", (AXP_OPCODE_BASE|AXP_OPCODE_EV5|AXP_OPCODE_BWX
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|AXP_OPCODE_CIX|AXP_OPCODE_MAX) },
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/* All new PALcodes? Extras? */
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{ "21264", (AXP_OPCODE_BASE|AXP_OPCODE_BWX
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|AXP_OPCODE_CIX|AXP_OPCODE_MAX) },
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{ "ev4", AXP_OPCODE_BASE },
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{ "ev45", AXP_OPCODE_BASE },
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{ "lca45", AXP_OPCODE_BASE },
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{ "ev5", AXP_OPCODE_BASE },
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{ "ev56", AXP_OPCODE_BASE|AXP_OPCODE_BWX },
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{ "pca56", AXP_OPCODE_BASE|AXP_OPCODE_BWX|AXP_OPCODE_CIX|AXP_OPCODE_MAX },
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{ "ev6", AXP_OPCODE_BASE|AXP_OPCODE_BWX|AXP_OPCODE_CIX|AXP_OPCODE_MAX },
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{ "all", AXP_OPCODE_BASE },
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{ 0 }
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};
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/* The macro table */
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static const struct alpha_macro alpha_macros[] = {
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@ -639,38 +678,30 @@ static const int alpha_num_macros
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void
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md_begin ()
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{
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unsigned int i = 0;
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unsigned int i;
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/* Create the opcode hash table */
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alpha_opcode_hash = hash_new ();
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for (i = 0; i < alpha_num_opcodes; )
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{
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const char *name, *retval;
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const char *name, *retval, *slash;
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name = alpha_opcodes[i].name;
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retval = hash_insert (alpha_opcode_hash, name, (PTR)&alpha_opcodes[i]);
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if (retval)
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as_fatal ("internal error: can't hash opcode `%s': %s", name, retval);
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while (++i < alpha_num_opcodes
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&& (alpha_opcodes[i].name == name
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|| !strcmp (alpha_opcodes[i].name, name)))
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continue;
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}
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/* Some opcodes include modifiers of various sorts with a "/mod"
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syntax, like the architecture manual suggests. However, for
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use with gcc at least, we also need access to those same opcodes
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without the "/". */
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/* Some opcodes include modifiers of various sorts with a "/mod" syntax,
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like the architecture manual suggests. However, for use with gcc at
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least, we also need access to those same opcodes without the "/". */
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for (i = 0; i < alpha_num_opcodes; )
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{
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const char *name, *slash;
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name = alpha_opcodes[i].name;
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if ((slash = strchr(name, '/')) != NULL)
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if ((slash = strchr (name, '/')) != NULL)
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{
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char *p = xmalloc (strlen (name));
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memcpy(p, name, slash-name);
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strcpy(p+(slash-name), slash+1);
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memcpy (p, name, slash - name);
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strcpy (p + (slash - name), slash + 1);
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(void)hash_insert(alpha_opcode_hash, p, (PTR)&alpha_opcodes[i]);
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/* Ignore failures -- the opcode table does duplicate some
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@ -892,41 +923,8 @@ md_parse_option (c, arg)
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case 'm':
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{
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static const struct machine
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{
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const char *name;
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unsigned flags;
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} *p, m[] =
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{
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{ "21064", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "21064a", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "21066", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "21068", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "21164", AXP_OPCODE_BASE|AXP_OPCODE_EV5 },
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/* Do we have CIX extension here? */
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{ "21164a", AXP_OPCODE_BASE|AXP_OPCODE_EV5|AXP_OPCODE_BWX },
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/* Still same PALcodes? */
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{ "21164pc", (AXP_OPCODE_BASE|AXP_OPCODE_EV5|AXP_OPCODE_BWX
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|AXP_OPCODE_CIX|AXP_OPCODE_MAX) },
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/* All new PALcodes? Extras? */
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{ "21264", (AXP_OPCODE_BASE|AXP_OPCODE_BWX
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|AXP_OPCODE_CIX|AXP_OPCODE_MAX) },
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{ "ev4", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "ev45", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "lca45", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
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{ "ev5", AXP_OPCODE_BASE|AXP_OPCODE_EV5 },
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{ "ev56", AXP_OPCODE_BASE|AXP_OPCODE_EV5|AXP_OPCODE_BWX },
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{ "pca56", (AXP_OPCODE_BASE|AXP_OPCODE_EV5|AXP_OPCODE_BWX
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|AXP_OPCODE_CIX|AXP_OPCODE_MAX) },
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{ "ev6", (AXP_OPCODE_BASE|AXP_OPCODE_BWX
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|AXP_OPCODE_CIX|AXP_OPCODE_MAX) },
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{ "all", AXP_OPCODE_BASE },
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{ 0 }
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};
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for (p = m; p->name; ++p)
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const struct cpu_type *p;
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for (p = cpu_types; p->name; ++p)
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if (strcmp(arg, p->name) == 0)
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{
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alpha_target_name = p->name, alpha_target = p->flags;
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@ -2241,7 +2239,10 @@ load_expression (targreg, exp, pbasereg, poffset)
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else
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set_tok_reg (newtok[0], targreg);
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if (!range_signed_32 (addend)
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/* XXX: Disable this .got minimizing optimization so that we can get
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better instruction offset knowledge in the compiler. This happens
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very infrequently anyway. */
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if (1 || !range_signed_32 (addend)
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&& (alpha_noat_on || targreg == AXP_REG_AT))
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{
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newtok[1] = *exp;
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@ -4018,6 +4019,7 @@ s_alpha_proc (is_static)
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int temp;
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/* Takes ".proc name,nargs" */
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SKIP_WHITESPACE ();
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name = input_line_pointer;
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c = get_symbol_end ();
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p = input_line_pointer;
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@ -4049,13 +4051,12 @@ static void
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s_alpha_set (x)
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int x;
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{
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char *name = input_line_pointer, ch, *s;
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char *name, ch, *s;
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int yesno = 1;
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while (!is_end_of_line[(unsigned char) *input_line_pointer])
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input_line_pointer++;
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ch = *input_line_pointer;
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*input_line_pointer = '\0';
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SKIP_WHITESPACE ();
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name = input_line_pointer;
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ch = get_symbol_end ();
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s = name;
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if (s[0] == 'n' && s[1] == 'o')
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@ -4214,6 +4215,32 @@ s_alpha_ucons (bytes)
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alpha_auto_align_on = hold;
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}
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/* Switch the working cpu type. */
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static void
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s_alpha_arch (ignored)
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int ignored;
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{
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char *name, ch;
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const struct cpu_type *p;
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SKIP_WHITESPACE ();
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name = input_line_pointer;
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ch = get_symbol_end ();
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for (p = cpu_types; p->name; ++p)
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if (strcmp(name, p->name) == 0)
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{
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alpha_target_name = p->name, alpha_target = p->flags;
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goto found;
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}
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as_warn("Unknown CPU identifier `%s'", name);
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found:
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*input_line_pointer = ch;
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demand_empty_rest_of_line ();
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}
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#ifdef DEBUG1
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@ -4331,6 +4358,8 @@ const pseudo_typeS md_pseudo_table[] =
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{"noalias", s_ignore, 0},
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{"alias", s_ignore, 0},
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{"arch", s_alpha_arch, 0},
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{NULL, 0, 0},
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};
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