gas/testsuite/
2007-07-29 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4834 * gas/i386/simd-intel.d: Updated. * gas/i386/simd.d: Likewise. * gas/i386/x86-64-simd-intel.d: Likewise. * gas/i386/x86-64-simd.d: Likewise. * gas/i386/simd.s: Add tests for SSE4 instructions. * gas/i386/x86-64-simd.s: Likewise. opcodes/ 2007-07-29 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4834 * i386-dis.c (EXw): New. (prefix_user_table): Updated to use EXw, EXd and EXq for SSE4 instructions when appropriated.
This commit is contained in:
parent
59d5bbeb35
commit
8976381e69
9 changed files with 112 additions and 13 deletions
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@ -1,3 +1,14 @@
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2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/4834
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* gas/i386/simd-intel.d: Updated.
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* gas/i386/simd.d: Likewise.
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* gas/i386/x86-64-simd-intel.d: Likewise.
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* gas/i386/x86-64-simd.d: Likewise.
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* gas/i386/simd.s: Add tests for SSE4 instructions.
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* gas/i386/x86-64-simd.s: Likewise.
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2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/simd.s: Add tests for cvtss2si/cvtsd2si in Intel
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@ -70,6 +70,19 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss xmm0,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: f2 0f 5c 00 subsd xmm0,QWORD PTR \[eax\]
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[ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 20 00 pmovsxbw xmm0,QWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 21 00 pmovsxbd xmm0,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 22 00 pmovsxbq xmm0,WORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 23 00 pmovsxwd xmm0,QWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 24 00 pmovsxwq xmm0,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 25 00 pmovsxdq xmm0,QWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 30 00 pmovzxbw xmm0,QWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 31 00 pmovzxbd xmm0,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 32 00 pmovzxbq xmm0,WORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 33 00 pmovzxwd xmm0,QWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 34 00 pmovzxwq xmm0,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq xmm0,QWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps xmm0,DWORD PTR \[eax\],0x0
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[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[eax\]
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#pass
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@ -69,6 +69,19 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss \(%eax\),%xmm0
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[ ]*[a-f0-9]+: f2 0f 5c 00 subsd \(%eax\),%xmm0
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[ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 20 00 pmovsxbw \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 21 00 pmovsxbd \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 22 00 pmovsxbq \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 23 00 pmovsxwd \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 24 00 pmovsxwq \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 25 00 pmovsxdq \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 30 00 pmovzxbw \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 31 00 pmovzxbd \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 32 00 pmovzxbq \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 33 00 pmovzxwd \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 34 00 pmovzxwq \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq \(%eax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps \$0x0,\(%eax\),%xmm0
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[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%eax\),%eax
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[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%eax\),%eax
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#pass
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@ -64,6 +64,20 @@ _start:
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subsd (%eax),%xmm0
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subss (%eax),%xmm0
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pmovsxbw (%eax),%xmm0
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pmovsxbd (%eax),%xmm0
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pmovsxbq (%eax),%xmm0
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pmovsxwd (%eax),%xmm0
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pmovsxwq (%eax),%xmm0
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pmovsxdq (%eax),%xmm0
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pmovzxbw (%eax),%xmm0
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pmovzxbd (%eax),%xmm0
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pmovzxbq (%eax),%xmm0
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pmovzxwd (%eax),%xmm0
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pmovzxwq (%eax),%xmm0
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pmovzxdq (%eax),%xmm0
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insertps $0x0,(%eax),%xmm0
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.intel_syntax noprefix
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cvtss2si eax,DWORD PTR [eax]
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cvtsd2si eax,QWORD PTR [eax]
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@ -74,6 +74,19 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss xmm0,DWORD PTR \[rax\]
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[ ]*[a-f0-9]+: f2 0f 5c 00 subsd xmm0,QWORD PTR \[rax\]
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[ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 20 00 pmovsxbw xmm0,QWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 21 00 pmovsxbd xmm0,DWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 22 00 pmovsxbq xmm0,WORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 23 00 pmovsxwd xmm0,QWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 24 00 pmovsxwq xmm0,DWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 25 00 pmovsxdq xmm0,QWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 30 00 pmovzxbw xmm0,QWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 31 00 pmovzxbd xmm0,DWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 32 00 pmovzxbq xmm0,WORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 33 00 pmovzxwd xmm0,QWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 34 00 pmovzxwq xmm0,DWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq xmm0,QWORD PTR \[rax\]
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[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps xmm0,DWORD PTR \[rax\],0x0
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[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[rax\]
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[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si rax,DWORD PTR \[rax\]
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[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[rax\]
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@ -73,6 +73,19 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss \(%rax\),%xmm0
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[ ]*[a-f0-9]+: f2 0f 5c 00 subsd \(%rax\),%xmm0
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[ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 20 00 pmovsxbw \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 21 00 pmovsxbd \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 22 00 pmovsxbq \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 23 00 pmovsxwd \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 24 00 pmovsxwq \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 25 00 pmovsxdq \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 30 00 pmovzxbw \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 31 00 pmovzxbd \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 32 00 pmovzxbq \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 33 00 pmovzxwd \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 34 00 pmovzxwq \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps \$0x0,\(%rax\),%xmm0
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[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax
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[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax
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[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax
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@ -68,6 +68,20 @@ _start:
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subsd (%rax),%xmm0
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subss (%rax),%xmm0
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pmovsxbw (%rax),%xmm0
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pmovsxbd (%rax),%xmm0
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pmovsxbq (%rax),%xmm0
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pmovsxwd (%rax),%xmm0
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pmovsxwq (%rax),%xmm0
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pmovsxdq (%rax),%xmm0
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pmovzxbw (%rax),%xmm0
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pmovzxbd (%rax),%xmm0
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pmovzxbq (%rax),%xmm0
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pmovzxwd (%rax),%xmm0
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pmovzxwq (%rax),%xmm0
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pmovzxdq (%rax),%xmm0
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insertps $0x0,(%rax),%xmm0
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.intel_syntax noprefix
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cvtss2si eax,DWORD PTR [rax]
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cvtss2si rax,DWORD PTR [rax]
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@ -1,3 +1,10 @@
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2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/4834
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* i386-dis.c (EXw): New.
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(prefix_user_table): Updated to use EXw, EXd and EXq for SSE4
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instructions when appropriated.
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2007-07-28 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/4834
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@ -311,6 +311,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define EM { OP_EM, v_mode }
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#define EMd { OP_EM, d_mode }
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#define EMx { OP_EM, x_mode }
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#define EXw { OP_EX, w_mode }
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#define EXd { OP_EX, d_mode }
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#define EXq { OP_EX, q_mode }
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#define EXx { OP_EX, x_mode }
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@ -2153,7 +2154,7 @@ static const struct dis386 prefix_user_table[][4] = {
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovsxbw", { XM, EXx } },
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{ "pmovsxbw", { XM, EXq } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovsxbd", { XM, EXx } },
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{ "pmovsxbd", { XM, EXd } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovsxbq", { XM, EXx } },
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{ "pmovsxbq", { XM, EXw } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovsxwd", { XM, EXx } },
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{ "pmovsxwd", { XM, EXq } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovsxwq", { XM, EXx } },
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{ "pmovsxwq", { XM, EXd } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovsxdq", { XM, EXx } },
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{ "pmovsxdq", { XM, EXq } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovzxbw", { XM, EXx } },
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{ "pmovzxbw", { XM, EXq } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovzxbd", { XM, EXx } },
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{ "pmovzxbd", { XM, EXd } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovzxbq", { XM, EXx } },
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{ "pmovzxbq", { XM, EXw } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovzxwd", { XM, EXx } },
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{ "pmovzxwd", { XM, EXq } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovzxwq", { XM, EXx } },
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{ "pmovzxwq", { XM, EXd } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "pmovzxdq", { XM, EXx } },
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{ "pmovzxdq", { XM, EXq } },
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{ "(bad)", { XX } },
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},
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "insertps", { XM, EXx, Ib } },
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{ "insertps", { XM, EXd, Ib } },
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{ "(bad)", { XX } },
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},
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