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Fix ld2w r2,@r2 so that r3 loads the proper value

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This commit is contained in:
Michael Meissner 1996-10-13 02:25:01 +00:00
parent aee4f36a89
commit 8918b3a72b
2 changed files with 115 additions and 13 deletions
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22
sim/d10v/ChangeLog
View file

@ -1,7 +1,29 @@
Sat Oct 12 22:17:43 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* simops.c (OP_{31000000,6601,6201,6200}): Store address in a
temporary in case the register is overriden when loading.
(OP_6200): Output type is OP_DREG for tracing.
Fri Oct 4 23:46:18 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* d10v_sim.h (struct _state): Add mem_{min,max} fields.
* interp.c (sim_size): Initialize mem_{min,max} fields.
(sim_write): Update mem_{min,max} fields.
(sim_resume): If PC is not in the minimum/maximum memory range,
abort.
(sim_create_inferior): Preserve mem_{min,max} fields.
Fri Sep 27 13:11:58 1996 Mark Alexander <marka@cygnus.com>
* simops.c (OP_5F00): Add support for time() system call.
Wed Sep 25 16:31:41 1996 Michael Meissner <meissner@tiktok.cygnus.com> Wed Sep 25 16:31:41 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* simops.c (OP_{6E01,6A01,6E1F,6A00}): Print both words being * simops.c (OP_{6E01,6A01,6E1F,6A00}): Print both words being
stored if tracing. stored if tracing.
(OP_5F00,trace_{in,out}put_func): Add finer grain tracing for
system calls.
Mon Sep 23 17:55:30 1996 Michael Meissner <meissner@tiktok.cygnus.com> Mon Sep 23 17:55:30 1996 Michael Meissner <meissner@tiktok.cygnus.com>

106
sim/d10v/simops.c
View file

@ -33,7 +33,9 @@ enum op_types {
OP_POSTINC, OP_POSTINC,
OP_PREDEC, OP_PREDEC,
OP_R2, OP_R2,
OP_R3 OP_R3,
OP_R4,
OP_R2R3
}; };
#ifdef DEBUG #ifdef DEBUG
@ -193,6 +195,7 @@ trace_input_func (name, in1, in2, in3)
case OP_VOID: case OP_VOID:
case OP_R2: case OP_R2:
case OP_R3: case OP_R3:
case OP_R4:
break; break;
case OP_REG: case OP_REG:
@ -398,6 +401,11 @@ trace_input_func (name, in1, in2, in3)
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)State.regs[3]); (uint16)State.regs[3]);
break; break;
case OP_R4:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)State.regs[4]);
break;
} }
} }
} }
@ -464,6 +472,18 @@ trace_output_func (result)
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "", (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
State.F0 != 0, State.F1 != 0, State.C != 0); State.F0 != 0, State.F1 != 0, State.C != 0);
break; break;
case OP_R2:
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
(uint16)State.regs[2],
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_R2R3:
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
(uint16)State.regs[2], (uint16)State.regs[3],
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
} }
} }
} }
@ -1194,9 +1214,10 @@ OP_6000 ()
void void
OP_31000000 () OP_31000000 ()
{ {
uint16 addr = State.regs[OP[2]];
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]); State.regs[OP[0]] = RW (OP[1] + addr);
State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2); State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
trace_output (OP_DREG); trace_output (OP_DREG);
} }
@ -1204,9 +1225,10 @@ OP_31000000 ()
void void
OP_6601 () OP_6601 ()
{ {
uint16 addr = State.regs[OP[1]];
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
State.regs[OP[0]] = RW (State.regs[OP[1]]); State.regs[OP[0]] = RW (addr);
State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2); State.regs[OP[0]+1] = RW (addr+2);
INC_ADDR(State.regs[OP[1]],-4); INC_ADDR(State.regs[OP[1]],-4);
trace_output (OP_DREG); trace_output (OP_DREG);
} }
@ -1215,21 +1237,23 @@ OP_6601 ()
void void
OP_6201 () OP_6201 ()
{ {
uint16 addr = State.regs[OP[1]];
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
State.regs[OP[0]] = RW (State.regs[OP[1]]); State.regs[OP[0]] = RW (addr);
State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2); State.regs[OP[0]+1] = RW (addr+2);
INC_ADDR(State.regs[OP[1]],4); INC_ADDR(State.regs[OP[1]],4);
trace_output (OP_REG); trace_output (OP_DREG);
} }
/* ld2w */ /* ld2w */
void void
OP_6200 () OP_6200 ()
{ {
uint16 addr = State.regs[OP[1]];
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
State.regs[OP[0]] = RW (State.regs[OP[1]]); State.regs[OP[0]] = RW (addr);
State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2); State.regs[OP[0]+1] = RW (addr+2);
trace_output (OP_REG); trace_output (OP_DREG);
} }
/* ldb */ /* ldb */
@ -2542,7 +2566,7 @@ OP_5F00 ()
{ {
trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID); trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
trace_output (OP_VOID); trace_output (OP_VOID);
switch (OP[0]) switch (OP[0])
{ {
default: default:
@ -2609,14 +2633,23 @@ OP_5F00 ()
#if !defined(__GO32__) && !defined(_WIN32) #if !defined(__GO32__) && !defined(_WIN32)
case SYS_fork: case SYS_fork:
RETVAL = fork (); RETVAL = fork ();
trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
trace_output (OP_R2);
break; break;
case SYS_execve: case SYS_execve:
RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
(char **)MEMPTR (PARM3)); (char **)MEMPTR (PARM3));
trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2);
break; break;
case SYS_execv: case SYS_execv:
RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
trace_output (OP_R2);
break; break;
case SYS_pipe: case SYS_pipe:
{ {
reg_t buf; reg_t buf;
@ -2627,21 +2660,31 @@ OP_5F00 ()
SW (buf, host_fd[0]); SW (buf, host_fd[0]);
buf += sizeof(uint16); buf += sizeof(uint16);
SW (buf, host_fd[1]); SW (buf, host_fd[1]);
trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
trace_output (OP_R2);
} }
break; break;
case SYS_wait: case SYS_wait:
{ {
int status; int status;
RETVAL = wait (&status); RETVAL = wait (&status);
SW (PARM1, status); if (PARM1)
SW (PARM1, status);
trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
trace_output (OP_R2);
} }
break; break;
#endif #endif
case SYS_read: case SYS_read:
RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2), RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
PARM3); PARM3);
trace_input ("<read>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2);
break; break;
case SYS_write: case SYS_write:
if (PARM1 == 1) if (PARM1 == 1)
RETVAL = (int)d10v_callback->write_stdout (d10v_callback, RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
@ -2649,7 +2692,10 @@ OP_5F00 ()
else else
RETVAL = (int)d10v_callback->write (d10v_callback, PARM1, RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
MEMPTR (PARM2), PARM3); MEMPTR (PARM2), PARM3);
trace_input ("<write>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2);
break; break;
case SYS_lseek: case SYS_lseek:
{ {
unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1, unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
@ -2658,15 +2704,28 @@ OP_5F00 ()
RETVAL_HIGH = ret >> 16; RETVAL_HIGH = ret >> 16;
RETVAL_LOW = ret & 0xffff; RETVAL_LOW = ret & 0xffff;
} }
trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2R3);
break; break;
case SYS_close: case SYS_close:
RETVAL = d10v_callback->close (d10v_callback, PARM1); RETVAL = d10v_callback->close (d10v_callback, PARM1);
trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
trace_output (OP_R2);
break; break;
case SYS_open: case SYS_open:
RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2); RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
trace_input ("<open>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2);
trace_input ("<open>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2);
break; break;
case SYS_exit: case SYS_exit:
State.exception = SIG_D10V_EXIT; State.exception = SIG_D10V_EXIT;
trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
trace_output (OP_VOID);
break; break;
case SYS_stat: case SYS_stat:
@ -2694,19 +2753,40 @@ OP_5F00 ()
SLW (buf+28, host_stat.st_mtime); SLW (buf+28, host_stat.st_mtime);
SLW (buf+36, host_stat.st_ctime); SLW (buf+36, host_stat.st_ctime);
} }
trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
trace_output (OP_R2);
break; break;
case SYS_chown: case SYS_chown:
RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2);
break; break;
case SYS_chmod: case SYS_chmod:
RETVAL = chmod (MEMPTR (PARM1), PARM2); RETVAL = chmod (MEMPTR (PARM1), PARM2);
trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2);
break; break;
case SYS_utime: case SYS_utime:
/* Cast the second argument to void *, to avoid type mismatch /* Cast the second argument to void *, to avoid type mismatch
if a prototype is present. */ if a prototype is present. */
RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2);
break; break;
case SYS_time:
{
unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
RETVAL_HIGH = ret >> 16;
RETVAL_LOW = ret & 0xffff;
}
trace_input ("<time>", OP_R2, OP_R3, OP_R4);
trace_output (OP_R2R3);
break;
default: default:
abort (); abort ();
} }