* gas/all/fwdexp.d: Also look for f8ffffff.
* gas/arm/msr-reg-thumb.d: Skip for non-ELF based targets. * gas/arm/vldr.d: Likewise. * gas/arm/thumb2_ldmstm.d: Allow for extra NOPs at the end of the disassembly. * gas/cfi/cfi.exp (cfi-arm-1): Only run for ELF based ARM targets.
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6 changed files with 16 additions and 1 deletions
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@ -1,3 +1,11 @@
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2010-10-22 Nick Clifton <nickc@redhat.com>
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* gas/all/fwdexp.d: Also look for f8ffffff.
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* gas/arm/msr-reg-thumb.d: Skip for non-ELF based targets.
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* gas/arm/vldr.d: Likewise.
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* gas/arm/thumb2_ldmstm.d: Allow for extra NOPs at the end of the disassembly.
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* gas/cfi/cfi.exp (cfi-arm-1): Only run for ELF based ARM targets.
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2010-10-21 Joseph Myers <joseph@codesourcery.com>
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* gas/tic6x/attr-arch-directive-1.d,
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@ -8,4 +8,4 @@ OFFSET +TYPE +VALUE
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0+ .*(\.data|i)(|\+0xf+e|\+0xf+c|\+0xf+8)
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Contents of section .*
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0+ (0+|feff|fffe|fcffffff|fffffffc|f8ffffff ffffffff|ffffffff fffffff8) .*
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0+ (0+|feff|fffe|fcffffff|fffffffc|f8ffffff|f8ffffff ffffffff|ffffffff fffffff8) .*
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@ -2,6 +2,7 @@
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# as: -march=armv7-a -mthumb
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# source: msr-reg.s
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# objdump: -dr --prefix-addresses --show-raw-insn
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# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
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.*: +file format .*arm.*
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@ -57,3 +57,4 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> 9800 ldr r0, \[sp, #0\]
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0[0-9a-f]+ <[^>]+> f848 9b04 str.w r9, \[r8\], #4
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0[0-9a-f]+ <[^>]+> f8c8 9000 str.w r9, \[r8\]
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#pass
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@ -2,6 +2,7 @@
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# as: -mfpu=vfp3 -mcpu=cortex-a8 -mthumb
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# source: vldr.s
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# objdump: -dr --prefix-addresses --show-raw-insn
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# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
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.*: +file format .*arm.*
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@ -73,6 +73,10 @@ if { [istarget "i*86-*-*"] || [istarget "x86_64-*-*"] } then {
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}
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} elseif { [istarget "arm*-*"] || [istarget "xscale*-*"] } then {
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# Only ELF based ARM targets support CFI.
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if { [is_pecoff_format] } then {
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return
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}
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run_dump_test "cfi-arm-1"
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} elseif { [istarget "mips*-*"] } then {
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