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PR binutils/15241

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* lm32.cpu (Control and status registers): Add CFG2, PSW,
	TLBVADDR, TLBPADDR and TLBBADVADDR.

	* lm32-desc.c: Regenerate.
This commit is contained in:
Nick Clifton 2013-03-08 17:25:12 +00:00
parent abb3f6cca7
commit 87a8d6cbe0
4 changed files with 20 additions and 3 deletions
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6
cpu/ChangeLog
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@ -1,3 +1,9 @@
2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
PR binutils/15241
* lm32.cpu (Control and status registers): Add CFG2, PSW,
TLBVADDR, TLBPADDR and TLBBADVADDR.
2012-11-30 Oleg Raikhman <oleg@adapteva.com> 2012-11-30 Oleg Raikhman <oleg@adapteva.com>
Joern Rennecke <joern.rennecke@embecosm.com> Joern Rennecke <joern.rennecke@embecosm.com>

4
cpu/lm32.cpu
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@ -1,5 +1,5 @@
; Lattice Mico32 CPU description. -*- Scheme -*- ; Lattice Mico32 CPU description. -*- Scheme -*-
; Copyright 2008, 2009 Free Software Foundation, Inc. ; Copyright 2008-2013 Free Software Foundation, Inc.
; Contributed by Jon Beniston <jon@beniston.com> ; Contributed by Jon Beniston <jon@beniston.com>
; ;
; This file is part of the GNU Binutils. ; This file is part of the GNU Binutils.
@ -101,9 +101,11 @@
(EBA 7) (EBA 7)
(DC 8) (DC 8)
(DEBA 9) (DEBA 9)
(CFG2 10)
(JTX 14) (JRX 15) (JTX 14) (JRX 15)
(BP0 16) (BP1 17) (BP2 18) (BP3 19) (BP0 16) (BP1 17) (BP2 18) (BP3 19)
(WP0 24) (WP1 25) (WP2 26) (WP3 27) (WP0 24) (WP1 25) (WP2 26) (WP3 27)
(PSW 29) (TLBVADDR 30) (TLBPADDR 31) (TLBBADVADDR 31)
) )
) )
() () () ()

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
* lm32-desc.c: Regenerate.
2013-03-01 H.J. Lu <hongjiu.lu@intel.com> 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-reg.tbl (riz): Add RegRex64. * i386-reg.tbl (riz): Add RegRex64.

9
opcodes/lm32-desc.c
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@ -185,6 +185,7 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
{ "EBA", 7, {0, {{{0, 0}}}}, 0, 0 }, { "EBA", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "DC", 8, {0, {{{0, 0}}}}, 0, 0 }, { "DC", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 }, { "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "CFG2", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "JTX", 14, {0, {{{0, 0}}}}, 0, 0 }, { "JTX", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "JRX", 15, {0, {{{0, 0}}}}, 0, 0 }, { "JRX", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "BP0", 16, {0, {{{0, 0}}}}, 0, 0 }, { "BP0", 16, {0, {{{0, 0}}}}, 0, 0 },
@ -194,13 +195,17 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
{ "WP0", 24, {0, {{{0, 0}}}}, 0, 0 }, { "WP0", 24, {0, {{{0, 0}}}}, 0, 0 },
{ "WP1", 25, {0, {{{0, 0}}}}, 0, 0 }, { "WP1", 25, {0, {{{0, 0}}}}, 0, 0 },
{ "WP2", 26, {0, {{{0, 0}}}}, 0, 0 }, { "WP2", 26, {0, {{{0, 0}}}}, 0, 0 },
{ "WP3", 27, {0, {{{0, 0}}}}, 0, 0 } { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 },
{ "PSW", 29, {0, {{{0, 0}}}}, 0, 0 },
{ "TLBVADDR", 30, {0, {{{0, 0}}}}, 0, 0 },
{ "TLBPADDR", 31, {0, {{{0, 0}}}}, 0, 0 },
{ "TLBBADVADDR", 31, {0, {{{0, 0}}}}, 0, 0 }
}; };
CGEN_KEYWORD lm32_cgen_opval_h_csr = CGEN_KEYWORD lm32_cgen_opval_h_csr =
{ {
& lm32_cgen_opval_h_csr_entries[0], & lm32_cgen_opval_h_csr_entries[0],
20, 25,
0, 0, 0, 0, "" 0, 0, 0, 0, ""
}; };