* m68hc11_sim.c (cpu_move8): Call sim_engine_abort in default case.
(cpu_move16): Likewise. (sim_memory_error): Use sim_io_printf. (cpu_option_handler): Fix compilation warning. * interp.c (sim_hw_configure): Fix compilation warning; remove m68hc12sio@2 device. (sim_open): Likewise. * dv-m68hc11tim.c (m68hc11tim_port_event): Fix clear of TFLG2 flags when reset. (cycle_to_string): Improve convertion of cpu cycle number. (m68hc11tim_info): Print info about PACNT. (m68hc11tim_io_write_buffer): Fix clearing of TFLG2; handle TCTL1 and TCTL2 registers. * dv-m68hc11.c (m68hc11_info): Print 6811 current running mode.
This commit is contained in:
Stephane Carrez
parent
827ec39a5a
commit
86596dc8e0
5 changed files with 77 additions and 35 deletions
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@ -1,3 +1,20 @@
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2002-03-07 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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* m68hc11_sim.c (cpu_move8): Call sim_engine_abort in default case.
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(cpu_move16): Likewise.
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(sim_memory_error): Use sim_io_printf.
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(cpu_option_handler): Fix compilation warning.
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* interp.c (sim_hw_configure): Fix compilation warning;
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remove m68hc12sio@2 device.
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(sim_open): Likewise.
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* dv-m68hc11tim.c (m68hc11tim_port_event): Fix clear of TFLG2
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flags when reset.
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(cycle_to_string): Improve convertion of cpu cycle number.
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(m68hc11tim_info): Print info about PACNT.
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(m68hc11tim_io_write_buffer): Fix clearing of TFLG2; handle
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TCTL1 and TCTL2 registers.
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* dv-m68hc11.c (m68hc11_info): Print 6811 current running mode.
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2002-03-07 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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* interp.c (sim_hw_configure): Save the HW cpu pointer in the
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@ -591,7 +591,21 @@ m68hc11_info (struct hw *me)
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val = cpu->ios[M6811_HPRIO];
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print_io_byte (sd, "HPRIO ", hprio_desc, val, base + M6811_HPRIO);
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sim_io_printf (sd, "\n");
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switch (cpu->cpu_mode)
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{
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case M6811_MDA | M6811_SMOD:
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sim_io_printf (sd, "[test]\n");
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break;
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case M6811_SMOD:
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sim_io_printf (sd, "[bootstrap]\n");
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break;
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case M6811_MDA:
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sim_io_printf (sd, "[extended]\n");
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break;
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default:
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sim_io_printf (sd, "[single]\n");
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break;
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}
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val = cpu->ios[M6811_CONFIG];
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print_io_byte (sd, "CONFIG", config_desc, val, base + M6811_CONFIG);
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@ -194,12 +194,12 @@ m68hc11tim_port_event (struct hw *me,
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}
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/* Reset the state of Timer registers. This also restarts
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the timer events (overflow and RTI clock). */
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the timer events (overflow and RTI clock). The pending
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flags (TFLG2) must be cleared explicitly here. */
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val = 0;
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cpu->ios[M6811_TFLG2] = 0;
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m68hc11tim_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_TMSK2, 1);
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m68hc11tim_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_TFLG2, 1);
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m68hc11tim_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_PACTL, 1);
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break;
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@ -436,17 +436,19 @@ const char*
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cycle_to_string (sim_cpu *cpu, signed64 t)
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{
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double dt;
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char tbuf[32];
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static char buf[64];
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dt = to_realtime (cpu, t);
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if (dt < 0.001)
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sprintf (buf, "%llu cycle%s (%3.1f us)", t,
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(t > 1 ? "s" : ""), dt * 1000000.0);
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sprintf (tbuf, "(%3.1f us)", dt * 1000000.0);
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else if (dt < 1.0)
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sprintf (buf, "%llu cycles (%3.1f ms)", t, dt * 1000.0);
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sprintf (tbuf, "(%3.1f ms)", dt * 1000.0);
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else
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sprintf (buf, "%llu cycles (%3.1f s)", t, dt);
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sprintf (tbuf, "(%3.1f s)", dt);
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sprintf (buf, "%llu cycle%s %10.10s", t,
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(t > 1 ? "s" : ""), tbuf);
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return buf;
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}
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@ -503,6 +505,10 @@ m68hc11tim_info (struct hw *me)
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print_io_byte (sd, "PACTL", pactl_desc, val, base + M6811_PACTL);
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sim_io_printf (sd, "\n");
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val = cpu->ios[M6811_PACNT];
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print_io_byte (sd, "PACNT", 0, val, base + M6811_PACNT);
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sim_io_printf (sd, "\n");
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/* Give info about the next timer interrupts. */
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m68hc11tim_print_timer (me, "RTI", controller->rti_timer_event);
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m68hc11tim_print_timer (me, "COP", controller->cop_timer_event);
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@ -625,7 +631,7 @@ m68hc11tim_io_write_buffer (struct hw *me,
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case M6811_TMSK2:
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/* Timer prescaler cannot be changed after 64 bus cycles. */
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/* Timer prescaler cannot be changed after 64 bus cycles. */
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if (cpu->cpu_absolute_cycle >= 64)
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{
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val &= ~(M6811_PR1 | M6811_PR0);
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@ -665,21 +671,22 @@ m68hc11tim_io_write_buffer (struct hw *me,
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break;
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case M6811_TFLG2:
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if (val & M6811_TOF)
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val &= ~M6811_TOF;
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else
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val |= cpu->ios[M6811_TFLG2] & M6811_TOF;
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/* Clear the Real Time interrupt flag. */
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if (val & M6811_RTIF)
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val &= ~M6811_RTIF;
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else
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val |= cpu->ios[M6811_TFLG2] & M6811_RTIF;
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cpu->ios[base] = val;
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val &= cpu->ios[M6811_TFLG2];
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cpu->ios[M6811_TFLG2] &= ~val;
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interrupts_update_pending (&cpu->cpu_interrupts);
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break;
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case M6811_TMSK1:
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cpu->ios[M6811_TMSK1] = val;
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interrupts_update_pending (&cpu->cpu_interrupts);
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break;
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case M6811_TFLG1:
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val &= cpu->ios[M6811_TFLG1];
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cpu->ios[M6811_TFLG1] &= ~val;
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interrupts_update_pending (&cpu->cpu_interrupts);
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break;
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case M6811_TOC1:
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case M6811_TOC2:
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case M6811_TOC3:
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@ -689,7 +696,13 @@ m68hc11tim_io_write_buffer (struct hw *me,
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reset_compare = 1;
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break;
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case M6811_TCTL1:
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case M6811_TCTL2:
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cpu->ios[base] = val;
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break;
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default:
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cpu->ios[base] = val;
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break;
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}
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@ -171,7 +171,6 @@ sim_hw_configure (SIM_DESC sd)
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{
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const struct bfd_arch_info *arch;
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struct hw *device_tree;
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int m6811_mode;
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sim_cpu *cpu;
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arch = STATE_ARCHITECTURE (sd);
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@ -252,12 +251,6 @@ sim_hw_configure (SIM_DESC sd)
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sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
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sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
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}
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if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@2/reg"))
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{
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sim_hw_parse (sd, "/m68hc12/m68hc12sio@2/reg 0xC8 0x8");
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sim_hw_parse (sd, "/m68hc12/m68hc12sio@2/backend tcp");
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sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@2");
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}
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if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
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{
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/* M68hc11 Timer configuration. */
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@ -312,10 +305,8 @@ SIM_DESC
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sim_open (SIM_OPEN_KIND kind, host_callback *callback,
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struct _bfd *abfd, char **argv)
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{
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char **p;
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SIM_DESC sd;
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sim_cpu *cpu;
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struct hw *device_tree;
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sd = sim_state_alloc (kind, callback);
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cpu = STATE_CPU (sd, 0);
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@ -54,7 +54,6 @@ static SIM_RC
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cpu_option_handler (SIM_DESC sd, sim_cpu *cpu,
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int opt, char *arg, int is_command)
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{
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sim_cpu *cpu;
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int val;
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cpu = STATE_CPU (sd, 0);
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@ -393,7 +392,11 @@ cpu_move8 (sim_cpu *cpu, uint8 code)
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src = cpu_get_indexed_operand8 (cpu, 1);
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addr = cpu_get_indexed_operand_addr (cpu, 1);
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break;
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default:
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sim_engine_abort (CPU_STATE (cpu), cpu, 0,
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"Invalid code 0x%0x -- internal error?", code);
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return;
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}
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memory_write8 (cpu, addr, src);
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}
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@ -436,7 +439,11 @@ cpu_move16 (sim_cpu *cpu, uint8 code)
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src = cpu_get_indexed_operand16 (cpu, 1);
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addr = cpu_get_indexed_operand_addr (cpu, 1);
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break;
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default:
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sim_engine_abort (CPU_STATE (cpu), cpu, 0,
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"Invalid code 0x%0x -- internal error?", code);
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return;
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}
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memory_write16 (cpu, addr, src);
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}
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@ -941,7 +948,7 @@ sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
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vsprintf (buf, message, args);
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va_end (args);
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printf("%s\n", buf);
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sim_io_printf (CPU_STATE (cpu), "%s\n", buf);
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cpu_memory_exception (cpu, excep, addr, buf);
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}
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