* pdp11-opc.c: Fix "mark" operand type. Fix operand types
for float opcodes that take float operands. Add alternate names (xxxD vs. xxxF) for float opcodes. * pdp11-dis.c (print_operand): Clean up formatting for mode 67. (print_foperand): New function to handle float opcode operands. (print_insn_pdp11): Use print_foperand to disassemble float ops.
This commit is contained in:
Alan Modra
parent
e4b29ec6bd
commit
84dd1cffbf
3 changed files with 118 additions and 20 deletions
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@ -1,3 +1,12 @@
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2002-03-05 Paul Koning <pkoning@equallogic.com>
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* pdp11-opc.c: Fix "mark" operand type. Fix operand types
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for float opcodes that take float operands. Add alternate
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names (xxxD vs. xxxF) for float opcodes.
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* pdp11-dis.c (print_operand): Clean up formatting for mode 67.
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(print_foperand): New function to handle float opcode operands.
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(print_insn_pdp11): Use print_foperand to disassemble float ops.
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2002-02-27 Nick Clifton <nickc@cambridge.redhat.com>
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* po/de.po: Updated.
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@ -1,5 +1,5 @@
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/* Print DEC PDP-11 instructions.
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Copyright 2001 Free Software Foundation, Inc.
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Copyright 2001, 2002 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -38,6 +38,8 @@ static void print_reg PARAMS ((int reg, disassemble_info *info));
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static void print_freg PARAMS ((int freg, disassemble_info *info));
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static int print_operand PARAMS ((bfd_vma *memaddr, int code,
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disassemble_info *info));
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static int print_foperand PARAMS ((bfd_vma *memaddr, int code,
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disassemble_info *info));
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int print_insn_pdp11 PARAMS ((bfd_vma memaddr, disassemble_info *info));
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static int
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@ -165,8 +167,10 @@ print_operand (memaddr, code, info)
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if (reg == 7)
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{
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bfd_vma address = *memaddr + sign_extend (disp);
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if (mode == 7)
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FPRINTF (F, "*");
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if (!(code & JUMP))
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FPRINTF (F, "*$");
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FPRINTF (F, "$");
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(*info->print_address_func) (address, info);
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}
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else
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@ -184,6 +188,23 @@ print_operand (memaddr, code, info)
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return 0;
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}
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static int
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print_foperand (memaddr, code, info)
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bfd_vma *memaddr;
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int code;
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disassemble_info *info;
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{
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int mode = (code >> 3) & 7;
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int reg = code & 7;
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if (mode == 0)
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print_freg (reg, info);
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else
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return print_operand (memaddr, code, info);
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return 0;
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}
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/* Print the PDP-11 instruction at address MEMADDR in debugged memory,
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on INFO->STREAM. Returns length of the instruction, in bytes. */
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@ -230,6 +251,14 @@ print_insn_pdp11 (memaddr, info)
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if (print_operand (&memaddr, dst, info) < 0)
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return -1;
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goto done;
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case PDP11_OPCODE_FOP:
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FPRINTF (F, OP.name);
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FPRINTF (F, AFTER_INSTRUCTION);
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if (strcmp (OP.name, "jmp") == 0)
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dst |= JUMP;
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if (print_foperand (&memaddr, dst, info) < 0)
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return -1;
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goto done;
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case PDP11_OPCODE_REG_OP:
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FPRINTF (F, OP.name);
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FPRINTF (F, AFTER_INSTRUCTION);
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@ -248,6 +277,28 @@ print_insn_pdp11 (memaddr, info)
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FPRINTF (F, OPERAND_SEPARATOR);
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print_reg (src, info);
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goto done;
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case PDP11_OPCODE_AC_FOP:
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{
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int ac = (opcode & 0xe0) >> 6;
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FPRINTF (F, OP.name);
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FPRINTF (F, AFTER_INSTRUCTION);
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print_freg (ac, info);
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FPRINTF (F, OPERAND_SEPARATOR);
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if (print_foperand (&memaddr, dst, info) < 0)
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return -1;
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goto done;
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}
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case PDP11_OPCODE_FOP_AC:
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{
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int ac = (opcode & 0xe0) >> 6;
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FPRINTF (F, OP.name);
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FPRINTF (F, AFTER_INSTRUCTION);
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if (print_foperand (&memaddr, dst, info) < 0)
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return -1;
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FPRINTF (F, OPERAND_SEPARATOR);
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print_freg (ac, info);
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goto done;
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}
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case PDP11_OPCODE_AC_OP:
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{
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int ac = (opcode & 0xe0) >> 6;
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@ -259,6 +310,17 @@ print_insn_pdp11 (memaddr, info)
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return -1;
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goto done;
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}
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case PDP11_OPCODE_OP_AC:
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{
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int ac = (opcode & 0xe0) >> 6;
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FPRINTF (F, OP.name);
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FPRINTF (F, AFTER_INSTRUCTION);
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if (print_operand (&memaddr, dst, info) < 0)
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return -1;
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FPRINTF (F, OPERAND_SEPARATOR);
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print_freg (ac, info);
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goto done;
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}
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case PDP11_OPCODE_OP_OP:
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FPRINTF (F, OP.name);
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FPRINTF (F, AFTER_INSTRUCTION);
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@ -1,5 +1,5 @@
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/* Opcode table for PDP-11.
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Copyright 2001 Free Software Foundation, Inc.
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Copyright 2001, 2002 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -86,7 +86,7 @@ const struct pdp11_opcode pdp11_opcodes[] =
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{ "rol", 0x0c40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "asr", 0x0c80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "asl", 0x0cc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "mark", 0x0d00, 0xffc0, PDP11_OPCODE_OP, PDP11_LEIS },
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{ "mark", 0x0d00, 0xffc0, PDP11_OPCODE_IMM6, PDP11_LEIS },
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{ "mfpi", 0x0d40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "mtpi", 0x0d80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "sxt", 0x0dc0, 0xffc0, PDP11_OPCODE_OP, PDP11_LEIS },
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@ -211,24 +211,28 @@ const struct pdp11_opcode pdp11_opcodes[] =
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{ "ldfps", 0xf040, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "stfps", 0xf080, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "stst", 0xf0c0, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "clrf", 0xf100, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "tstf", 0xf140, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "absf", 0xf180, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "negf", 0xf1c0, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "mulf", 0xf200, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "modf", 0xf300, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "addf", 0xf400, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "ldf", 0xf500, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },/*movif*/
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{ "subf", 0xf600, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "cmpf", 0xf700, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stf", 0xf800, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },/*movfi*/
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{ "divf", 0xf900, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "clrf", 0xf100, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "tstf", 0xf140, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "absf", 0xf180, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "negf", 0xf1c0, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "mulf", 0xf200, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "modf", 0xf300, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "addf", 0xf400, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "ldf", 0xf500, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/*movif*/
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{ "subf", 0xf600, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "cmpf", 0xf700, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "stf", 0xf800, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/*movfi*/
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{ "divf", 0xf900, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "stexp", 0xfa00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcfi", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcff", 0xfc00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },/* ? */
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{ "ldexp", 0xfd00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "ldcif", 0xfe00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "ldcff", 0xff00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },/* ? */
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{ "stcff", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */
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{ "ldexp", 0xfd00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldcif", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldcff", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */
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/* This entry MUST be last; it is a "catch-all" entry that will match when no
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* other opcode entry matches during disassembly.
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*/
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{ "", 0x0000, 0x0000, PDP11_OPCODE_ILLEGAL, PDP11_NONE },
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};
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const struct pdp11_opcode pdp11_aliases[] =
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@ -239,6 +243,29 @@ const struct pdp11_opcode pdp11_aliases[] =
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{ "bhis", 0x8600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "blo", 0x8700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "trap", 0x8900, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC },
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/* fpp xxxd alternate names to xxxf opcodes */
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{ "clrd", 0xf100, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "tstd", 0xf140, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "absd", 0xf180, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "negd", 0xf1c0, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "muld", 0xf200, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "modd", 0xf300, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "addd", 0xf400, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "ldd", 0xf500, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/*movif*/
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{ "subd", 0xf600, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "cmpd", 0xf700, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "std", 0xf800, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/*movfi*/
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{ "divd", 0xf900, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "stcfl", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcdi", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcdl", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcfd", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */
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{ "stcdf", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */
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{ "ldcid", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldclf", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldcld", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldcfd", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */
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{ "ldcdf", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */
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};
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const int pdp11_num_opcodes = sizeof pdp11_opcodes / sizeof pdp11_opcodes[0];
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