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Remove a29k files.

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This commit is contained in:
Alan Modra 2005-08-18 03:59:24 +00:00
parent c17ae8a24e
commit 848cf006a0
13 changed files with 14 additions and 1425 deletions
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2
bfd/ChangeLog
View file

@ -1,5 +1,7 @@
2005-08-18 Alan Modra <amodra@bigpond.net.au>
* coff-a29k.c: Delete.
* cpu-a29k.c: Delete.
* Makefile.am: Remove mention of a29k files.
* aoutf1.h: Remove a29k support.
* aoutx.h: Likewise.

584
bfd/coff-a29k.c
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@ -1,584 +0,0 @@
/* BFD back-end for AMD 29000 COFF binaries.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2002, 2003, 2004
Free Software Foundation, Inc.
Contributed by David Wood at New York University 7/8/91.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#define A29K 1
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
#include "coff/a29k.h"
#include "coff/internal.h"
#include "libcoff.h"
static long get_symbol_value PARAMS ((asymbol *));
static bfd_reloc_status_type a29k_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static bfd_boolean coff_a29k_relocate_section
PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
struct internal_reloc *, struct internal_syment *, asection **));
static bfd_boolean coff_a29k_adjust_symndx
PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *,
struct internal_reloc *, bfd_boolean *));
static void reloc_processing
PARAMS ((arelent *, struct internal_reloc *, asymbol **, bfd *, asection *));
#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2)
#define INSERT_HWORD(WORD,HWORD) \
(((WORD) & 0xff00ff00) | (((HWORD) & 0xff00) << 8) | ((HWORD)& 0xff))
#define EXTRACT_HWORD(WORD) \
((((WORD) & 0x00ff0000) >> 8) | ((WORD) & 0xff))
#define SIGN_EXTEND_HWORD(HWORD) \
(((HWORD) ^ 0x8000) - 0x8000)
/* Provided the symbol, returns the value reffed. */
static long
get_symbol_value (symbol)
asymbol *symbol;
{
long relocation = 0;
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value +
symbol->section->output_section->vma +
symbol->section->output_offset;
return relocation;
}
/* This function is in charge of performing all the 29k relocations. */
static bfd_reloc_status_type
a29k_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol_in;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message;
{
/* The consth relocation comes in two parts, we have to remember
the state between calls, in these variables. */
static bfd_boolean part1_consth_active = FALSE;
static unsigned long part1_consth_value;
unsigned long insn;
unsigned long sym_value;
unsigned long unsigned_value;
unsigned short r_type;
long signed_value;
unsigned long addr = reloc_entry->address ; /*+ input_section->vma*/
bfd_byte *hit_data =addr + (bfd_byte *) (data);
r_type = reloc_entry->howto->type;
if (output_bfd)
{
/* Partial linking - do nothing. */
reloc_entry->address += input_section->output_offset;
return bfd_reloc_ok;
}
if (symbol_in != NULL
&& bfd_is_und_section (symbol_in->section))
{
/* Keep the state machine happy in case we're called again. */
if (r_type == R_IHIHALF)
{
part1_consth_active = TRUE;
part1_consth_value = 0;
}
return bfd_reloc_undefined;
}
if ((part1_consth_active) && (r_type != R_IHCONST))
{
part1_consth_active = FALSE;
*error_message = (char *) _("Missing IHCONST");
return bfd_reloc_dangerous;
}
sym_value = get_symbol_value(symbol_in);
switch (r_type)
{
case R_IREL:
insn = bfd_get_32 (abfd, hit_data);
/* Take the value in the field and sign extend it. */
signed_value = EXTRACT_HWORD(insn);
signed_value = SIGN_EXTEND_HWORD(signed_value);
signed_value <<= 2;
/* See the note on the R_IREL reloc in coff_a29k_relocate_section. */
if (signed_value == - (long) reloc_entry->address)
signed_value = 0;
signed_value += sym_value + reloc_entry->addend;
if ((signed_value & ~0x3ffff) == 0)
{ /* Absolute jmp/call */
insn |= (1 << 24); /* Make it absolute */
/* FIXME: Should we change r_type to R_IABS. */
}
else
{
/* Relative jmp/call, so subtract from the value the
address of the place we're coming from. */
signed_value -= (reloc_entry->address
+ input_section->output_section->vma
+ input_section->output_offset);
if (signed_value > 0x1ffff || signed_value < -0x20000)
return bfd_reloc_overflow;
}
signed_value >>= 2;
insn = INSERT_HWORD (insn, signed_value);
bfd_put_32 (abfd, (bfd_vma) insn ,hit_data);
break;
case R_ILOHALF:
insn = bfd_get_32 (abfd, hit_data);
unsigned_value = EXTRACT_HWORD(insn);
unsigned_value += sym_value + reloc_entry->addend;
insn = INSERT_HWORD(insn, unsigned_value);
bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
break;
case R_IHIHALF:
insn = bfd_get_32 (abfd, hit_data);
/* consth, part 1
Just get the symbol value that is referenced. */
part1_consth_active = TRUE;
part1_consth_value = sym_value + reloc_entry->addend;
/* Don't modify insn until R_IHCONST. */
break;
case R_IHCONST:
insn = bfd_get_32 (abfd, hit_data);
/* consth, part 2
Now relocate the reference. */
if (! part1_consth_active)
{
*error_message = (char *) _("Missing IHIHALF");
return bfd_reloc_dangerous;
}
/* sym_ptr_ptr = r_symndx, in coff_slurp_reloc_table() */
unsigned_value = 0; /*EXTRACT_HWORD(insn) << 16;*/
unsigned_value += reloc_entry->addend; /* r_symndx */
unsigned_value += part1_consth_value;
unsigned_value = unsigned_value >> 16;
insn = INSERT_HWORD(insn, unsigned_value);
part1_consth_active = FALSE;
bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
break;
case R_BYTE:
insn = bfd_get_8 (abfd, hit_data);
unsigned_value = insn + sym_value + reloc_entry->addend;
if (unsigned_value & 0xffffff00)
return bfd_reloc_overflow;
bfd_put_8 (abfd, unsigned_value, hit_data);
break;
case R_HWORD:
insn = bfd_get_16 (abfd, hit_data);
unsigned_value = insn + sym_value + reloc_entry->addend;
if (unsigned_value & 0xffff0000)
return bfd_reloc_overflow;
bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
break;
case R_WORD:
insn = bfd_get_32 (abfd, hit_data);
insn += sym_value + reloc_entry->addend;
bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
break;
default:
*error_message = _("Unrecognized reloc");
return bfd_reloc_dangerous;
}
return(bfd_reloc_ok);
}
/*FIXME: I'm not real sure about this table. */
static reloc_howto_type howto_table[] =
{
{R_ABS, 0, 3, 32, FALSE, 0, complain_overflow_bitfield,a29k_reloc,"ABS", TRUE, 0xffffffff,0xffffffff, FALSE},
EMPTY_HOWTO (1),
EMPTY_HOWTO (2),
EMPTY_HOWTO (3),
EMPTY_HOWTO (4),
EMPTY_HOWTO (5),
EMPTY_HOWTO (6),
EMPTY_HOWTO (7),
EMPTY_HOWTO (8),
EMPTY_HOWTO (9),
EMPTY_HOWTO (10),
EMPTY_HOWTO (11),
EMPTY_HOWTO (12),
EMPTY_HOWTO (13),
EMPTY_HOWTO (14),
EMPTY_HOWTO (15),
EMPTY_HOWTO (16),
EMPTY_HOWTO (17),
EMPTY_HOWTO (18),
EMPTY_HOWTO (19),
EMPTY_HOWTO (20),
EMPTY_HOWTO (21),
EMPTY_HOWTO (22),
EMPTY_HOWTO (23),
{R_IREL, 0, 3, 32, TRUE, 0, complain_overflow_signed,a29k_reloc,"IREL", TRUE, 0xffffffff,0xffffffff, FALSE},
{R_IABS, 0, 3, 32, FALSE, 0, complain_overflow_bitfield, a29k_reloc,"IABS", TRUE, 0xffffffff,0xffffffff, FALSE},
{R_ILOHALF, 0, 3, 16, TRUE, 0, complain_overflow_signed, a29k_reloc,"ILOHALF", TRUE, 0x0000ffff,0x0000ffff, FALSE},
{R_IHIHALF, 0, 3, 16, TRUE, 16, complain_overflow_signed, a29k_reloc,"IHIHALF", TRUE, 0xffff0000,0xffff0000, FALSE},
{R_IHCONST, 0, 3, 16, TRUE, 0, complain_overflow_signed, a29k_reloc,"IHCONST", TRUE, 0xffff0000,0xffff0000, FALSE},
{R_BYTE, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, a29k_reloc,"BYTE", TRUE, 0x000000ff,0x000000ff, FALSE},
{R_HWORD, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, a29k_reloc,"HWORD", TRUE, 0x0000ffff,0x0000ffff, FALSE},
{R_WORD, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, a29k_reloc,"WORD", TRUE, 0xffffffff,0xffffffff, FALSE},
};
#define BADMAG(x) A29KBADMAG(x)
#define RELOC_PROCESSING(relent, reloc, symbols, abfd, section) \
reloc_processing(relent, reloc, symbols, abfd, section)
static void
reloc_processing (relent,reloc, symbols, abfd, section)
arelent *relent;
struct internal_reloc *reloc;
asymbol **symbols;
bfd *abfd;
asection *section;
{
static bfd_vma ihihalf_vaddr = (bfd_vma) -1;
relent->address = reloc->r_vaddr;
relent->howto = howto_table + reloc->r_type;
if (reloc->r_type == R_IHCONST)
{
/* The address of an R_IHCONST should always be the address of
the immediately preceding R_IHIHALF. relocs generated by gas
are correct, but relocs generated by High C are different (I
can't figure out what the address means for High C). We can
handle both gas and High C by ignoring the address here, and
simply reusing the address saved for R_IHIHALF. */
if (ihihalf_vaddr == (bfd_vma) -1)
abort ();
relent->address = ihihalf_vaddr;
ihihalf_vaddr = (bfd_vma) -1;
relent->addend = reloc->r_symndx;
relent->sym_ptr_ptr= bfd_abs_section_ptr->symbol_ptr_ptr;
}
else
{
asymbol *ptr;
relent->sym_ptr_ptr = symbols + obj_convert (abfd)[reloc->r_symndx];
ptr = *(relent->sym_ptr_ptr);
if (ptr
&& bfd_asymbol_bfd(ptr) == abfd
&& ((ptr->flags & BSF_OLD_COMMON) == 0))
relent->addend = 0;
else
relent->addend = 0;
relent->address-= section->vma;
if (reloc->r_type == R_IHIHALF)
ihihalf_vaddr = relent->address;
else if (ihihalf_vaddr != (bfd_vma) -1)
abort ();
}
}
/* The reloc processing routine for the optimized COFF linker. */
static bfd_boolean
coff_a29k_relocate_section (output_bfd, info, input_bfd, input_section,
contents, relocs, syms, sections)
bfd *output_bfd ATTRIBUTE_UNUSED;
struct bfd_link_info *info;
bfd *input_bfd;
asection *input_section;
bfd_byte *contents;
struct internal_reloc *relocs;
struct internal_syment *syms;
asection **sections;
{
struct internal_reloc *rel;
struct internal_reloc *relend;
bfd_boolean hihalf;
bfd_vma hihalf_val;
/* If we are performing a relocatable link, we don't need to do a
thing. The caller will take care of adjusting the reloc
addresses and symbol indices. */
if (info->relocatable)
return TRUE;
hihalf = FALSE;
hihalf_val = 0;
rel = relocs;
relend = rel + input_section->reloc_count;
for (; rel < relend; rel++)
{
long symndx;
bfd_byte *loc;
struct coff_link_hash_entry *h;
struct internal_syment *sym;
asection *sec;
bfd_vma val;
bfd_boolean overflow;
unsigned long insn;
long signed_value;
unsigned long unsigned_value;
bfd_reloc_status_type rstat;
symndx = rel->r_symndx;
loc = contents + rel->r_vaddr - input_section->vma;
if (symndx == -1 || rel->r_type == R_IHCONST)
h = NULL;
else
h = obj_coff_sym_hashes (input_bfd)[symndx];
sym = NULL;
sec = NULL;
val = 0;
/* An R_IHCONST reloc does not have a symbol. Instead, the
symbol index is an addend. R_IHCONST is always used in
conjunction with R_IHHALF. */
if (rel->r_type != R_IHCONST)
{
if (h == NULL)
{
if (symndx == -1)
sec = bfd_abs_section_ptr;
else
{
sym = syms + symndx;
sec = sections[symndx];
val = (sec->output_section->vma
+ sec->output_offset
+ sym->n_value
- sec->vma);
}
}
else
{
if ( h->root.type == bfd_link_hash_defined
|| h->root.type == bfd_link_hash_defweak)
{
sec = h->root.u.def.section;
val = (h->root.u.def.value
+ sec->output_section->vma
+ sec->output_offset);
}
else
{
if (! ((*info->callbacks->undefined_symbol)
(info, h->root.root.string, input_bfd, input_section,
rel->r_vaddr - input_section->vma, TRUE)))
return FALSE;
}
}
if (hihalf)
{
if (! ((*info->callbacks->reloc_dangerous)
(info, _("missing IHCONST reloc"), input_bfd,
input_section, rel->r_vaddr - input_section->vma)))
return FALSE;
hihalf = FALSE;
}
}
overflow = FALSE;
switch (rel->r_type)
{
default:
bfd_set_error (bfd_error_bad_value);
return FALSE;
case R_IREL:
insn = bfd_get_32 (input_bfd, loc);
/* Extract the addend. */
signed_value = EXTRACT_HWORD (insn);
signed_value = SIGN_EXTEND_HWORD (signed_value);
signed_value <<= 2;
/* Unfortunately, there are two different versions of COFF
a29k. In the original AMD version, the value stored in
the field for the R_IREL reloc is a simple addend. In
the GNU version, the value is the negative of the address
of the reloc within section. We try to cope here by
assuming the AMD version, unless the addend is exactly
the negative of the address; in the latter case we assume
the GNU version. This means that something like
.text
nop
jmp i-4
will fail, because the addend of -4 will happen to equal
the negative of the address within the section. The
compiler will never generate code like this.
At some point in the future we may want to take out this
check. */
if (signed_value == - (long) (rel->r_vaddr - input_section->vma))
signed_value = 0;
/* Determine the destination of the jump. */
signed_value += val;
if ((signed_value & ~0x3ffff) == 0)
{
/* We can use an absolute jump. */
insn |= (1 << 24);
}
else
{
/* Make the destination PC relative. */
signed_value -= (input_section->output_section->vma
+ input_section->output_offset
+ (rel->r_vaddr - input_section->vma));
if (signed_value > 0x1ffff || signed_value < - 0x20000)
{
overflow = TRUE;
signed_value = 0;
}
}
/* Put the adjusted value back into the instruction. */
signed_value >>= 2;
insn = INSERT_HWORD (insn, signed_value);
bfd_put_32 (input_bfd, (bfd_vma) insn, loc);
break;
case R_ILOHALF:
insn = bfd_get_32 (input_bfd, loc);
unsigned_value = EXTRACT_HWORD (insn);
unsigned_value += val;
insn = INSERT_HWORD (insn, unsigned_value);
bfd_put_32 (input_bfd, (bfd_vma) insn, loc);
break;
case R_IHIHALF:
/* Save the value for the R_IHCONST reloc. */
hihalf = TRUE;
hihalf_val = val;
break;
case R_IHCONST:
if (! hihalf)
{
if (! ((*info->callbacks->reloc_dangerous)
(info, _("missing IHIHALF reloc"), input_bfd,
input_section, rel->r_vaddr - input_section->vma)))
return FALSE;
hihalf_val = 0;
}
insn = bfd_get_32 (input_bfd, loc);
unsigned_value = rel->r_symndx + hihalf_val;
unsigned_value >>= 16;
insn = INSERT_HWORD (insn, unsigned_value);
bfd_put_32 (input_bfd, (bfd_vma) insn, loc);
hihalf = FALSE;
break;
case R_BYTE:
case R_HWORD:
case R_WORD:
rstat = _bfd_relocate_contents (howto_table + rel->r_type,
input_bfd, val, loc);
if (rstat == bfd_reloc_overflow)
overflow = TRUE;
else if (rstat != bfd_reloc_ok)
abort ();
break;
}
if (overflow)
{
const char *name;
char buf[SYMNMLEN + 1];
if (symndx == -1)
name = "*ABS*";
else if (h != NULL)
name = NULL;
else if (sym == NULL)
name = "*unknown*";
else if (sym->_n._n_n._n_zeroes == 0
&& sym->_n._n_n._n_offset != 0)
name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
else
{
strncpy (buf, sym->_n._n_name, SYMNMLEN);
buf[SYMNMLEN] = '\0';
name = buf;
}
if (! ((*info->callbacks->reloc_overflow)
(info, (h ? &h->root : NULL), name,
howto_table[rel->r_type].name, (bfd_vma) 0, input_bfd,
input_section, rel->r_vaddr - input_section->vma)))
return FALSE;
}
}
return TRUE;
}
#define coff_relocate_section coff_a29k_relocate_section
/* We don't want to change the symndx of a R_IHCONST reloc, since it
is actually an addend, not a symbol index at all. */
static bfd_boolean
coff_a29k_adjust_symndx (obfd, info, ibfd, sec, irel, adjustedp)
bfd *obfd ATTRIBUTE_UNUSED;
struct bfd_link_info *info ATTRIBUTE_UNUSED;
bfd *ibfd ATTRIBUTE_UNUSED;
asection *sec ATTRIBUTE_UNUSED;
struct internal_reloc *irel;
bfd_boolean *adjustedp;
{
if (irel->r_type == R_IHCONST)
*adjustedp = TRUE;
else
*adjustedp = FALSE;
return TRUE;
}
#define coff_adjust_symndx coff_a29k_adjust_symndx
#include "coffcode.h"
CREATE_BIG_COFF_TARGET_VEC (a29kcoff_big_vec, "coff-a29k-big", 0, SEC_READONLY, '_', NULL, COFF_SWAP_TABLE)

39
bfd/cpu-a29k.c
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@ -1,39 +0,0 @@
/* BFD support for the AMD 29000 architecture.
Copyright 1992, 2000, 2002 Free Software Foundation, Inc.
Hacked by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_a29k_arch =
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_a29k,
0, /* only 1 machine */
"a29k",
"a29k",
4,
TRUE, /* the one and only */
bfd_default_compatible,
bfd_default_scan ,
0,
};

4
include/coff/ChangeLog
View file

@ -1,3 +1,7 @@
2005-08-18 Alan Modra <amodra@bigpond.net.au>
* a29k.h: Delete.
2005-07-14 Daniel Marques <marques@cs.cornell.edu>
* alpha.h (ALPHA_ECOFF_COMPRESSEDMAG): Define.

148
include/coff/a29k.h
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@ -1,148 +0,0 @@
/* COFF spec for AMD 290*0
Copyright 2001 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
Contributed by David Wood @ New York University. */
#ifndef AMD
# define AMD
#endif
#define L_LNNO_SIZE 2
#include "coff/external.h"
/*
** Magic numbers for Am29000
** (AT&T will assign the "real" magic number)
*/
#define SIPFBOMAGIC 0572 /* Am29000 (Byte 0 is MSB) */
#define SIPRBOMAGIC 0573 /* Am29000 (Byte 0 is LSB) */
#define A29K_MAGIC_BIG SIPFBOMAGIC
#define A29K_MAGIC_LITTLE SIPRBOMAGIC
#define A29KBADMAG(x) ( ((x).f_magic != A29K_MAGIC_BIG) && \
((x).f_magic != A29K_MAGIC_LITTLE))
#define OMAGIC A29K_MAGIC_BIG
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
/*
** File header flags currently known to us.
**
** Am29000 will use the F_AR32WR and F_AR32W flags to indicate
** the byte ordering in the file.
*/
/*--------------------------------------------------------------*/
/* aouthdr magic numbers */
#define NMAGIC 0410 /* separate i/d executable */
#define SHMAGIC 0406 /* NYU/Ultra3 shared data executable
(writable text) */
#undef _ETEXT
#define _ETEXT "_etext"
/*--------------------------------------------------------------*/
/* More names of "special" sections. */
#define _LIT ".lit"
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
/*
** Section types - with additional section type for global
** registers which will be relocatable for the Am29000.
**
** In instances where it is necessary for a linker to produce an
** output file which contains text or data not based at virtual
** address 0, e.g. for a ROM, then the linker should accept
** address base information as command input and use PAD sections
** to skip over unused addresses.
*/
#define STYP_BSSREG 0x1200 /* Global register area (like STYP_INFO) */
#define STYP_ENVIR 0x2200 /* Environment (like STYP_INFO) */
#define STYP_ABS 0x4000 /* Absolute (allocated, not reloc, loaded) */
/*--------------------------------------------------------------*/
/*
** Relocation information declaration and related definitions
*/
struct external_reloc
{
char r_vaddr[4]; /* (virtual) address of reference */
char r_symndx[4]; /* index into symbol table */
char r_type[2]; /* relocation type */
};
#define RELOC struct external_reloc
#define RELSZ 10 /* sizeof (RELOC) */
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
/*
** Relocation types for the Am29000
*/
#define R_ABS 0 /* reference is absolute */
#define R_IREL 030 /* instruction relative (jmp/call) */
#define R_IABS 031 /* instruction absolute (jmp/call) */
#define R_ILOHALF 032 /* instruction low half (const) */
#define R_IHIHALF 033 /* instruction high half (consth) part 1 */
#define R_IHCONST 034 /* instruction high half (consth) part 2 */
/* constant offset of R_IHIHALF relocation */
#define R_BYTE 035 /* relocatable byte value */
#define R_HWORD 036 /* relocatable halfword value */
#define R_WORD 037 /* relocatable word value */
#define R_IGLBLRC 040 /* instruction global register RC */
#define R_IGLBLRA 041 /* instruction global register RA */
#define R_IGLBLRB 042 /* instruction global register RB */
/*
NOTE:
All the "I" forms refer to 29000 instruction formats. The linker is
expected to know how the numeric information is split and/or aligned
within the instruction word(s). R_BYTE works for instructions, too.
If the parameter to a CONSTH instruction is a relocatable type, two
relocation records are written. The first has an r_type of R_IHIHALF
(33 octal) and a normal r_vaddr and r_symndx. The second relocation
record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which
is redundant), and an r_symndx containing the 32-bit constant offset
to the relocation instead of the actual symbol table index. This
second record is always written, even if the constant offset is zero.
The constant fields of the instruction are set to zero.
*/
/*--------------------------------------------------------------*/
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
/*
** Storage class definitions - new classes for global registers.
*/
#define C_GLBLREG 19 /* global register */
#define C_EXTREG 20 /* external global register */
#define C_DEFREG 21 /* ext. def. of global register */

4
include/opcode/ChangeLog
View file

@ -1,3 +1,7 @@
2005-08-18 Alan Modra <amodra@bigpond.net.au>
* a29k.h: Delete.
2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
* ppc.h (PPC_OPCODE_E300): Define.

281
include/opcode/a29k.h
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@ -1,281 +0,0 @@
/* Table of opcodes for the AMD 29000 family.
Copyright 1990, 1991, 1993, 1994, 2002 Free Software Foundation, Inc.
This file is part of GDB and GAS.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
struct a29k_opcode {
/* Name of the instruction. */
char *name;
/* Opcode word */
unsigned long opcode;
/* A string of characters which describe the operands.
Valid characters are:
, Itself. The character appears in the assembly code.
a RA. The register number is in bits 8-15 of the instruction.
b RB. The register number is in bits 0-7 of the instruction.
c RC. The register number is in bits 16-23 of the instruction.
i An immediate operand is in bits 0-7 of the instruction.
x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15
(respectively) of the immediate operand.
h Same as x but the instruction contains bits 16-31 of the
immediate operand.
X Same as x but bits 16-31 of the signed immediate operand
are set to 1 (thus the operand is always negative).
P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17
(respectively) of the immediate operand.
P=PC-relative, sign-extended to 32 bits.
A=Absolute, zero-extended to 32 bits.
e CE bit (bit 23) for a load/store instruction.
n Control field (bits 16-22) for a load/store instruction.
v Immediate operand in bits 16-23 of the instruction.
(used for trap numbers).
s SA. Special-purpose register number in bits 8-15
of the instruction.
u UI--bit 7 of the instruction.
r RND--bits 4-6 of the instruction.
d FD--bits 2-3 of the instruction.
f FS--bits 0-1 of the instruction.
I ID--bits 16-17 of the instruction.
Extensions for 29050:
d FMT--bits 2-3 of the instruction (not really new).
f ACN--bits 0-1 of the instruction (not really new).
F FUNC--Special function in bits 18-21 of the instruction.
C ACN--bits 16-17 specifying the accumlator register. */
char *args;
};
static const struct a29k_opcode a29k_opcodes[] =
{
{ "add", 0x14000000, "c,a,b" },
{ "add", 0x15000000, "c,a,i" },
{ "addc", 0x1c000000, "c,a,b" },
{ "addc", 0x1d000000, "c,a,i" },
{ "addcs", 0x18000000, "c,a,b" },
{ "addcs", 0x19000000, "c,a,i" },
{ "addcu", 0x1a000000, "c,a,b" },
{ "addcu", 0x1b000000, "c,a,i" },
{ "adds", 0x10000000, "c,a,b" },
{ "adds", 0x11000000, "c,a,i" },
{ "addu", 0x12000000, "c,a,b" },
{ "addu", 0x13000000, "c,a,i" },
{ "and", 0x90000000, "c,a,b" },
{ "and", 0x91000000, "c,a,i" },
{ "andn", 0x9c000000, "c,a,b" },
{ "andn", 0x9d000000, "c,a,i" },
{ "aseq", 0x70000000, "v,a,b" },
{ "aseq", 0x71000000, "v,a,i" },
{ "asge", 0x5c000000, "v,a,b" },
{ "asge", 0x5d000000, "v,a,i" },
{ "asgeu", 0x5e000000, "v,a,b" },
{ "asgeu", 0x5f000000, "v,a,i" },
{ "asgt", 0x58000000, "v,a,b" },
{ "asgt", 0x59000000, "v,a,i" },
{ "asgtu", 0x5a000000, "v,a,b" },
{ "asgtu", 0x5b000000, "v,a,i" },
{ "asle", 0x54000000, "v,a,b" },
{ "asle", 0x55000000, "v,a,i" },
{ "asleu", 0x56000000, "v,a,b" },
{ "asleu", 0x57000000, "v,a,i" },
{ "aslt", 0x50000000, "v,a,b" },
{ "aslt", 0x51000000, "v,a,i" },
{ "asltu", 0x52000000, "v,a,b" },
{ "asltu", 0x53000000, "v,a,i" },
{ "asneq", 0x72000000, "v,a,b" },
{ "asneq", 0x73000000, "v,a,i" },
{ "call", 0xa8000000, "a,P" },
{ "call", 0xa9000000, "a,A" },
{ "calli", 0xc8000000, "a,b" },
{ "class", 0xe6000000, "c,a,f" },
{ "clz", 0x08000000, "c,b" },
{ "clz", 0x09000000, "c,i" },
{ "const", 0x03000000, "a,x" },
{ "consth", 0x02000000, "a,h" },
{ "consthz", 0x05000000, "a,h" },
{ "constn", 0x01000000, "a,X" },
{ "convert", 0xe4000000, "c,a,u,r,d,f" },
{ "cpbyte", 0x2e000000, "c,a,b" },
{ "cpbyte", 0x2f000000, "c,a,i" },
{ "cpeq", 0x60000000, "c,a,b" },
{ "cpeq", 0x61000000, "c,a,i" },
{ "cpge", 0x4c000000, "c,a,b" },
{ "cpge", 0x4d000000, "c,a,i" },
{ "cpgeu", 0x4e000000, "c,a,b" },
{ "cpgeu", 0x4f000000, "c,a,i" },
{ "cpgt", 0x48000000, "c,a,b" },
{ "cpgt", 0x49000000, "c,a,i" },
{ "cpgtu", 0x4a000000, "c,a,b" },
{ "cpgtu", 0x4b000000, "c,a,i" },
{ "cple", 0x44000000, "c,a,b" },
{ "cple", 0x45000000, "c,a,i" },
{ "cpleu", 0x46000000, "c,a,b" },
{ "cpleu", 0x47000000, "c,a,i" },
{ "cplt", 0x40000000, "c,a,b" },
{ "cplt", 0x41000000, "c,a,i" },
{ "cpltu", 0x42000000, "c,a,b" },
{ "cpltu", 0x43000000, "c,a,i" },
{ "cpneq", 0x62000000, "c,a,b" },
{ "cpneq", 0x63000000, "c,a,i" },
{ "dadd", 0xf1000000, "c,a,b" },
{ "ddiv", 0xf7000000, "c,a,b" },
{ "deq", 0xeb000000, "c,a,b" },
{ "dge", 0xef000000, "c,a,b" },
{ "dgt", 0xed000000, "c,a,b" },
{ "div", 0x6a000000, "c,a,b" },
{ "div", 0x6b000000, "c,a,i" },
{ "div0", 0x68000000, "c,b" },
{ "div0", 0x69000000, "c,i" },
{ "divide", 0xe1000000, "c,a,b" },
{ "dividu", 0xe3000000, "c,a,b" },
{ "divl", 0x6c000000, "c,a,b" },
{ "divl", 0x6d000000, "c,a,i" },
{ "divrem", 0x6e000000, "c,a,b" },
{ "divrem", 0x6f000000, "c,a,i" },
{ "dmac", 0xd9000000, "F,C,a,b" },
{ "dmsm", 0xdb000000, "c,a,b" },
{ "dmul", 0xf5000000, "c,a,b" },
{ "dsub", 0xf3000000, "c,a,b" },
{ "emulate", 0xd7000000, "v,a,b" },
{ "exbyte", 0x0a000000, "c,a,b" },
{ "exbyte", 0x0b000000, "c,a,i" },
{ "exhw", 0x7c000000, "c,a,b" },
{ "exhw", 0x7d000000, "c,a,i" },
{ "exhws", 0x7e000000, "c,a" },
{ "extract", 0x7a000000, "c,a,b" },
{ "extract", 0x7b000000, "c,a,i" },
{ "fadd", 0xf0000000, "c,a,b" },
{ "fdiv", 0xf6000000, "c,a,b" },
{ "fdmul", 0xf9000000, "c,a,b" },
{ "feq", 0xea000000, "c,a,b" },
{ "fge", 0xee000000, "c,a,b" },
{ "fgt", 0xec000000, "c,a,b" },
{ "fmac", 0xd8000000, "F,C,a,b" },
{ "fmsm", 0xda000000, "c,a,b" },
{ "fmul", 0xf4000000, "c,a,b" },
{ "fsub", 0xf2000000, "c,a,b" },
{ "halt", 0x89000000, "" },
{ "inbyte", 0x0c000000, "c,a,b" },
{ "inbyte", 0x0d000000, "c,a,i" },
{ "inhw", 0x78000000, "c,a,b" },
{ "inhw", 0x79000000, "c,a,i" },
{ "inv", 0x9f000000, "I" },
{ "iret", 0x88000000, "" },
{ "iretinv", 0x8c000000, "I" },
{ "jmp", 0xa0000000, "P" },
{ "jmp", 0xa1000000, "A" },
{ "jmpf", 0xa4000000, "a,P" },
{ "jmpf", 0xa5000000, "a,A" },
{ "jmpfdec", 0xb4000000, "a,P" },
{ "jmpfdec", 0xb5000000, "a,A" },
{ "jmpfi", 0xc4000000, "a,b" },
{ "jmpi", 0xc0000000, "b" },
{ "jmpt", 0xac000000, "a,P" },
{ "jmpt", 0xad000000, "a,A" },
{ "jmpti", 0xcc000000, "a,b" },
{ "load", 0x16000000, "e,n,a,b" },
{ "load", 0x17000000, "e,n,a,i" },
{ "loadl", 0x06000000, "e,n,a,b" },
{ "loadl", 0x07000000, "e,n,a,i" },
{ "loadm", 0x36000000, "e,n,a,b" },
{ "loadm", 0x37000000, "e,n,a,i" },
{ "loadset", 0x26000000, "e,n,a,b" },
{ "loadset", 0x27000000, "e,n,a,i" },
{ "mfacc", 0xe9000100, "c,d,f" },
{ "mfsr", 0xc6000000, "c,s" },
{ "mftlb", 0xb6000000, "c,a" },
{ "mtacc", 0xe8010000, "a,d,f" },
{ "mtsr", 0xce000000, "s,b" },
{ "mtsrim", 0x04000000, "s,x" },
{ "mttlb", 0xbe000000, "a,b" },
{ "mul", 0x64000000, "c,a,b" },
{ "mul", 0x65000000, "c,a,i" },
{ "mull", 0x66000000, "c,a,b" },
{ "mull", 0x67000000, "c,a,i" },
{ "multiplu", 0xe2000000, "c,a,b" },
{ "multiply", 0xe0000000, "c,a,b" },
{ "multm", 0xde000000, "c,a,b" },
{ "multmu", 0xdf000000, "c,a,b" },
{ "mulu", 0x74000000, "c,a,b" },
{ "mulu", 0x75000000, "c,a,i" },
{ "nand", 0x9a000000, "c,a,b" },
{ "nand", 0x9b000000, "c,a,i" },
{ "nop", 0x70400101, "" },
{ "nor", 0x98000000, "c,a,b" },
{ "nor", 0x99000000, "c,a,i" },
{ "or", 0x92000000, "c,a,b" },
{ "or", 0x93000000, "c,a,i" },
{ "orn", 0xaa000000, "c,a,b" },
{ "orn", 0xab000000, "c,a,i" },
/* The description of "setip" in Chapter 8 ("instruction set") of the user's
manual claims that these are absolute register numbers. But section
7.2.1 explains that they are not. The latter is correct, so print
these normally ("lr0", "lr5", etc.). */
{ "setip", 0x9e000000, "c,a,b" },
{ "sll", 0x80000000, "c,a,b" },
{ "sll", 0x81000000, "c,a,i" },
{ "sqrt", 0xe5000000, "c,a,f" },
{ "sra", 0x86000000, "c,a,b" },
{ "sra", 0x87000000, "c,a,i" },
{ "srl", 0x82000000, "c,a,b" },
{ "srl", 0x83000000, "c,a,i" },
{ "store", 0x1e000000, "e,n,a,b" },
{ "store", 0x1f000000, "e,n,a,i" },
{ "storel", 0x0e000000, "e,n,a,b" },
{ "storel", 0x0f000000, "e,n,a,i" },
{ "storem", 0x3e000000, "e,n,a,b" },
{ "storem", 0x3f000000, "e,n,a,i" },
{ "sub", 0x24000000, "c,a,b" },
{ "sub", 0x25000000, "c,a,i" },
{ "subc", 0x2c000000, "c,a,b" },
{ "subc", 0x2d000000, "c,a,i" },
{ "subcs", 0x28000000, "c,a,b" },
{ "subcs", 0x29000000, "c,a,i" },
{ "subcu", 0x2a000000, "c,a,b" },
{ "subcu", 0x2b000000, "c,a,i" },
{ "subr", 0x34000000, "c,a,b" },
{ "subr", 0x35000000, "c,a,i" },
{ "subrc", 0x3c000000, "c,a,b" },
{ "subrc", 0x3d000000, "c,a,i" },
{ "subrcs", 0x38000000, "c,a,b" },
{ "subrcs", 0x39000000, "c,a,i" },
{ "subrcu", 0x3a000000, "c,a,b" },
{ "subrcu", 0x3b000000, "c,a,i" },
{ "subrs", 0x30000000, "c,a,b" },
{ "subrs", 0x31000000, "c,a,i" },
{ "subru", 0x32000000, "c,a,b" },
{ "subru", 0x33000000, "c,a,i" },
{ "subs", 0x20000000, "c,a,b" },
{ "subs", 0x21000000, "c,a,i" },
{ "subu", 0x22000000, "c,a,b" },
{ "subu", 0x23000000, "c,a,i" },
{ "xnor", 0x96000000, "c,a,b" },
{ "xnor", 0x97000000, "c,a,i" },
{ "xor", 0x94000000, "c,a,b" },
{ "xor", 0x95000000, "c,a,i" },
{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. This
lets code examine entry i+1 without checking
if we've run off the end of the table. */
};
const unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1);

3
ld/ChangeLog
View file

@ -1,5 +1,8 @@
2005-08-18 Alan Modra <amodra@bigpond.net.au>
* emulparams/a29k.sh: Delete.
* emulparams/ebmon29k.sh: Delete.
* emulparams/sa29200.sh: Delete.
* Makefile.am: Remove a29k support.
* configure.tgt: Likewise.
* ld.texinfo: Likewise.

5
ld/emulparams/a29k.sh
View file

@ -1,5 +0,0 @@
SCRIPT_NAME=a29k
OUTPUT_FORMAT="coff-a29k-big"
TEXT_START_ADDR=0x1000000
TARGET_PAGE_SIZE=0x1000000
ARCH=a29k

5
ld/emulparams/ebmon29k.sh
View file

@ -1,5 +0,0 @@
SCRIPT_NAME=ebmon29k
OUTPUT_FORMAT="coff-a29k-big"
TEXT_START_ADDR=0x8000
TARGET_PAGE_SIZE=0x1000
ARCH=a29k

5
ld/emulparams/sa29200.sh
View file

@ -1,5 +0,0 @@
SCRIPT_NAME=sa29200
OUTPUT_FORMAT="coff-a29k-big"
TEXT_START_ADDR=0x40004000
TARGET_PAGE_SIZE=0x1000
ARCH=a29k

1
opcodes/ChangeLog
View file

@ -1,5 +1,6 @@
2005-08-18 Alan Modra <amodra@bigpond.net.au>
* a29k-dis.c: Delete.
* Makefile.am: Remove a29k support.
* configure.in: Likewise.
* disassemble.c: Likewise.

358
opcodes/a29k-dis.c
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@ -1,358 +0,0 @@
/* Instruction printing code for the AMD 29000
Copyright 1990, 1993, 1994, 1995, 1998, 2000, 2001, 2002
Free Software Foundation, Inc.
Contributed by Cygnus Support. Written by Jim Kingdon.
This file is part of GDB and GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/a29k.h"
/* Print a symbolic representation of a general-purpose
register number NUM on STREAM.
NUM is a number as found in the instruction, not as found in
debugging symbols; it must be in the range 0-255. */
static void
print_general (int num, struct disassemble_info *info)
{
if (num < 128)
(*info->fprintf_func) (info->stream, "gr%d", num);
else
(*info->fprintf_func) (info->stream, "lr%d", num - 128);
}
/* Like print_general but a special-purpose register.
The mnemonics used by the AMD assembler are not quite the same
as the ones in the User's Manual. We use the ones that the
assembler uses. */
static void
print_special (unsigned int num, struct disassemble_info *info)
{
/* Register names of registers 0-SPEC0_NUM-1. */
static char *spec0_names[] =
{
"vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
"pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1",
"spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc",
"cir", "cdr"
};
#define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0]))
/* Register names of registers 128-128+SPEC128_NUM-1. */
static char *spec128_names[] =
{
"ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
};
#define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0]))
/* Register names of registers 160-160+SPEC160_NUM-1. */
static char *spec160_names[] =
{
"fpe", "inte", "fps", "sr163", "exop"
};
#define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0]))
if (num < SPEC0_NUM)
(*info->fprintf_func) (info->stream, spec0_names[num]);
else if (num >= 128 && num < 128 + SPEC128_NUM)
(*info->fprintf_func) (info->stream, spec128_names[num-128]);
else if (num >= 160 && num < 160 + SPEC160_NUM)
(*info->fprintf_func) (info->stream, spec160_names[num-160]);
else
(*info->fprintf_func) (info->stream, "sr%d", num);
}
/* Is an instruction with OPCODE a delayed branch? */
static int
is_delayed_branch (int opcode)
{
return (opcode == 0xa8 || opcode == 0xa9 || opcode == 0xa0 || opcode == 0xa1
|| opcode == 0xa4 || opcode == 0xa5
|| opcode == 0xb4 || opcode == 0xb5
|| opcode == 0xc4 || opcode == 0xc0
|| opcode == 0xac || opcode == 0xad
|| opcode == 0xcc);
}
/* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}. */
static void
find_bytes_big (char *insn,
unsigned char *insn0,
unsigned char *insn8,
unsigned char *insn16,
unsigned char *insn24)
{
*insn24 = insn[0];
*insn16 = insn[1];
*insn8 = insn[2];
*insn0 = insn[3];
}
static void
find_bytes_little (char *insn,
unsigned char *insn0,
unsigned char *insn8,
unsigned char *insn16,
unsigned char *insn24)
{
*insn24 = insn[3];
*insn16 = insn[2];
*insn8 = insn[1];
*insn0 = insn[0];
}
typedef void (*find_byte_func_type)
(char *, unsigned char *, unsigned char *,
unsigned char *, unsigned char *);
/* Print one instruction from MEMADDR on INFO->STREAM.
Return the size of the instruction (always 4 on a29k). */
static int
print_insn (bfd_vma memaddr, struct disassemble_info *info)
{
/* The raw instruction. */
char insn[4];
/* The four bytes of the instruction. */
unsigned char insn24, insn16, insn8, insn0;
find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data;
struct a29k_opcode const * opcode;
{
int status =
(*info->read_memory_func) (memaddr, (bfd_byte *) &insn[0], 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
}
(*find_byte_func) (insn, &insn0, &insn8, &insn16, &insn24);
printf ("%02x%02x%02x%02x ", insn24, insn16, insn8, insn0);
/* Handle the nop (aseq 0x40,gr1,gr1) specially. */
if ( (insn24 == 0x70)
&& (insn16 == 0x40)
&& (insn8 == 0x01)
&& (insn0 == 0x01))
{
(*info->fprintf_func) (info->stream,"nop");
return 4;
}
/* The opcode is always in insn24. */
for (opcode = &a29k_opcodes[0];
opcode < &a29k_opcodes[num_opcodes];
++opcode)
{
if (((unsigned long) insn24 << 24) == opcode->opcode)
{
char *s;
(*info->fprintf_func) (info->stream, "%s ", opcode->name);
for (s = opcode->args; *s != '\0'; ++s)
{
switch (*s)
{
case 'a':
print_general (insn8, info);
break;
case 'b':
print_general (insn0, info);
break;
case 'c':
print_general (insn16, info);
break;
case 'i':
(*info->fprintf_func) (info->stream, "%d", insn0);
break;
case 'x':
(*info->fprintf_func) (info->stream, "0x%x",
(insn16 << 8) + insn0);
break;
case 'h':
/* This used to be %x for binutils. */
(*info->fprintf_func) (info->stream, "0x%x",
(insn16 << 24) + (insn0 << 16));
break;
case 'X':
(*info->fprintf_func) (info->stream, "%d",
((insn16 << 8) + insn0) | 0xffff0000);
break;
case 'P':
/* This output looks just like absolute addressing, but
maybe that's OK (it's what the GDB m68k and EBMON
a29k disassemblers do). */
/* All the shifting is to sign-extend it. p*/
(*info->print_address_func)
(memaddr +
(((int)((insn16 << 10) + (insn0 << 2)) << 14) >> 14),
info);
break;
case 'A':
(*info->print_address_func)
((insn16 << 10) + (insn0 << 2), info);
break;
case 'e':
(*info->fprintf_func) (info->stream, "%d", insn16 >> 7);
break;
case 'n':
(*info->fprintf_func) (info->stream, "0x%x", insn16 & 0x7f);
break;
case 'v':
(*info->fprintf_func) (info->stream, "0x%x", insn16);
break;
case 's':
print_special (insn8, info);
break;
case 'u':
(*info->fprintf_func) (info->stream, "%d", insn0 >> 7);
break;
case 'r':
(*info->fprintf_func) (info->stream, "%d", (insn0 >> 4) & 7);
break;
case 'I':
if ((insn16 & 3) != 0)
(*info->fprintf_func) (info->stream, "%d", insn16 & 3);
break;
case 'd':
(*info->fprintf_func) (info->stream, "%d", (insn0 >> 2) & 3);
break;
case 'f':
(*info->fprintf_func) (info->stream, "%d", insn0 & 3);
break;
case 'F':
(*info->fprintf_func) (info->stream, "%d",
(insn16 >> 2) & 15);
break;
case 'C':
(*info->fprintf_func) (info->stream, "%d", insn16 & 3);
break;
default:
(*info->fprintf_func) (info->stream, "%c", *s);
}
}
/* Now we look for a const,consth pair of instructions,
in which case we try to print the symbolic address. */
if (insn24 == 2) /* consth */
{
int errcode;
char prev_insn[4];
unsigned char prev_insn0, prev_insn8, prev_insn16, prev_insn24;
errcode = (*info->read_memory_func) (memaddr - 4,
(bfd_byte *) &prev_insn[0],
4,
info);
if (errcode == 0)
{
/* If it is a delayed branch, we need to look at the
instruction before the delayed brach to handle
things like
const _foo
call _printf
consth _foo
*/
(*find_byte_func) (prev_insn, & prev_insn0, & prev_insn8,
& prev_insn16, & prev_insn24);
if (is_delayed_branch (prev_insn24))
{
errcode = (*info->read_memory_func)
(memaddr - 8, (bfd_byte *) & prev_insn[0], 4, info);
(*find_byte_func) (prev_insn, & prev_insn0, & prev_insn8,
& prev_insn16, & prev_insn24);
}
}
/* If there was a problem reading memory, then assume
the previous instruction was not const. */
if (errcode == 0)
{
/* Is it const to the same register? */
if (prev_insn24 == 3
&& prev_insn8 == insn8)
{
(*info->fprintf_func) (info->stream, "\t; ");
(*info->print_address_func)
(((insn16 << 24) + (insn0 << 16)
+ (prev_insn16 << 8) + (prev_insn0)),
info);
}
}
}
return 4;
}
}
/* This used to be %8x for binutils. */
(*info->fprintf_func)
(info->stream, ".word 0x%08x",
(insn24 << 24) + (insn16 << 16) + (insn8 << 8) + insn0);
return 4;
}
/* Disassemble an big-endian a29k instruction. */
int
print_insn_big_a29k (bfd_vma memaddr, struct disassemble_info *info)
{
info->private_data = (PTR) find_bytes_big;
return print_insn (memaddr, info);
}
/* Disassemble a little-endian a29k instruction. */
int
print_insn_little_a29k (bfd_vma memaddr, struct disassemble_info *info)
{
info->private_data = (PTR) find_bytes_little;
return print_insn (memaddr, info);
}