* interp.c (sim_fetch_register): Convert internal r5900 regs to
target byte order
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2 changed files with 10 additions and 1 deletions
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@ -1,3 +1,10 @@
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start-sanitize-r5900
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Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_fetch_register): Convert internal r5900 regs to
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target byte order
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end-sanitize-r5900
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Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
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Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
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* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
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* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
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@ -35,11 +42,13 @@ Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
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function check_op_hilo_hi1lo1 with the pair
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function check_op_hilo_hi1lo1 with the pair
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check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
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check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
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start-sanitize-r5900
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Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
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Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
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* tx.igen (madd,maddu): Replace calls to check_op_hilo
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* tx.igen (madd,maddu): Replace calls to check_op_hilo
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with calls to check_div_hilo.
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with calls to check_div_hilo.
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end-sanitize-r5900
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Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
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Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
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* mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
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* mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
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@ -1017,7 +1017,7 @@ sim_fetch_register (sd,rn,memory,length)
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/* start-sanitize-r5900 */
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/* start-sanitize-r5900 */
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if (rn >= 90 && rn < 90 + 32)
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if (rn >= 90 && rn < 90 + 32)
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{
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{
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*(unsigned64*)memory = GPR1[rn - 90];
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*((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
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return 8;
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return 8;
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}
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}
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switch (rn)
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switch (rn)
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