From 823d25713dd1d6aedc605e3da2007b54da9dff2d Mon Sep 17 00:00:00 2001 From: Terry Guo Date: Tue, 24 Mar 2015 14:08:08 +0800 Subject: [PATCH] Extend arm_feature_set struct to provide more bits gas/ChangeLog: 2015-03-24 Terry Guo * config/tc-arm.c (no_cpu_selected): Use new macro to compare features. (parse_psr): Likewise. (do_t_mrs): Likewise. (do_t_msr): Likewise. (static const arm_feature_set arm_ext_*): Defined with new macros. (static const arm_feature_set arm_cext_*): Likewise. (static const arm_feature_set fpu_fpa_ext_*): Likewise. (static const arm_feature_set fpu_vfp_ext_*): Likewise. (deprecated_coproc_regs): Likewise. (UL_BARRIER): Likewise. (barrier_opt_names): Likewise. (arm_cpus): Likewise. (arm_extensions): Likewise. include/opcode/ChangeLog: 2015-03-24 Terry Guo * arm.h (arm_feature_set): Extended to provide more available * bits. (ARM_ANY): Updated to follow above new definition. (ARM_CPU_HAS_FEATURE): Likewise. (ARM_CPU_IS_ANY): Likewise. (ARM_MERGE_FEATURE_SETS): Likewise. (ARM_CLEAR_FEATURE): Likewise. (ARM_FEATURE): Likewise. (ARM_FEATURE_COPY): New macro. (ARM_FEATURE_EQUAL): Likewise. (ARM_FEATURE_ZERO): Likewise. (ARM_FEATURE_CORE_EQUAL): Likewise. (ARM_FEATURE_LOW): Likewise. (ARM_FEATURE_CORE_LOW): Likewise. (ARM_FEATURE_CORE_COPROC): Likewise. opcodes/ChangeLog: 2015-03-24 Terry Guo * arm-dis.c (opcode32): Updated to use new arm feature struct. (opcode16): Likewise. (coprocessor_opcodes): Replace bit with feature struct. (neon_opcodes): Likewise. (arm_opcodes): Likewise. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise. (print_insn_coprocessor): Likewise. (print_insn_arm): Likewise. (select_arm_features): Follow new feature struct. --- gas/ChangeLog | 17 + gas/config/tc-arm.c | 228 +-- include/opcode/ChangeLog | 17 + include/opcode/arm.h | 202 +- opcodes/ChangeLog | 13 + opcodes/arm-dis.c | 3756 +++++++++++++++++++++++++------------- 6 files changed, 2782 insertions(+), 1451 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 0a7f46ff9c..6579c2ffef 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,20 @@ +2015-03-24 Terry Guo + + * config/tc-arm.c (no_cpu_selected): Use new macro to compare + features. + (parse_psr): Likewise. + (do_t_mrs): Likewise. + (do_t_msr): Likewise. + (static const arm_feature_set arm_ext_*): Defined with new macros. + (static const arm_feature_set arm_cext_*): Likewise. + (static const arm_feature_set fpu_fpa_ext_*): Likewise. + (static const arm_feature_set fpu_vfp_ext_*): Likewise. + (deprecated_coproc_regs): Likewise. + (UL_BARRIER): Likewise. + (barrier_opt_names): Likewise. + (arm_cpus): Likewise. + (arm_extensions): Likewise. + 2015-03-20 H.J. Lu * config/tc-i386.c (i386_align_code): Limit multi-byte nop diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index e97036a422..eeead8ae40 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -168,82 +168,96 @@ static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; static const arm_feature_set cpu_default = CPU_DEFAULT; #endif -static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); -static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); -static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); -static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); -static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); -static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); -static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); -static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); +static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); +static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); +static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S); +static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3); +static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M); +static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4); +static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T); +static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5); static const arm_feature_set arm_ext_v4t_5 = - ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); -static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); -static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); -static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); -static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); -static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); -static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); -static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); -static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); -static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); -static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); -static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); -static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); -static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); -static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); -static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); -static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); -static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); -static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0); + ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5); +static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T); +static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E); +static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP); +static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J); +static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); +static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); +static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); +static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M); +static const arm_feature_set arm_ext_v6_notm = + ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); +static const arm_feature_set arm_ext_v6_dsp = + ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP); +static const arm_feature_set arm_ext_barrier = + ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER); +static const arm_feature_set arm_ext_msr = + ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR); +static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV); +static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7); +static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A); +static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R); +static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); +static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8); static const arm_feature_set arm_ext_m = - ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); -static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); -static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); -static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); -static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); -static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); + ARM_FEATURE_CORE_LOW (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M); +static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP); +static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC); +static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS); +static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV); +static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT); static const arm_feature_set arm_arch_any = ARM_ANY; -static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); +static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1, -1); static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; static const arm_feature_set arm_cext_iwmmxt2 = - ARM_FEATURE (0, ARM_CEXT_IWMMXT2); + ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2); static const arm_feature_set arm_cext_iwmmxt = - ARM_FEATURE (0, ARM_CEXT_IWMMXT); + ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT); static const arm_feature_set arm_cext_xscale = - ARM_FEATURE (0, ARM_CEXT_XSCALE); + ARM_FEATURE_COPROC (ARM_CEXT_XSCALE); static const arm_feature_set arm_cext_maverick = - ARM_FEATURE (0, ARM_CEXT_MAVERICK); -static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); -static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); + ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK); +static const arm_feature_set fpu_fpa_ext_v1 = + ARM_FEATURE_COPROC (FPU_FPA_EXT_V1); +static const arm_feature_set fpu_fpa_ext_v2 = + ARM_FEATURE_COPROC (FPU_FPA_EXT_V2); static const arm_feature_set fpu_vfp_ext_v1xd = - ARM_FEATURE (0, FPU_VFP_EXT_V1xD); -static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); -static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); -static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); -static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); + ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD); +static const arm_feature_set fpu_vfp_ext_v1 = + ARM_FEATURE_COPROC (FPU_VFP_EXT_V1); +static const arm_feature_set fpu_vfp_ext_v2 = + ARM_FEATURE_COPROC (FPU_VFP_EXT_V2); +static const arm_feature_set fpu_vfp_ext_v3xd = + ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD); +static const arm_feature_set fpu_vfp_ext_v3 = + ARM_FEATURE_COPROC (FPU_VFP_EXT_V3); static const arm_feature_set fpu_vfp_ext_d32 = - ARM_FEATURE (0, FPU_VFP_EXT_D32); -static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); + ARM_FEATURE_COPROC (FPU_VFP_EXT_D32); +static const arm_feature_set fpu_neon_ext_v1 = + ARM_FEATURE_COPROC (FPU_NEON_EXT_V1); static const arm_feature_set fpu_vfp_v3_or_neon_ext = - ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); -static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); -static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); -static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); + ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); +static const arm_feature_set fpu_vfp_fp16 = + ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16); +static const arm_feature_set fpu_neon_ext_fma = + ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA); +static const arm_feature_set fpu_vfp_ext_fma = + ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA); static const arm_feature_set fpu_vfp_ext_armv8 = - ARM_FEATURE (0, FPU_VFP_EXT_ARMV8); + ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8); static const arm_feature_set fpu_vfp_ext_armv8xd = - ARM_FEATURE (0, FPU_VFP_EXT_ARMV8xD); + ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD); static const arm_feature_set fpu_neon_ext_armv8 = - ARM_FEATURE (0, FPU_NEON_EXT_ARMV8); + ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8); static const arm_feature_set fpu_crypto_ext_armv8 = - ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8); + ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8); static const arm_feature_set crc_ext_armv8 = - ARM_FEATURE (0, CRC_EXT_ARMV8); + ARM_FEATURE_COPROC (CRC_EXT_ARMV8); static int mfloat_abi_opt = -1; /* Record user cpu selection for object attributes. */ @@ -257,8 +271,7 @@ extern FLONUM_TYPE generic_floating_point_number; static bfd_boolean no_cpu_selected (void) { - return selected_cpu.core == arm_arch_none.core - && selected_cpu.coproc == arm_arch_none.coproc; + return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none); } #ifdef OBJ_ELF @@ -5769,7 +5782,7 @@ parse_psr (char **str, bfd_boolean lhs) /* PR gas/12698: If the user has specified -march=all then m_profile will be TRUE, but we want to ignore it in this case as we are building for any CPU type, including non-m variants. */ - if (selected_cpu.core == arm_arch_any.core) + if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any)) m_profile = FALSE; /* CPSR's and SPSR's can now be lowercase. This is just a convenience @@ -8331,19 +8344,19 @@ struct deprecated_coproc_regs_s static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = { {15, 0, 7, 10, 5, /* CP15DMB. */ - ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, DEPR_ACCESS_V8, NULL}, {15, 0, 7, 10, 4, /* CP15DSB. */ - ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, DEPR_ACCESS_V8, NULL}, {15, 0, 7, 5, 4, /* CP15ISB. */ - ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, DEPR_ACCESS_V8, NULL}, {14, 6, 1, 0, 0, /* TEEHBR. */ - ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, DEPR_ACCESS_V8, NULL}, {14, 6, 0, 0, 0, /* TEECR. */ - ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, DEPR_ACCESS_V8, NULL}, }; @@ -11920,7 +11933,8 @@ do_t_mrs (void) /* PR gas/12698: The constraint is only applied for m_profile. If the user has specified -march=all, we want to ignore it as we are building for any CPU type, including non-m variants. */ - bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; + bfd_boolean m_profile = + !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); constraint ((flags != 0) && m_profile, _("selected processor does " "not support requested special purpose register")); } @@ -11960,7 +11974,8 @@ do_t_msr (void) /* PR gas/12698: The constraint is only applied for m_profile. If the user has specified -march=all, we want to ignore it as we are building for any CPU type, including non-m variants. */ - bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; + bfd_boolean m_profile = + !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) && (bits & ~(PSR_s | PSR_f)) != 0) || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) @@ -18207,8 +18222,8 @@ static const struct asm_cond conds[] = }; #define UL_BARRIER(L,U,CODE,FEAT) \ - { L, CODE, ARM_FEATURE (FEAT, 0) }, \ - { U, CODE, ARM_FEATURE (FEAT, 0) } + { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \ + { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) } static struct asm_barrier_opt barrier_opt_names[] = { @@ -24433,11 +24448,11 @@ static const struct arm_cpu_option_table arm_cpus[] = ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, "Cortex-A7"), ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, - ARM_FEATURE (0, FPU_VFP_V3 + ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1), "Cortex-A8"), ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, - ARM_FEATURE (0, FPU_VFP_V3 + ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1), "Cortex-A9"), ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, @@ -24473,13 +24488,14 @@ static const struct arm_cpu_option_table arm_cpus[] = ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), /* Maverick */ - ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), + ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"), /* Marvell processors. */ - ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0), + ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP + | ARM_EXT_SEC), FPU_ARCH_VFP_V3D16, NULL), - ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP - | ARM_EXT_SEC, 0), + ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP + | ARM_EXT_SEC), FPU_ARCH_NEON_VFP_V4, NULL), /* APM X-Gene family. */ ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, @@ -24566,40 +24582,40 @@ struct arm_option_extension_value_table #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA } static const struct arm_option_extension_value_table arm_extensions[] = { - ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (0, CRC_EXT_ARMV8), - ARM_FEATURE (ARM_EXT_V8, 0)), + ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, - ARM_FEATURE (0, FPU_CRYPTO_ARMV8), - ARM_FEATURE (ARM_EXT_V8, 0)), - ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE (0, FPU_VFP_ARMV8), - ARM_FEATURE (ARM_EXT_V8, 0)), - ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), - ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), - ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), - ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), - ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY), - ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), - ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY), - ARM_EXT_OPT ("maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), - ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY), - ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0), - ARM_FEATURE (ARM_EXT_MP, 0), - ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), + ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), + ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), + ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), + ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), + ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)), + ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), + ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ANY), + ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), + ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ANY), + ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ANY), + ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP), + ARM_FEATURE_CORE_LOW (ARM_EXT_MP), + ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)), ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, - ARM_FEATURE(0, FPU_NEON_ARMV8), - ARM_FEATURE (ARM_EXT_V8, 0)), - ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0), - ARM_FEATURE (ARM_EXT_OS, 0), - ARM_FEATURE (ARM_EXT_V6M, 0)), - ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0), - ARM_FEATURE (ARM_EXT_SEC, 0), - ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)), - ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV - | ARM_EXT_DIV, 0), - ARM_FEATURE (ARM_EXT_VIRT, 0), - ARM_FEATURE (ARM_EXT_V7A, 0)), - ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), - ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY), + ARM_FEATURE_COPROC (FPU_NEON_ARMV8), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), + ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS), + ARM_FEATURE_CORE_LOW (ARM_EXT_OS), + ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)), + ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), + ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), + ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V7A)), + ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV + | ARM_EXT_DIV), + ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), + ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), + ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ANY), { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE } }; #undef ARM_EXT_OPT diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 36bc33521f..4a0534f283 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,20 @@ +2015-03-24 Terry Guo + + * arm.h (arm_feature_set): Extended to provide more available bits. + (ARM_ANY): Updated to follow above new definition. + (ARM_CPU_HAS_FEATURE): Likewise. + (ARM_CPU_IS_ANY): Likewise. + (ARM_MERGE_FEATURE_SETS): Likewise. + (ARM_CLEAR_FEATURE): Likewise. + (ARM_FEATURE): Likewise. + (ARM_FEATURE_COPY): New macro. + (ARM_FEATURE_EQUAL): Likewise. + (ARM_FEATURE_ZERO): Likewise. + (ARM_FEATURE_CORE_EQUAL): Likewise. + (ARM_FEATURE_LOW): Likewise. + (ARM_FEATURE_CORE_LOW): Likewise. + (ARM_FEATURE_CORE_COPROC): Likewise. + 2015-02-19 Pedro Alves * cgen.h [__cplusplus]: Wrap in extern "C". diff --git a/include/opcode/arm.h b/include/opcode/arm.h index cd1953c6c5..1bf6b3cb55 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -139,11 +139,12 @@ | ARM_EXT_VIRT | ARM_EXT_V8) /* Processors with specific extensions in the co-processor space. */ -#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) +#define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) #define ARM_ARCH_IWMMXT \ - ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) + ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) #define ARM_ARCH_IWMMXT2 \ - ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) + ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \ + | ARM_CEXT_IWMMXT2) #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) @@ -165,128 +166,159 @@ #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) /* Deprecated. */ -#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) +#define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) -#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) -#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) +#define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1) +#define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA) -#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) -#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) -#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) -#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16) +#define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD) +#define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1) +#define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2) +#define FPU_ARCH_VFP_V3D16 ARM_FEATURE_COPROC (FPU_VFP_V3D16) #define FPU_ARCH_VFP_V3D16_FP16 \ - ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) -#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) -#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16) -#define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD) -#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16) -#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) + ARM_FEATURE_COPROC (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) +#define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3) +#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_VFP_EXT_FP16) +#define FPU_ARCH_VFP_V3xD ARM_FEATURE_COPROC (FPU_VFP_V3xD) +#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \ + | FPU_VFP_EXT_FP16) +#define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1) #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ - ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) + ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1) #define FPU_ARCH_NEON_FP16 \ - ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) -#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) -#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4) -#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16) -#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) -#define FPU_ARCH_VFP_V5D16 ARM_FEATURE(0, FPU_VFP_V5D16) -#define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE(0, FPU_VFP_V5_SP_D16) + ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) +#define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD) +#define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4) +#define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16) +#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16) +#define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16) +#define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16) #define FPU_ARCH_NEON_VFP_V4 \ - ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) -#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8) -#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8) + ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) +#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8) +#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ + | FPU_VFP_ARMV8) #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ - ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) -#define ARCH_CRC_ARMV8 ARM_FEATURE(0, CRC_EXT_ARMV8) + ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) +#define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8) -#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) +#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) -#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) +#define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK) -#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) -#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) -#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) -#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) -#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) -#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) -#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) -#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) -#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) -#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) -#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) -#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) -#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) -#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) -#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) -#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) -#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) -#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) -#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) -#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) -#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) -#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) -#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) -#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) -#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0) -#define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0) -#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) -#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) -#define ARM_ARCH_V7VE ARM_FEATURE (ARM_AEXT_V7VE, 0) -#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) -#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) -#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) -#define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0) +#define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1) +#define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2) +#define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S) +#define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3) +#define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M) +#define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM) +#define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4) +#define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM) +#define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T) +#define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM) +#define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5) +#define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM) +#define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T) +#define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP) +#define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE) +#define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ) +#define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6) +#define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K) +#define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z) +#define ARM_ARCH_V6ZK ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZK) +#define ARM_ARCH_V6T2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6T2) +#define ARM_ARCH_V6KT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KT2) +#define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZT2) +#define ARM_ARCH_V6ZKT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZKT2) +#define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M) +#define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM) +#define ARM_ARCH_V7 ARM_FEATURE_CORE_LOW (ARM_AEXT_V7) +#define ARM_ARCH_V7A ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A) +#define ARM_ARCH_V7VE ARM_FEATURE_CORE_LOW (ARM_AEXT_V7VE) +#define ARM_ARCH_V7R ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R) +#define ARM_ARCH_V7M ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M) +#define ARM_ARCH_V7EM ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM) +#define ARM_ARCH_V8A ARM_FEATURE_CORE_LOW (ARM_AEXT_V8A) /* Some useful combinations: */ -#define ARM_ARCH_NONE ARM_FEATURE (0, 0) -#define FPU_NONE ARM_FEATURE (0, 0) -#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ -#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) -#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) +#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) +#define FPU_NONE ARM_FEATURE_LOW (0, 0) +#define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */ +#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) +#define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 | ARM_EXT_V7 \ + | ARM_EXT_V7A | ARM_EXT_V7R \ + | ARM_EXT_V7M | ARM_EXT_DIV) /* v7-a+sec. */ -#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0) +#define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_SEC) /* v7-a+mp+sec. */ #define ARM_ARCH_V7A_MP_SEC \ - ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \ - 0) + ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC) /* v7-r+idiv. */ -#define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0) +#define ARM_ARCH_V7R_IDIV ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R | ARM_EXT_ADIV) /* Features that are present in v6M and v6S-M but not other v6 cores. */ -#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0) +#define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY) /* v8-a+fp. */ -#define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) +#define ARM_ARCH_V8A_FP ARM_FEATURE_LOW (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) /* v8-a+simd (implies fp). */ -#define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \ +#define ARM_ARCH_V8A_SIMD ARM_FEATURE_LOW (ARM_AEXT_V8A, \ FPU_ARCH_NEON_VFP_ARMV8) /* v8-a+crypto (implies simd+fp). */ -#define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \ +#define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE_LOW (ARM_AEXT_V8A, \ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) /* There are too many feature bits to fit in a single word, so use a - structure. For simplicity we put all core features in one word and - everything else in the other. */ + structure. For simplicity we put all core features in array CORE + and everything else in the other. All the bits in element core[0] + have been occupied, so new feature should use bit in element core[1] + and use macro ARM_FEATURE to initialize the feature set variable. */ typedef struct { - unsigned long core; + unsigned long core[2]; unsigned long coproc; } arm_feature_set; #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ - (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) + (((CPU).core[0] & (FEAT).core[0]) != 0 \ + || ((CPU).core[1] & (FEAT).core[1]) != 0 \ + || ((CPU).coproc & (FEAT).coproc) != 0) #define ARM_CPU_IS_ANY(CPU) \ - ((CPU).core == ((arm_feature_set)ARM_ANY).core) + ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \ + && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1]) #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ do { \ - (TARG).core = (F1).core | (F2).core; \ + (TARG).core[0] = (F1).core[0] | (F2).core[0];\ + (TARG).core[1] = (F1).core[1] | (F2).core[1];\ (TARG).coproc = (F1).coproc | (F2).coproc; \ } while (0) #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ do { \ - (TARG).core = (F1).core &~ (F2).core; \ + (TARG).core[0] = (F1).core[0] &~ (F2).core[0];\ + (TARG).core[1] = (F1).core[1] &~ (F2).core[1];\ (TARG).coproc = (F1).coproc &~ (F2).coproc; \ } while (0) -#define ARM_FEATURE(core, coproc) {(core), (coproc)} +#define ARM_FEATURE_COPY(F1, F2) \ + do { \ + (F1).core[0] = (F2).core[0]; \ + (F1).core[1] = (F2).core[1]; \ + (F1).coproc = (F2).coproc; \ + } while (0) + +#define ARM_FEATURE_EQUAL(T1,T2) \ + ((T1).core[0] == (T2).core[0] \ + && (T1).core[1] == (T2).core[1] \ + && (T1).coproc == (T2).coproc) + +#define ARM_FEATURE_ZERO(T) \ + ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0) + +#define ARM_FEATURE_CORE_EQUAL(T1, T2) \ + ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1]) + +#define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)} +#define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0} +#define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)} +#define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)} diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 374f50e027..b3537edc5c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,16 @@ +2015-03-24 Terry Guo + + * arm-dis.c (opcode32): Updated to use new arm feature struct. + (opcode16): Likewise. + (coprocessor_opcodes): Replace bit with feature struct. + (neon_opcodes): Likewise. + (arm_opcodes): Likewise. + (thumb_opcodes): Likewise. + (thumb32_opcodes): Likewise. + (print_insn_coprocessor): Likewise. + (print_insn_arm): Likewise. + (select_arm_features): Follow new feature struct. + 2015-03-17 Ganesh Gopalasubramanian * i386-dis.c (rm_table): Add clzero. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 994586d8a0..c626bc9f31 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -71,15 +71,15 @@ struct arm_private_data struct opcode32 { - unsigned long arch; /* Architecture defining this insn. */ - unsigned long value; /* If arch == 0 then value is a sentinel. */ + arm_feature_set arch; /* Architecture defining this insn. */ + unsigned long value; /* If arch is 0 then value is a sentinel. */ unsigned long mask; /* Recognise insn if (op & mask) == value. */ const char * assembler; /* How to disassemble this insn. */ }; struct opcode16 { - unsigned long arch; /* Architecture defining this insn. */ + arm_feature_set arch; /* Architecture defining this insn. */ unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ const char *assembler; /* How to disassemble this insn. */ }; @@ -148,382 +148,748 @@ enum opcode_sentinel_enum static const struct opcode32 coprocessor_opcodes[] = { /* XScale instructions. */ - {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, - {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200010, 0x0fff0ff0, + "mia%c\tacc0, %0-3r, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e280010, 0x0fff0ff0, + "miaph%c\tacc0, %0-3r, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, /* Intel Wireless MMX technology instructions. */ - { 0, SENTINEL_IWMMXT_START, 0, "" }, - {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, - {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, - {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, - {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, - {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, - {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, - {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, - {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, - {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, - {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, - {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, - {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, - {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, - {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, - {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, - {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, - {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, - {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, - {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, - {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, - {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, - {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, - {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, - { 0, SENTINEL_IWMMXT_END, 0, "" }, + {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, + {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), + 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e800120, 0x0f800ff0, + "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e8000a0, 0x0f800ff0, + "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_FEATURE_CORE_LOW (0), + SENTINEL_IWMMXT_END, 0, "" }, /* Floating point coprocessor (FPA) instructions. */ - {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, - {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, - {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, - {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, - {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, - {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, - {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, - {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, - {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, - {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), + 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, + {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), + 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, /* Register load/store. */ - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, - {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, - {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, - {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, - {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, - {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, - {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, - {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, - {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, - {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, - {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, - {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, - {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, /* Data transfer between ARM and NEON registers. */ - {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, - {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, - {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, - {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, - {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, - {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, - {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, /* Half-precision conversion instructions. */ - {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, - {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, - {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, - {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), + 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), + 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, /* Floating point coprocessor (VFP) instructions. */ - {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, - {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, - {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, - {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, - {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, - {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, - {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, - {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, - {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, - {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, "}, - {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, - {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, - {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, - {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, - {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, - {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, - {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, - {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, - {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, - {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"}, - {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"}, - {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, - {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, - {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, - {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee00a10, 0x0ff00fff, "vmsr%c\t, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, "}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), + 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), + 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), + 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), + 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), + 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), + 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), + 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), + 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), + 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, /* Cirrus coprocessor instructions. */ - {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, - {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, - {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, - {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, - {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000600, 0x0ff00f10, + "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100600, 0x0ff00f10, + "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200600, 0x0ff00f10, + "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300600, 0x0ff00f10, + "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, /* VFP Fused multiply add instructions. */ - {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, /* FP v5. */ - {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, - {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, - {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, - {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, /* Generic coprocessor instructions. */ - { 0, SENTINEL_GENERIC_START, 0, "" }, - {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, - {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, - {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0x0c500000, 0x0ff00000, + "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0e000000, 0x0f000010, + "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0e10f010, 0x0f10f010, + "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0e100010, 0x0f100010, + "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0e000010, 0x0f100010, + "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, /* V6 coprocessor instructions. */ - {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, - {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xfc500000, 0xfff00000, + "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xfc400000, 0xfff00000, + "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, /* V5 coprocessor instructions. */ - {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfe000000, 0xff000010, + "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfe000010, 0xff100010, + "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfe100010, 0xff100010, + "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0, 0, 0, 0} + {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} }; /* Neon opcode table: This does not encode the top byte -- that is @@ -561,275 +927,568 @@ static const struct opcode32 coprocessor_opcodes[] = static const struct opcode32 neon_opcodes[] = { /* Extract. */ - {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, - {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2b00840, 0xffb00850, + "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2b00000, 0xffb00810, + "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, /* Move data element to all lanes. */ - {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, - {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, - {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, /* Table lookup. */ - {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, - + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, + /* Half-precision conversions. */ - {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, - {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), + 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), + 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, /* NEON fused multiply add instructions. */ - {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), + 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), + 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, /* Two registers, miscellaneous. */ - {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, - {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), + 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), + 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20300, 0xffb30fd0, + "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b30600, 0xffb30e10, + "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, /* Three registers of the same length. */ - {FPU_CRYPTO_EXT_ARMV8, 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, - {FPU_CRYPTO_EXT_ARMV8, 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, - {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, - {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, - {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, - {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), + 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), + 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000b00, 0xff800f10, + "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000b10, 0xff800f10, + "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000b00, 0xff800f10, + "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000000, 0xfe800f10, + "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000010, 0xfe800f10, + "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000100, 0xfe800f10, + "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000200, 0xfe800f10, + "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000210, 0xfe800f10, + "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000300, 0xfe800f10, + "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000310, 0xfe800f10, + "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000400, 0xfe800f10, + "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000410, 0xfe800f10, + "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000500, 0xfe800f10, + "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000510, 0xfe800f10, + "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000600, 0xfe800f10, + "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000610, 0xfe800f10, + "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000700, 0xfe800f10, + "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000710, 0xfe800f10, + "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000910, 0xfe800f10, + "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000a00, 0xfe800f10, + "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000a10, 0xfe800f10, + "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, /* One register and an immediate value. */ - {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, /* Two registers and a shift amount. */ - {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, - {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, - {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, - {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, - {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880950, 0xfeb80fd0, + "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900950, 0xfeb00fd0, + "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00950, 0xfea00fd0, + "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00e10, 0xfea00e90, + "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, /* Three registers of different lengths. */ - {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800400, 0xff800f50, + "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800600, 0xff800f50, + "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800900, 0xff800f50, + "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800b00, 0xff800f50, + "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800d00, 0xff800f50, + "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800400, 0xff800f50, + "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800600, 0xff800f50, + "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800000, 0xfe800f50, + "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800100, 0xfe800f50, + "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800200, 0xfe800f50, + "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800300, 0xfe800f50, + "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800500, 0xfe800f50, + "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800700, 0xfe800f50, + "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800800, 0xfe800f50, + "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800a00, 0xfe800f50, + "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800c00, 0xfe800f50, + "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, /* Two registers and a scalar. */ - {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800240, 0xfe800f50, + "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800640, 0xfe800f50, + "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800a40, 0xfe800f50, + "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, /* Element and structure load/store. */ - {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, - {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, - {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, - {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, - {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, - {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, - {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, - {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, - {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, - {0,0 ,0, 0} + {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} }; /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially @@ -876,403 +1535,728 @@ static const struct opcode32 neon_opcodes[] = static const struct opcode32 arm_opcodes[] = { /* ARM instructions. */ - {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, - {ARM_EXT_V1, 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, - {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, - {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), + 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), + 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), + 0x00800090, 0x0fa000f0, + "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), + 0x00a00090, 0x0fa000f0, + "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, /* V8 instructions. */ - {ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"}, - {ARM_EXT_V8, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, - {ARM_EXT_V8, 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, - {ARM_EXT_V8, 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, - {ARM_EXT_V8, 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, - {ARM_EXT_V8, 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, - {ARM_EXT_V8, 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, - {ARM_EXT_V8, 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, - {ARM_EXT_V8, 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, - {ARM_EXT_V8, 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, - {ARM_EXT_V8, 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x0320f005, 0x0fffffff, "sevl"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, /* CRC32 instructions. */ - {CRC_EXT_ARMV8, 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, - {CRC_EXT_ARMV8, 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, - {CRC_EXT_ARMV8, 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, - {CRC_EXT_ARMV8, 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, - {CRC_EXT_ARMV8, 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, - {CRC_EXT_ARMV8, 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, /* Virtualization Extension instructions. */ - {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"}, - {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, /* Integer Divide Extension instructions. */ - {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), + 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), + 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, /* MP Extension instructions. */ - {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, /* V7 instructions. */ - {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, - {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, - {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"}, - {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"}, - {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"}, - {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"}, - {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, /* ARM V6T2 instructions. */ - {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, - {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, - {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6T2, 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, - {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, - {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, - - {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, - {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, - {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, /* ARM Security extension instructions. */ - {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), + 0x01600070, 0x0ff000f0, "smc%c\t%e"}, /* ARM V6K instructions. */ - {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, - {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, - {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, - {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, - {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, - {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0xf57ff01f, 0xffffffff, "clrex"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, /* ARM V6K NOP hints. */ - {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, - {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"}, - {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"}, - {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, - {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f001, 0x0fffffff, "yield%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f002, 0x0fffffff, "wfe%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f003, 0x0fffffff, "wfi%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f004, 0x0fffffff, "sev%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, /* ARM V6 instructions. */ - {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, - {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, - {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, - {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, - {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, - {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, - {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, - {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, - {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, - {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, - {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, - {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, - {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, - {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, /* V5J instruction. */ - {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), + 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, /* V5 Instructions. */ - {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, - {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, - {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, - {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xe1200070, 0xfff000f0, + "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfa000000, 0xfe000000, "blx\t%B"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, - /* V5E "El Segundo" Instructions. */ - {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, - {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, - {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, - {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, + /* V5E "El Segundo" Instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0xf450f000, 0xfc70f000, "pld\t%a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, - {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, - {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, - {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, /* ARM Instructions. */ - {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, - - {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, - - {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, - {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, - {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, - {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, - {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, - {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, - {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, - {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), + 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), + 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), + 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, - {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, - {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"}, - {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, - {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, - {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, - {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, - {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, - {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, - {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, - {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, - {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, - {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, - {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, - {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, - - {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, - - {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, - {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, - {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, - {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, - {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, - {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, - {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0000, 0x0fff0000, "push%c\t%m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, /* The rest. */ - {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, - {0, 0x00000000, 0x00000000, 0} + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (0), + 0x00000000, 0x00000000, 0} }; /* print_insn_thumb16 recognizes the following format control codes: @@ -1307,125 +2291,151 @@ static const struct opcode16 thumb_opcodes[] = /* Thumb instructions. */ /* ARM V8 instructions. */ - {ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"}, - {ARM_EXT_V8, 0xba80, 0xffc0, "hlt\t%0-5x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, /* ARM V6K no-argument instructions. */ - {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, - {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, - {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"}, - {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"}, - {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"}, - {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, /* ARM V6T2 instructions. */ - {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, - {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, - {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, /* ARM V6. */ - {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, - {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, - {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"}, - {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, /* ARM V5 ISA extends Thumb. */ - {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), + 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ /* This is BLX(2). BLX(1) is a 32-bit instruction. */ - {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), + 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ /* ARM V4T ISA (Thumb v1). */ - {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, /* Format 4. */ - {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, /* format 13 */ - {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, - {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, /* format 5 */ - {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"}, - {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"}, - {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"}, - {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, /* format 14 */ - {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"}, - {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, /* format 2 */ - {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, - {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, - {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, - {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, /* format 8 */ - {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, /* format 7 */ - {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, /* format 1 */ - {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, - {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, - {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, /* format 3 */ - {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, /* format 6 */ - {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=" */ + /* TODO: Disassemble PC relative "LDR rD,=" */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x4800, 0xF800, + "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* format 9 */ - {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, - {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, - {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, - {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, /* format 10 */ - {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, - {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, /* format 11 */ - {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, - {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, /* format 12 */ - {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, - {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, /* format 15 */ - {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, - {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, /* format 17 */ - {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, /* format 16 */ - {ARM_EXT_V4T, 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, - {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, /* format 18 */ - {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, /* The E800 .. FFFF range is unconditionally redirected to the 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs are processed via that table. Thus, we can never encounter a bare "second half of BL/BLX(1)" instruction here. */ - {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, - {0, 0, 0, 0} + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} }; /* Thumb32 opcodes use the same table structure as the ARM opcodes. @@ -1482,246 +2492,455 @@ static const struct opcode16 thumb_opcodes[] = static const struct opcode32 thumb32_opcodes[] = { /* V8 instructions. */ - {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"}, - {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, - {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xf3af8005, 0xffffffff, "sevl%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, /* CRC32 instructions. */ - {CRC_EXT_ARMV8, 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, - {CRC_EXT_ARMV8, 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, - {CRC_EXT_ARMV8, 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, - {CRC_EXT_ARMV8, 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, - {CRC_EXT_ARMV8, 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, - {CRC_EXT_ARMV8, 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, + {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), + 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, /* V7 instructions. */ - {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, - {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, - {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, - {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, - {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, - {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, - {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, - {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), + 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), + 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, /* Virtualization Extension instructions. */ - {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, /* We skip ERET as that is SUBS pc, lr, #0. */ /* MP Extension instructions. */ - {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, /* Security extension instructions. */ - {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, /* Instructions defined in the basic V6T2 set. */ - {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, - {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, - {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"}, - {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, - {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"}, - {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, - {ARM_EXT_V6T2, 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, - {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, - {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, - {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, - {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, - {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, - {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, - {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, - {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, - {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, - {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, - {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, - {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, - {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, - {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, - {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, - {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, - {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, - {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, - {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, - {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, - {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, - {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, - {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, - {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, - {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, - {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, - {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, - {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, - {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, - {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, - {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, - {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, - {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, - {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, - {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, - {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, - {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, - {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3bf8f2f, 0xffffffff, "clrex%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf810f000, 0xff70f000, "pld%c\t%a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb100000, 0xfff000c0, + "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbc00080, 0xfff000c0, + "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9400000, 0xff500000, + "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9500000, 0xff500000, + "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8600000, 0xff700000, + "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8700000, 0xff700000, + "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, /* Filter out Bcc with cond=E or F, which are used for other instructions. */ - {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, - {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, - {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, - {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, /* These have been 32-bit since the invention of Thumb. */ - {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, - {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, /* Fallback. */ - {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, - {0, 0, 0, 0} + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} }; static const char *const arm_conditional[] = @@ -1929,9 +3148,11 @@ print_insn_coprocessor (bfd_vma pc, fprintf_ftype func = info->fprintf_func; unsigned long mask; unsigned long value = 0; - struct arm_private_data *private_data = info->private_data; - unsigned long allowed_arches = private_data->features.coproc; int cond; + struct arm_private_data *private_data = info->private_data; + arm_feature_set allowed_arches = ARM_ARCH_NONE; + + ARM_FEATURE_COPY (allowed_arches, private_data->features); for (insn = coprocessor_opcodes; insn->assembler; insn++) { @@ -1940,7 +3161,7 @@ print_insn_coprocessor (bfd_vma pc, signed long value_in_comment = 0; const char *c; - if (insn->arch == 0) + if (ARM_FEATURE_ZERO (insn->arch)) switch (insn->value) { case SENTINEL_IWMMXT_START: @@ -1949,14 +3170,15 @@ print_insn_coprocessor (bfd_vma pc, && info->mach != bfd_mach_arm_iWMMXt2) do insn++; - while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END); + while ((! ARM_FEATURE_ZERO (insn->arch)) + && insn->value != SENTINEL_IWMMXT_END); continue; case SENTINEL_IWMMXT_END: continue; case SENTINEL_GENERIC_START: - allowed_arches = private_data->features.core; + ARM_FEATURE_COPY (allowed_arches, private_data->features); continue; default: @@ -1993,11 +3215,11 @@ print_insn_coprocessor (bfd_vma pc, cond = COND_UNCOND; } } - + if ((given & mask) != value) continue; - if ((insn->arch & allowed_arches) == 0) + if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) continue; for (c = insn->assembler; *c; c++) @@ -3153,8 +4375,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { if ((given & insn->mask) != insn->value) continue; - - if ((insn->arch & private_data->features.core) == 0) + + if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) continue; /* Special case: an instruction with all bits set in the condition field @@ -3368,10 +4590,14 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'p': if ((given & 0x0000f000) == 0x0000f000) { + arm_feature_set arm_ext_v6 = + ARM_FEATURE_CORE_LOW (ARM_EXT_V6); + /* The p-variants of tst/cmp/cmn/teq are the pre-V6 mechanism for setting PSR flag bits. They are obsolete in V6 onwards. */ - if ((private_data->features.core & ARM_EXT_V6) == 0) + if (! ARM_CPU_HAS_FEATURE (private_data->features, \ + arm_ext_v6)) func (stream, "p"); } break; @@ -4794,12 +6020,20 @@ static void select_arm_features (unsigned long mach, arm_feature_set * features) { -#undef ARM_FEATURE -#define ARM_FEATURE(ARCH,CEXT) \ - features->core = (ARCH); \ +#undef ARM_FEATURE_LOW +#define ARM_FEATURE_LOW(ARCH1,CEXT) \ + features->core[0] = (ARCH1); \ + features->core[1] = 0; \ features->coproc = (CEXT) | FPU_FPA; \ return +#undef ARM_FEATURE_CORE_LOW +#define ARM_FEATURE_CORE_LOW(ARCH1) \ + features->core[0] = (ARCH1); \ + features->core[1] = 0; \ + features->coproc = FPU_FPA; \ + return + switch (mach) { case bfd_mach_arm_2: ARM_ARCH_V2; @@ -4812,12 +6046,14 @@ select_arm_features (unsigned long mach, case bfd_mach_arm_5T: ARM_ARCH_V5T; case bfd_mach_arm_5TE: ARM_ARCH_V5TE; case bfd_mach_arm_XScale: ARM_ARCH_XSCALE; - case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK); + case bfd_mach_arm_ep9312: ARM_FEATURE_LOW (ARM_AEXT_V4T, \ + ARM_CEXT_MAVERICK \ + | FPU_MAVERICK); case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT; case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2; /* If the machine type is unknown allow all architecture types and all extensions. */ - case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL); + case bfd_mach_arm_unknown: ARM_FEATURE_LOW (-1UL, -1UL); default: abort (); }