* ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries.
Move duplicate mnemonic entries together. Use RS instead of RT on all mt*. * ppc-dis.c: Convert to ISO C.
This commit is contained in:
Alan Modra
parent
37b6de1b9d
commit
823bbe9d95
3 changed files with 223 additions and 243 deletions
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@ -1,3 +1,10 @@
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2003-09-02 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries.
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Move duplicate mnemonic entries together. Use RS instead of RT on
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all mt*.
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* ppc-dis.c: Convert to ISO C.
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2003-08-29 Dave Brolley <brolley@redhat.com>
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* Makefile.am (stamp-frv): Copy frv.cpu and frv.opc from
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@ -30,18 +30,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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in both big and little endian mode and also for the POWER (RS/6000)
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chip. */
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static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
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int bigendian, int dialect));
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static int powerpc_dialect PARAMS ((struct disassemble_info *));
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static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
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/* Determine which set of machines to disassemble for. PPC403/601 or
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BookE. For convenience, also disassemble instructions supported
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by the AltiVec vector unit. */
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int
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powerpc_dialect(info)
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struct disassemble_info *info;
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powerpc_dialect (struct disassemble_info *info)
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{
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int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;
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@ -97,9 +93,7 @@ powerpc_dialect(info)
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/* Print a big endian PowerPC instruction. */
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int
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print_insn_big_powerpc (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info));
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}
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@ -107,9 +101,7 @@ print_insn_big_powerpc (memaddr, info)
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/* Print a little endian PowerPC instruction. */
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int
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print_insn_little_powerpc (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info));
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}
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@ -117,9 +109,7 @@ print_insn_little_powerpc (memaddr, info)
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/* Print a POWER (RS/6000) instruction. */
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int
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print_insn_rs6000 (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
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}
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@ -127,11 +117,10 @@ print_insn_rs6000 (memaddr, info)
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/* Print a PowerPC or POWER instruction. */
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static int
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print_insn_powerpc (memaddr, info, bigendian, dialect)
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bfd_vma memaddr;
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struct disassemble_info *info;
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int bigendian;
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int dialect;
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print_insn_powerpc (bfd_vma memaddr,
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struct disassemble_info *info,
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int bigendian,
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int dialect)
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{
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bfd_byte buffer[4];
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int status;
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@ -295,7 +284,7 @@ print_insn_powerpc (memaddr, info, bigendian, dialect)
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}
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void
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print_ppc_disassembler_options (FILE * stream)
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print_ppc_disassembler_options (FILE *stream)
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{
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fprintf (stream, "\n\
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The following PPC specific disassembler options are supported for use with\n\
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@ -2682,186 +2682,186 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
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{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
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{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
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{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
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{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
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{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
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{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
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{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
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{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
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{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
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{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
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{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
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{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
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{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
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{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
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{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
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{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
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{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
|
||||
{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
|
||||
{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
|
||||
{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
|
||||
{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
|
||||
{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
|
||||
{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
|
||||
{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
|
||||
{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
|
||||
{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
|
||||
{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
|
||||
{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
|
||||
{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
|
|
@ -2906,8 +2906,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
|
||||
|
||||
{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
|
||||
{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
|
||||
{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
|
||||
{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
|
||||
|
||||
{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
|
||||
|
||||
|
|
@ -2935,143 +2934,143 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
|
||||
{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
|
||||
{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
|
||||
{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
|
||||
{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
|
||||
{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
|
||||
{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
|
||||
{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
|
||||
{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
|
||||
|
|
@ -3235,6 +3234,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
|
||||
|
||||
{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
|
||||
{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
|
||||
|
||||
{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
|
||||
{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
|
||||
|
|
@ -3357,8 +3357,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
|
||||
|
||||
{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
|
||||
{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
|
||||
{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
|
||||
|
||||
{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
|
||||
|
||||
|
|
@ -3404,8 +3403,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
|
||||
{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
|
||||
|
||||
{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
|
||||
{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
|
||||
{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
|
||||
|
||||
{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
|
||||
{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
|
||||
|
|
@ -3505,8 +3503,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
|
||||
|
||||
{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
|
||||
|
||||
{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
|
||||
{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
|
||||
{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
|
||||
|
|
@ -3585,8 +3581,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
|
||||
{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
|
||||
{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
|
||||
|
||||
{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
|
||||
{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
|
||||
|
|
@ -3600,21 +3595,24 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
|
||||
{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
|
||||
{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
|
||||
{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
|
||||
{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
|
||||
{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
|
||||
{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
|
||||
{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
|
||||
{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
|
||||
{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
|
||||
{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
|
||||
{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
|
||||
{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
|
||||
{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
|
||||
{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
|
||||
|
|
@ -3639,8 +3637,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
|
||||
{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
|
||||
{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
|
||||
{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
|
||||
{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
|
||||
{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
|
||||
|
|
@ -3651,19 +3652,32 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
|
||||
{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
|
||||
|
|
@ -3726,12 +3740,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
|
||||
|
|
@ -3742,26 +3751,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
|
||||
|
|
@ -3801,10 +3799,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
|
||||
|
||||
{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
|
||||
{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
|
||||
{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
|
||||
|
||||
{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
|
||||
|
||||
{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
|
||||
|
|
@ -3856,42 +3850,41 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
|
||||
{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
|
||||
|
||||
{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
|
||||
{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
|
||||
{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
|
||||
|
||||
{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
|
||||
{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
|
||||
|
|
@ -3924,61 +3917,73 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
|
||||
{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
|
||||
{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
|
||||
{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
|
||||
{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
|
||||
{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
|
||||
{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
|
||||
{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
|
||||
{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
|
||||
{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
|
||||
{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
|
||||
{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
|
||||
{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
|
||||
{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
|
||||
{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
|
||||
{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
|
||||
{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
|
||||
{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
|
||||
{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
|
||||
{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
|
||||
{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
|
||||
{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
|
||||
{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
|
||||
{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
|
||||
|
|
@ -4005,61 +4010,45 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
|
||||
{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
|
||||
{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
|
||||
{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
|
||||
{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
|
||||
{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
|
||||
{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
|
||||
|
||||
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
|
||||
|
|
@ -4206,8 +4195,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
|
||||
|
||||
{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
|
||||
{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
|
||||
{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
|
||||
|
||||
{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
|
||||
|
||||
|
|
@ -4251,11 +4239,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
|
||||
{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
|
||||
|
||||
{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
|
||||
{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
|
||||
|
||||
{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
|
||||
{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
|
||||
{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
|
||||
{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
|
||||
{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
|
||||
{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
|
||||
|
||||
|
|
@ -4278,10 +4265,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
|
||||
|
||||
{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
|
||||
|
||||
{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
|
||||
{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
|
||||
|
||||
{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
|
||||
|
|
@ -4294,13 +4280,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
|
||||
|
||||
{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
|
||||
|
||||
{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
|
||||
|
||||
{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
|
||||
{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
|
||||
{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
|
||||
|
||||
{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue