* traps.c: New file. Trap support moved here from sim-if.c.
* Makefile.in (SIM_OBJS): Add traps.o * sim-if.c: Don't include targ-vals.h. (sim_engine_illegal_insn): Moved to traps.c * sim-main.h (SIM_CORE_SIGNAL): Define. (m32r_core_signal): Declare. * devices.c (device_io_read_buffer): Handle cache purging via MCCR register. * m32r-sim.h (M32R_MISC_PROFILE): Move here from sim-main.h. (PROFILE_COUNT_SHORTINSNS,PROFILE_COUNT_LONGINSNS): New macros. (TRAP_SYSCALL,TRAP_BREAKPOINT): New macros.
This commit is contained in:
Doug Evans
parent
a040908c40
commit
7e92721894
5 changed files with 379 additions and 11 deletions
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@ -57,6 +57,7 @@ sem.c
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sim-if.c
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sim-main.h
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tconfig.in
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traps.c
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Things-to-lose:
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@ -1,3 +1,24 @@
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Wed Jun 10 17:39:29 1998 Doug Evans <devans@canuck.cygnus.com>
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* traps.c: New file. Trap support moved here from sim-if.c.
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* Makefile.in (SIM_OBJS): Add traps.o
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* sim-if.c: Don't include targ-vals.h.
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(sim_engine_illegal_insn): Moved to traps.c
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* sim-main.h (SIM_CORE_SIGNAL): Define.
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(m32r_core_signal): Declare.
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* devices.c (device_io_read_buffer): Handle cache purging via MCCR
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register.
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* m32r-sim.h (M32R_MISC_PROFILE): Move here from sim-main.h.
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(PROFILE_COUNT_SHORTINSNS,PROFILE_COUNT_LONGINSNS): New macros.
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(TRAP_SYSCALL,TRAP_BREAKPOINT): New macros.
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* extract.c,sem-switch.c,sem.c: Regenerate.
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start-sanitize-m32rx
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* cpux.h,readx.c,semx.c: Regenerate.
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end-sanitize-m32rx
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Wed May 20 00:10:40 1998 Doug Evans <devans@seba.cygnus.com>
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* m32r-sim.h (PROFILE_COUNT_PARINSNS): New macro.
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@ -32,6 +53,7 @@ start-sanitize-m32rx
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* cpux.c,cpux.h,modelx.c,semx.c: Regenerate.
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* m32rx.c (m32rx_model_mark_{busy,unbusy}_reg): New functions.
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* mloopx.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
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Fix pc value passed to TRACE_INSN for second parallel insn.
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end-sanitize-m32rx
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Thu May 7 02:51:35 1998 Doug Evans <devans@seba.cygnus.com>
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156
sim/m32r/m32r-sim.h
Normal file
156
sim/m32r/m32r-sim.h
Normal file
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@ -0,0 +1,156 @@
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/* collection of junk waiting time to sort out
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef M32R_SIM_H
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#define M32R_SIM_H
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/* Register numbers used in gdb interface. */
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#define PC_REGNUM 21
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#define ACCL_REGNUM 22
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#define ACCH_REGNUM 23
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/* Misc. profile data. */
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typedef struct {
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/* nop insn slot filler count */
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unsigned int fillnop_count;
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/* number of parallel insns */
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unsigned int parallel_count;
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/* number of short insns, not including parallel ones */
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unsigned int short_count;
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/* number of long insns */
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unsigned int long_count;
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} M32R_MISC_PROFILE;
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/* This is invoked by the nop pattern in the .cpu file. */
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#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
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do { \
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if (PROFILE_INSN_P (cpu) \
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&& (addr & 3) != 0) \
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++ CPU_M32R_MISC_PROFILE (cpu).fillnop_count; \
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} while (0)
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/* This is invoked by the execute section of mloop{,x}.in. */
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#define PROFILE_COUNT_PARINSNS(cpu) \
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do { \
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if (PROFILE_INSN_P (cpu)) \
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++ CPU_M32R_MISC_PROFILE (cpu).parallel_count; \
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} while (0)
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/* This is invoked by the execute section of mloop{,x}.in. */
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#define PROFILE_COUNT_SHORTINSNS(cpu) \
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do { \
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if (PROFILE_INSN_P (cpu)) \
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++ CPU_M32R_MISC_PROFILE (cpu).short_count; \
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} while (0)
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/* This is invoked by the execute section of mloop{,x}.in. */
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#define PROFILE_COUNT_LONGINSNS(cpu) \
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do { \
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if (PROFILE_INSN_P (cpu)) \
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++ CPU_M32R_MISC_PROFILE (cpu).long_count; \
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} while (0)
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#define GETTWI GETTSI
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#define SETTWI SETTSI
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/* Additional execution support. */
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/* Result of semantic function is one of
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- next address, branch only
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- NEW_PC_SKIP, sc/snc insn
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- NEW_PC_2, 2 byte non-branch non-sc/snc insn
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- NEW_PC_4, 4 byte non-branch insn
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The special values have bit 1 set so it's cheap to distinguish them. */
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#define NEW_PC_BASE 0xffff0001
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#define NEW_PC_SKIP NEW_PC_BASE
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#define NEW_PC_2 (NEW_PC_BASE + 2)
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#define NEW_PC_4 (NEW_PC_BASE + 4)
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#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
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/* start-sanitize-m32rx */
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/* Modify "next pc" handling to handle parallel execution. */
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#ifdef WANT_CPU_M32RX
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#undef SEM_NEXT_PC
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#define SEM_NEXT_PC(abuf, len) (NEW_PC_BASE + (len))
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#endif
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/* end-sanitize-m32rx */
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/* This macro is emitted by the generator to record branch addresses. */
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#define BRANCH_NEW_PC(var, addr) \
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do { var = (addr); } while (0)
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/* Hardware/device support. */
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/* Exception, Interrupt, and Trap addresses */
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#define EIT_SYSBREAK_ADDR 0x10
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#define EIT_RSVD_INSN_ADDR 0x20
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#define EIT_ADDR_EXCP_ADDR 0x30
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#define EIT_TRAP_BASE_ADDR 0x40
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#define EIT_EXTERN_ADDR 0x80
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#define EIT_RESET_ADDR 0x7ffffff0
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#define EIT_WAKEUP_ADDR 0x7ffffff0
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/* Special purpose traps. */
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#define TRAP_SYSCALL 0
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#define TRAP_BREAKPOINT 1
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/* Support for the MSPR register (Cache Purge Control Register)
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and the MCCR register (Cache Control Register) are needed in order for
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overlays to work correctly with the scache.
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MSPR no longer exists but is supported for upward compatibility with
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early overlay support. */
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/* Cache Purge Control (only exists on early versions of chips) */
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#define MSPR_ADDR 0xfffffff7
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#define MSPR_PURGE 1
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/* Lock Control Register (not supported) */
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#define MLCR_ADDR 0xfffffff7
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#define MLCR_LM 1
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/* Power Management Control Register (not supported) */
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#define MPMR_ADDR 0xfffffffb
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/* Cache Control Register */
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#define MCCR_ADDR 0xffffffff
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#define MCCR_CP 0x80
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/* not supported */
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#define MCCR_CM0 2
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#define MCCR_CM1 1
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/* Serial device addresses. */
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#define UART_INCHAR_ADDR 0xff102013
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#define UART_OUTCHAR_ADDR 0xff10200f
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#define UART_STATUS_ADDR 0xff102006
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#define UART_INPUT_EMPTY 0x4
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#define UART_OUTPUT_EMPTY 0x1
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/* Start address and length of all device support. */
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#define M32R_DEVICE_ADDR 0xff000000
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#define M32R_DEVICE_LEN 0x00ffffff
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/* sim_core_attach device argument. */
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extern device m32r_devices;
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/* FIXME: Temporary, until device support ready. */
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struct _device { int foo; };
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#endif /* M32R_SIM_H */
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@ -10,12 +10,13 @@ typedef struct _sim_cpu SIM_CPU;
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#include "config.h"
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#include "ansidecl.h"
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#include "symcat.h"
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#include "cgen-types.h"
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#include "arch.h"
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#include "sim-basics.h"
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/* These must be defined before sim-base.h. */
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typedef SI sim_cia;
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typedef USI sim_cia;
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#define CIA_GET(cpu) 0 /* FIXME:(CPU_CGEN_HW (cpu)->h_pc) */
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#define CIA_SET(cpu,val) 0 /* FIXME:(CPU_CGEN_HW (cpu)->h_pc = (val)) */
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@ -23,12 +24,20 @@ typedef SI sim_cia;
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#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
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#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA)
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/* Catch address exceptions. */
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#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
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m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
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(TRANSFER), (ERROR))
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#include "sim-base.h"
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#include "cgen-sim.h"
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/*#include "cgen-mem.h"*/
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#include "cgen-trace.h"
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#include "cpu-sim.h"
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/* Function to catch address exceptions. */
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extern SIM_CORE_SIGNAL_FN m32r_core_signal;
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#ifdef WANT_CPU_M32R
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#include "cpu.h"
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#include "decode.h"
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@ -40,12 +49,8 @@ typedef SI sim_cia;
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#endif
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/* end-sanitize-m32rx */
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#include "cpuall.h"
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/* Misc. profile data. */
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typedef struct {
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/* nop insn slot filler count */
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unsigned int fillnop_count;
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} M32R_MISC_PROFILE;
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/* The _sim_cpu struct. */
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struct _sim_cpu {
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sim_cpu_base base;
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@ -53,11 +58,15 @@ struct _sim_cpu {
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/* Static parts of cgen. */
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CGEN_CPU cgen_cpu;
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M32R_MISC_PROFILE m32r_misc_profile;
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#define CPU_M32R_MISC_PROFILE(cpu) ((cpu)->m32r_misc_profile)
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/* CPU specific parts go here.
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Note that in files that don't need to access these pieces WANT_CPU_FOO
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won't be defined and thus these parts won't appear. This is ok.
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One has to of course be careful to not take the size of this
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struct, etc. */
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struct and no structure members accessed in non-cpu specific files can
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go after here. */
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#if defined (WANT_CPU_M32R)
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M32R_CPU_DATA cpu_data;
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/* start-sanitize-m32rx */
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@ -65,10 +74,9 @@ struct _sim_cpu {
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M32RX_CPU_DATA cpu_data;
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/* end-sanitize-m32rx */
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#endif
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M32R_MISC_PROFILE m32r_misc_profile;
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#define CPU_M32R_MISC_PROFILE(cpu) ((cpu)->m32r_misc_profile)
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};
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/* The sim_state struct. */
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struct sim_state {
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sim_cpu *cpu;
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|
@ -78,6 +86,13 @@ struct sim_state {
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|||
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||||
sim_state_base base;
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||||
};
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||||
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||||
/* Misc. */
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||||
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||||
/* Default memory size. */
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||||
#define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */
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||||
|
||||
/* Register access fns. These look up the current mach and call the
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||||
appropriate handler. */
|
||||
SI h_gr_get (SIM_CPU *, UINT);
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||||
void h_gr_set (SIM_CPU *, UINT, SI);
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||||
|
|
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|||
174
sim/m32r/traps.c
Normal file
174
sim/m32r/traps.c
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
/* m32r exception, interrupt, and trap (EIT) support
|
||||
Copyright (C) 1998 Free Software Foundation, Inc.
|
||||
Contributed by Cygnus Solutions.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "targ-vals.h"
|
||||
|
||||
/* The semantic code invokes this for illegal (unrecognized) instructions. */
|
||||
|
||||
void
|
||||
sim_engine_illegal_insn (SIM_CPU *current_cpu, PCADDR cia)
|
||||
{
|
||||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||||
|
||||
#if 0
|
||||
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
|
||||
{
|
||||
h_bsm_set (current_cpu, h_sm_get (current_cpu));
|
||||
h_bie_set (current_cpu, h_ie_get (current_cpu));
|
||||
h_bcond_set (current_cpu, h_cond_get (current_cpu));
|
||||
/* sm not changed */
|
||||
h_ie_set (current_cpu, 0);
|
||||
h_cond_set (current_cpu, 0);
|
||||
|
||||
h_bpc_set (current_cpu, cia);
|
||||
|
||||
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
|
||||
EIT_RSVD_INSN_ADDR);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
|
||||
}
|
||||
|
||||
/* Process an address exception. */
|
||||
|
||||
void
|
||||
m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
|
||||
unsigned int map, int nr_bytes, address_word addr,
|
||||
transfer_type transfer, sim_core_signals sig)
|
||||
{
|
||||
#if 0
|
||||
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
|
||||
{
|
||||
h_bsm_set (current_cpu, h_sm_get (current_cpu));
|
||||
h_bie_set (current_cpu, h_ie_get (current_cpu));
|
||||
h_bcond_set (current_cpu, h_cond_get (current_cpu));
|
||||
/* sm not changed */
|
||||
h_ie_set (current_cpu, 0);
|
||||
h_cond_set (current_cpu, 0);
|
||||
|
||||
h_bpc_set (current_cpu, cia);
|
||||
|
||||
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
|
||||
EIT_ADDR_EXCP_ADDR);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
|
||||
transfer, sig);
|
||||
}
|
||||
|
||||
/* Read/write functions for system call interface. */
|
||||
|
||||
static int
|
||||
syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
|
||||
unsigned long taddr, char *buf, int bytes)
|
||||
{
|
||||
SIM_DESC sd = (SIM_DESC) sc->p1;
|
||||
SIM_CPU *cpu = (SIM_CPU *) sc->p2;
|
||||
|
||||
return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
|
||||
}
|
||||
|
||||
static int
|
||||
syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
|
||||
unsigned long taddr, const char *buf, int bytes)
|
||||
{
|
||||
SIM_DESC sd = (SIM_DESC) sc->p1;
|
||||
SIM_CPU *cpu = (SIM_CPU *) sc->p2;
|
||||
|
||||
return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
|
||||
}
|
||||
|
||||
/* Trap support.
|
||||
The result is the pc address to continue at.
|
||||
Preprocessing like saving the various registers has already been done. */
|
||||
|
||||
USI
|
||||
a_m32r_trap (SIM_CPU *current_cpu, int num)
|
||||
{
|
||||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||||
host_callback *cb = STATE_CALLBACK (sd);
|
||||
|
||||
#ifdef SIM_HAVE_BREAKPOINTS
|
||||
/* Check for breakpoints "owned" by the simulator first, regardless
|
||||
of --environment. */
|
||||
if (num == TRAP_BREAKPOINT)
|
||||
{
|
||||
/* First try sim-break.c. If it's a breakpoint the simulator "owns"
|
||||
it doesn't return. Otherwise it returns and let's us try. */
|
||||
sim_handle_breakpoint (sd, current_cpu, sim_pc_get (current_cpu));
|
||||
/* Fall through. */
|
||||
}
|
||||
#endif
|
||||
|
||||
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
|
||||
{
|
||||
/* The new pc is the trap vector entry.
|
||||
We assume there's a branch there to some handler. */
|
||||
USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
|
||||
return new_pc;
|
||||
}
|
||||
|
||||
switch (num)
|
||||
{
|
||||
case TRAP_SYSCALL :
|
||||
{
|
||||
CB_SYSCALL s;
|
||||
|
||||
CB_SYSCALL_INIT (&s);
|
||||
s.func = h_gr_get (current_cpu, 0);
|
||||
s.arg1 = h_gr_get (current_cpu, 1);
|
||||
s.arg2 = h_gr_get (current_cpu, 2);
|
||||
s.arg3 = h_gr_get (current_cpu, 3);
|
||||
|
||||
if (s.func == TARGET_SYS_exit)
|
||||
{
|
||||
sim_engine_halt (sd, current_cpu, NULL, sim_pc_get (current_cpu),
|
||||
sim_exited, s.arg1);
|
||||
}
|
||||
|
||||
s.p1 = (PTR) sd;
|
||||
s.p2 = (PTR) current_cpu;
|
||||
s.read_mem = syscall_read_mem;
|
||||
s.write_mem = syscall_write_mem;
|
||||
cb_syscall (STATE_CALLBACK (sd), &s);
|
||||
h_gr_set (current_cpu, 2, s.errcode);
|
||||
h_gr_set (current_cpu, 0, s.result);
|
||||
h_gr_set (current_cpu, 1, s.result2);
|
||||
break;
|
||||
}
|
||||
|
||||
case TRAP_BREAKPOINT:
|
||||
sim_engine_halt (sd, current_cpu, NULL, NULL_CIA,
|
||||
sim_stopped, SIM_SIGTRAP);
|
||||
break;
|
||||
|
||||
default :
|
||||
{
|
||||
USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
|
||||
return new_pc;
|
||||
}
|
||||
}
|
||||
|
||||
/* Fake an "rte" insn. */
|
||||
return (sim_pc_get (current_cpu) & -4) + 4;
|
||||
}
|
||||
Loading…
Reference in a new issue