gas/testsuite/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * gas/i386/i386.s: Add tests for fnstsw and fstsw. * gas/i386/inval.s: Likewise. * gas/i386/x86_64.s: Likewise. * gas/i386/intel.s: Use word instead of dword on ss. * gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in and out. * gas/i386/prefix.s: Remove invalid fstsw. * gas/i386/inval.l: Updated. * gas/i386/intelbad.l: Likewise. * gas/i386/i386.d: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. * gas/i386/prefix.d: Updated. gas/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * config/tc-i386.c (_i386_insn): Update comment. (operand_type_match): Also clear unspecified. (operand_type_register_match): Likewise. (parse_operands): Initialize unspecified. (i386_intel_operand): Likewise. (match_template): Check memory and accumulator operand size. (i386_att_operand): Clear unspecified on register operand. (intel_e11): Likewise. (intel_e09): Set operand size and clean unspecified for "XXX PTR". opcodes/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * i386-gen.c (operand_type_init): Add Dword to OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64. (opcode_modifiers): Remove CheckSize, Byte, Word, Dword, Qword and Xmmword. (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte, Xmmword, Unspecified and Anysize. (set_bitfield): Make Mmword an alias of Qword. Make Oword an alias of Xmmword. * i386-opc.h (CheckSize): Removed. (Byte): Updated. (Word): Likewise. (Dword): Likewise. (Qword): Likewise. (Xmmword): Likewise. (FWait): Updated. (OTMax): Likewise. (i386_opcode_modifier): Remove checksize, byte, word, dword, qword and xmmword. (Fword): New. (TBYTE): Likewise. (Unspecified): Likewise. (Anysize): Likewise. (i386_operand_type): Add byte, word, dword, fword, qword, tbyte xmmword, unspecified and anysize. * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword, Tbyte, Xmmword, Unspecified and Anysize. * i386-reg.tbl: Add size for accumulator. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
b17828ca41
commit
7d5e4556a3
22 changed files with 11676 additions and 8511 deletions
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@ -1,3 +1,17 @@
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2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/5534
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* config/tc-i386.c (_i386_insn): Update comment.
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(operand_type_match): Also clear unspecified.
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(operand_type_register_match): Likewise.
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(parse_operands): Initialize unspecified.
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(i386_intel_operand): Likewise.
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(match_template): Check memory and accumulator operand size.
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(i386_att_operand): Clear unspecified on register operand.
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(intel_e11): Likewise.
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(intel_e09): Set operand size and clean unspecified for
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"XXX PTR".
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2008-01-11 Andreas Schwab <schwab@suse.de>
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* read.c (s_space): Declare `repeat' as offsetT.
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@ -113,8 +113,8 @@ struct _i386_insn
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/* TM holds the template for the insn were currently assembling. */
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template tm;
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/* SUFFIX holds the instruction mnemonic suffix if given.
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(e.g. 'l' for 'movl') */
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/* SUFFIX holds the instruction size suffix for byte, word, dword
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or qword, if given. */
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char suffix;
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/* OPERANDS gives the number of given operands. */
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@ -1154,6 +1154,7 @@ operand_type_match (i386_operand_type overlap,
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i386_operand_type temp = overlap;
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temp.bitfield.jumpabsolute = 0;
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temp.bitfield.unspecified = 0;
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if (UINTS_ALL_ZERO (temp))
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return 0;
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@ -1161,7 +1162,7 @@ operand_type_match (i386_operand_type overlap,
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&& given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
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}
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/* If given types r0 and r1 are registers they must be of the same type
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/* If given types g0 and g1 are registers they must be of the same type
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unless the expected operand type register overlap is null.
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Note that Acc in a template matches every size of reg. */
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@ -2642,6 +2643,7 @@ parse_operands (char *l, const char *mnemonic)
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{ /* Yes, we've read in another operand. */
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unsigned int operand_ok;
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this_operand = i.operands++;
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i.types[this_operand].bitfield.unspecified = 1;
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if (i.operands > MAX_OPERANDS)
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{
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as_bad (_("spurious operands; (%d operands/instruction max)"),
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@ -2968,6 +2970,7 @@ match_template (void)
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unsigned int j;
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unsigned int found_cpu_match;
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unsigned int check_register;
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unsigned int size_match;
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#if MAX_OPERANDS != 4
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# error "MAX_OPERANDS must be 4."
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@ -2989,8 +2992,6 @@ match_template (void)
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suffix_check.no_qsuf = 1;
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else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
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suffix_check.no_ldsuf = 1;
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else if (i.suffix == XMMWORD_MNEM_SUFFIX)
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suffix_check.xmmword = 1;
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for (t = current_templates->start; t < current_templates->end; t++)
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{
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@ -3027,21 +3028,52 @@ match_template (void)
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|| (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
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continue;
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/* Check the memory size in Intel mode when it is provided if
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needed. */
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if (intel_syntax
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&& i.suffix
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&& t->opcode_modifier.checksize
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&& (!t->opcode_modifier.byte || !suffix_check.no_bsuf)
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&& (!t->opcode_modifier.word || !suffix_check.no_wsuf)
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&& (!t->opcode_modifier.dword || !suffix_check.no_lsuf)
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&& (!t->opcode_modifier.qword || !suffix_check.no_qsuf)
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&& (!t->opcode_modifier.xmmword || !suffix_check.xmmword))
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continue;
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size_match = 1;
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for (j = 0; j < MAX_OPERANDS; j++)
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{
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operand_types[j] = t->operand_types[j];
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/* Check memory and accumulator operand size. We check
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operand_types for accumulator, and both operand_types
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and i.types for memory. */
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if (j < i.operands
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&& !operand_types[j].bitfield.anysize
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&& ((operand_types[j].bitfield.acc
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&& ((i.types[j].bitfield.byte
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&& !operand_types[j].bitfield.byte)
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|| (i.types[j].bitfield.word
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&& !operand_types[j].bitfield.word)
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|| (i.types[j].bitfield.dword
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&& !operand_types[j].bitfield.dword)
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|| (i.types[j].bitfield.qword
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&& !operand_types[j].bitfield.qword)))
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|| (operand_types[j].bitfield.baseindex
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&& i.types[j].bitfield.baseindex
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&& ((i.types[j].bitfield.unspecified
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&& !operand_types[j].bitfield.unspecified)
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|| (i.types[j].bitfield.byte
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&& !operand_types[j].bitfield.byte)
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|| (i.types[j].bitfield.word
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&& !operand_types[j].bitfield.word)
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|| (i.types[j].bitfield.dword
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&& !operand_types[j].bitfield.dword)
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|| (i.types[j].bitfield.fword
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&& !operand_types[j].bitfield.fword)
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|| (i.types[j].bitfield.qword
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&& !operand_types[j].bitfield.qword)
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|| (i.types[j].bitfield.tbyte
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&& !operand_types[j].bitfield.tbyte)
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|| (i.types[j].bitfield.xmmword
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&& !operand_types[j].bitfield.xmmword)))))
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{
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size_match = 0;
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break;
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}
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}
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if (!size_match)
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continue;
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/* In general, don't allow 64-bit operands in 32-bit mode. */
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if (i.suffix == QWORD_MNEM_SUFFIX
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&& flag_code != CODE_64BIT
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@ -6139,6 +6171,7 @@ i386_att_operand (char *operand_string)
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temp.bitfield.baseindex = 0;
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i.types[this_operand] = operand_type_or (i.types[this_operand],
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temp);
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i.types[this_operand].bitfield.unspecified = 0;
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i.op[this_operand].regs = r;
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i.reg_operands++;
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}
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@ -7854,6 +7887,7 @@ i386_intel_operand (char *operand_string, int got_a_float)
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break;
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intel_parser.op_string = intel_parser.next_operand;
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this_operand = i.operands++;
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i.types[this_operand].bitfield.unspecified = 1;
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}
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free (p);
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@ -8062,7 +8096,10 @@ intel_e09 (void)
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char suffix;
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if (prev_token.code == T_BYTE)
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{
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suffix = BYTE_MNEM_SUFFIX;
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i.types[this_operand].bitfield.byte = 1;
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}
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else if (prev_token.code == T_WORD)
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{
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@ -8074,6 +8111,7 @@ intel_e09 (void)
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suffix = SHORT_MNEM_SUFFIX;
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else
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suffix = WORD_MNEM_SUFFIX;
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i.types[this_operand].bitfield.word = 1;
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}
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else if (prev_token.code == T_DWORD)
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@ -8090,6 +8128,7 @@ intel_e09 (void)
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suffix = SHORT_MNEM_SUFFIX;
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else
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suffix = LONG_MNEM_SUFFIX;
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i.types[this_operand].bitfield.dword = 1;
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}
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else if (prev_token.code == T_FWORD)
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@ -8106,6 +8145,7 @@ intel_e09 (void)
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}
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else
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suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
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i.types[this_operand].bitfield.fword = 1;
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}
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else if (prev_token.code == T_QWORD)
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@ -8114,6 +8154,7 @@ intel_e09 (void)
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suffix = LONG_MNEM_SUFFIX;
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else
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suffix = QWORD_MNEM_SUFFIX;
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i.types[this_operand].bitfield.qword = 1;
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}
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else if (prev_token.code == T_TBYTE)
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@ -8127,6 +8168,7 @@ intel_e09 (void)
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else if (prev_token.code == T_XMMWORD)
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{
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suffix = XMMWORD_MNEM_SUFFIX;
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i.types[this_operand].bitfield.xmmword = 1;
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}
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else
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@ -8135,6 +8177,8 @@ intel_e09 (void)
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return 0;
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}
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i.types[this_operand].bitfield.unspecified = 0;
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/* Operands for jump/call using 'ptr' notation denote absolute
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addresses. */
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if (current_templates->start->opcode_modifier.jump
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@ -8465,6 +8509,7 @@ intel_e11 (void)
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temp.bitfield.baseindex = 0;
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i.types[this_operand] = operand_type_or (i.types[this_operand],
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temp);
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i.types[this_operand].bitfield.unspecified = 0;
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i.op[this_operand].regs = reg;
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i.reg_operands++;
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}
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@ -1,3 +1,24 @@
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2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/5534
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* gas/i386/i386.s: Add tests for fnstsw and fstsw.
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* gas/i386/inval.s: Likewise.
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* gas/i386/x86_64.s: Likewise.
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* gas/i386/intel.s: Use word instead of dword on ss.
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* gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in
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and out.
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* gas/i386/prefix.s: Remove invalid fstsw.
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* gas/i386/inval.l: Updated.
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* gas/i386/intelbad.l: Likewise.
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* gas/i386/i386.d: Likewise.
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* gas/i386/x86_64.d: Likewise.
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* gas/i386/x86-64-inval.l: Likewise.
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* gas/i386/prefix.d: Updated.
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2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/nops.s: Add more tests with opcodes from 0x0f19
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@ -6,6 +6,10 @@
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Disassembly of section .text:
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0+ <.*>:
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[ ]*[a-f0-9]+: df e0 fnstsw %ax
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[ ]*[a-f0-9]+: df e0 fnstsw %ax
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[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
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[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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@ -19,6 +23,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
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[ ]*[a-f0-9]+: df e0 fnstsw %ax
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[ ]*[a-f0-9]+: df e0 fnstsw %ax
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[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
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[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
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@ -1,6 +1,11 @@
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# i386 instructions
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.text
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fnstsw
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fnstsw %ax
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fstsw
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fstsw %ax
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movsx (%eax), %edx
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movsx (%eax), %dx
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movsbl (%eax), %edx
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@ -17,6 +22,11 @@
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movzwl (%eax), %edx
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.intel_syntax noprefix
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fnstsw
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fnstsw ax
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fstsw
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fstsw ax
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movsx edx,BYTE PTR [eax]
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movsx dx,BYTE PTR [eax]
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movsx edx,WORD PTR [eax]
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@ -131,9 +131,9 @@ foo:
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mov 0x90909090[eax], edx
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mov dl, 0x90909090[eax]
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mov edx, 0x90909090[eax]
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mov dword ptr 0x90909090[eax], ss
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mov word ptr 0x90909090[eax], ss
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lea edx, 0x90909090[eax]
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mov ss, dword ptr 0x90909090[eax]
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mov ss, word ptr 0x90909090[eax]
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pop dword ptr 0x90909090[eax]
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xchg eax, eax
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xchg ecx, eax
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@ -3,10 +3,18 @@
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.*:5: Error: .*
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.*:6: Error: .*
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.*:7: Error: .*
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.*:8: Error: .*
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.*:9: Error: .*
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.*:10: Error: .*
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.*:11: Error: .*
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.*:12: Error: .*
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.*:13: Error: .*
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.*:14: Error: .*
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.*:15: Error: .*
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.*:16: Error: .*
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.*:17: Error: .*
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.*:18: Error: .*
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.*:19: Error: .*
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.*:20: Error: .*
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.*:21: Error: .*
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.*:22: Error: .*
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@ -50,7 +58,16 @@
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.*:60: Error: .*
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.*:61: Error: .*
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.*:62: Error: .*
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.*:63: Error: .*
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.*:64: Error: .*
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.*:65: Error: .*
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.*:66: Error: .*
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.*:67: Error: .*
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.*:68: Error: .*
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.*:69: Error: .*
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.*:70: Error: .*
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.*:71: Error: .*
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.*:72: Error: .*
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.*:73: Error: .*
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.*:74: Error: .*
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.*:75: Error: .*
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@ -49,10 +49,10 @@
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.*:50: Error: .*
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.*:51: Error: .*
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.*:52: Error: .*
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.*:53: Error: .*
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.*:54: Error: .*
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.*:55: Error: .*
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.*:56: Error: .*
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.*:57: Error: .*
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.*:58: Error: .*
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.*:59: Error: .*
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.*:60: Error: .*
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.*:61: Error: .*
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@ -61,6 +61,14 @@
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.*:64: Error: .*
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.*:65: Error: .*
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.*:66: Error: .*
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.*:67: Error: .*
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.*:68: Error: .*
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.*:69: Error: .*
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.*:70: Error: .*
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.*:71: Error: .*
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.*:72: Error: .*
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.*:73: Error: .*
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.*:74: Error: .*
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GAS LISTING .*
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@ -116,20 +124,28 @@ GAS LISTING .*
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[ ]*50[ ]+insertq \$4,\$2,%xmm2,%ebx
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[ ]*51[ ]+cvtsi2ssq \(%eax\),%xmm1
|
||||
[ ]*52[ ]+cvtsi2sdq \(%eax\),%xmm1
|
||||
[ ]*53[ ]+
|
||||
[ ]*54[ ]+\.intel_syntax noprefix
|
||||
[ ]*55[ ]+cvtsi2ss xmm1,QWORD PTR \[eax\]
|
||||
[ ]*56[ ]+cvtsi2sd xmm1,QWORD PTR \[eax\]
|
||||
[ ]*57[ ]+cvtsi2ssq xmm1,QWORD PTR \[eax\]
|
||||
[ ]*53[ ]+fnstsw %eax
|
||||
[ ]*54[ ]+fnstsw %al
|
||||
[ ]*55[ ]+fstsw %eax
|
||||
[ ]*56[ ]+fstsw %al
|
||||
[ ]*57[ ]+
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*58[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
|
||||
[ ]*59[ ]+movq xmm1, XMMWORD PTR \[esp\]
|
||||
[ ]*60[ ]+movq xmm1, DWORD PTR \[esp\]
|
||||
[ ]*61[ ]+movq xmm1, WORD PTR \[esp\]
|
||||
[ ]*62[ ]+movq xmm1, BYTE PTR \[esp\]
|
||||
[ ]*63[ ]+movq XMMWORD PTR \[esp\],xmm1
|
||||
[ ]*64[ ]+movq DWORD PTR \[esp\],xmm1
|
||||
[ ]*65[ ]+movq WORD PTR \[esp\],xmm1
|
||||
[ ]*66[ ]+movq BYTE PTR \[esp\],xmm1
|
||||
[ ]*58[ ]+\.intel_syntax noprefix
|
||||
[ ]*59[ ]+cvtsi2ss xmm1,QWORD PTR \[eax\]
|
||||
[ ]*60[ ]+cvtsi2sd xmm1,QWORD PTR \[eax\]
|
||||
[ ]*61[ ]+cvtsi2ssq xmm1,QWORD PTR \[eax\]
|
||||
[ ]*62[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
|
||||
[ ]*63[ ]+movq xmm1, XMMWORD PTR \[esp\]
|
||||
[ ]*64[ ]+movq xmm1, DWORD PTR \[esp\]
|
||||
[ ]*65[ ]+movq xmm1, WORD PTR \[esp\]
|
||||
[ ]*66[ ]+movq xmm1, BYTE PTR \[esp\]
|
||||
[ ]*67[ ]+movq XMMWORD PTR \[esp\],xmm1
|
||||
[ ]*68[ ]+movq DWORD PTR \[esp\],xmm1
|
||||
[ ]*69[ ]+movq WORD PTR \[esp\],xmm1
|
||||
[ ]*70[ ]+movq BYTE PTR \[esp\],xmm1
|
||||
[ ]*71[ ]+fnstsw eax
|
||||
[ ]*72[ ]+fnstsw al
|
||||
[ ]*73[ ]+fstsw eax
|
||||
[ ]*74[ ]+fstsw al
|
||||
|
|
|
|||
|
|
@ -50,6 +50,10 @@ foo: jaw foo
|
|||
insertq $4,$2,%xmm2,%ebx
|
||||
cvtsi2ssq (%eax),%xmm1
|
||||
cvtsi2sdq (%eax),%xmm1
|
||||
fnstsw %eax
|
||||
fnstsw %al
|
||||
fstsw %eax
|
||||
fstsw %al
|
||||
|
||||
.intel_syntax noprefix
|
||||
cvtsi2ss xmm1,QWORD PTR [eax]
|
||||
|
|
@ -64,3 +68,7 @@ foo: jaw foo
|
|||
movq DWORD PTR [esp],xmm1
|
||||
movq WORD PTR [esp],xmm1
|
||||
movq BYTE PTR [esp],xmm1
|
||||
fnstsw eax
|
||||
fnstsw al
|
||||
fstsw eax
|
||||
fstsw al
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@ Disassembly of section .text:
|
|||
0: 9b 26 67 d9 3c [ ]*addr16 fstcw %es:\(%si\)
|
||||
5: 9b df e0 [ ]*fstsw %ax
|
||||
8: 9b df e0 [ ]*fstsw %ax
|
||||
b: 9b df e0 [ ]*fstsw %ax
|
||||
e: 9b 67 df e0 [ ]*addr16 fstsw %ax
|
||||
12: 36 67 66 f3 a7 [ ]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\)
|
||||
b: 9b 67 df e0 [ ]*addr16 fstsw %ax
|
||||
f: 36 67 66 f3 a7 [ ]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\)
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
.text ; foo: addr16 fstcw %es:(%si)
|
||||
fstsw;fstsw %ax;fstsw %eax
|
||||
fstsw; fstsw %ax;
|
||||
addr16 fstsw %ax ;addr16 rep cmpsw %es:(%di),%ss:(%si)
|
||||
|
||||
# Get a good alignment.
|
||||
|
|
|
|||
|
|
@ -49,15 +49,27 @@
|
|||
.*:50: Error: .*
|
||||
.*:51: Error: .*
|
||||
.*:52: Error: .*
|
||||
.*:53: Error: .*
|
||||
.*:54: Error: .*
|
||||
.*:55: Error: .*
|
||||
.*:56: Error: .*
|
||||
.*:57: Error: .*
|
||||
.*:58: Error: .*
|
||||
.*:59: Error: .*
|
||||
.*:60: Error: .*
|
||||
.*:61: Error: .*
|
||||
.*:62: Error: .*
|
||||
.*:63: Error: .*
|
||||
.*:64: Error: .*
|
||||
.*:65: Error: .*
|
||||
.*:66: Error: .*
|
||||
.*:67: Error: .*
|
||||
.*:68: Error: .*
|
||||
.*:69: Error: .*
|
||||
.*:70: Error: .*
|
||||
.*:71: Error: .*
|
||||
.*:72: Error: .*
|
||||
.*:73: Error: .*
|
||||
.*:74: Error: .*
|
||||
.*:75: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
|
|
@ -113,16 +125,29 @@ GAS LISTING .*
|
|||
[ ]*50[ ]+popfl \# can't have 32-bit stack operands
|
||||
[ ]*51[ ]+retl \# can't have 32-bit stack operands
|
||||
[ ]*52[ ]+insertq \$4,\$2,%xmm2,%ebx \# The last operand must be XMM register\.
|
||||
[ ]*53[ ]+\.intel_syntax noprefix
|
||||
[ ]*54[ ]+cmpxchg16b dword ptr \[rax\] \# Must be oword
|
||||
[ ]*55[ ]+movq xmm1, XMMWORD PTR \[rsp\]
|
||||
[ ]*56[ ]+movq xmm1, DWORD PTR \[rsp\]
|
||||
[ ]*57[ ]+movq xmm1, WORD PTR \[rsp\]
|
||||
[ ]*53[ ]+fnstsw %eax
|
||||
[ ]*54[ ]+fnstsw %al
|
||||
[ ]*55[ ]+fstsw %eax
|
||||
[ ]*56[ ]+fstsw %al
|
||||
[ ]*57[ ]+in \$8,%rax
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*58[ ]+movq xmm1, BYTE PTR \[rsp\]
|
||||
[ ]*59[ ]+movq XMMWORD PTR \[rsp\],xmm1
|
||||
[ ]*60[ ]+movq DWORD PTR \[rsp\],xmm1
|
||||
[ ]*61[ ]+movq WORD PTR \[rsp\],xmm1
|
||||
[ ]*62[ ]+movq BYTE PTR \[rsp\],xmm1
|
||||
[ ]*58[ ]+out %rax,\$8
|
||||
[ ]*59[ ]+
|
||||
[ ]*60[ ]+\.intel_syntax noprefix
|
||||
[ ]*61[ ]+cmpxchg16b dword ptr \[rax\] \# Must be oword
|
||||
[ ]*62[ ]+movq xmm1, XMMWORD PTR \[rsp\]
|
||||
[ ]*63[ ]+movq xmm1, DWORD PTR \[rsp\]
|
||||
[ ]*64[ ]+movq xmm1, WORD PTR \[rsp\]
|
||||
[ ]*65[ ]+movq xmm1, BYTE PTR \[rsp\]
|
||||
[ ]*66[ ]+movq XMMWORD PTR \[rsp\],xmm1
|
||||
[ ]*67[ ]+movq DWORD PTR \[rsp\],xmm1
|
||||
[ ]*68[ ]+movq WORD PTR \[rsp\],xmm1
|
||||
[ ]*69[ ]+movq BYTE PTR \[rsp\],xmm1
|
||||
[ ]*70[ ]+fnstsw eax
|
||||
[ ]*71[ ]+fnstsw al
|
||||
[ ]*72[ ]+fstsw eax
|
||||
[ ]*73[ ]+fstsw al
|
||||
[ ]*74[ ]+in rax,8
|
||||
[ ]*75[ ]+out 8,rax
|
||||
|
|
|
|||
|
|
@ -50,6 +50,13 @@ foo: jcxz foo # No prefix exists to select CX as a counter
|
|||
popfl # can't have 32-bit stack operands
|
||||
retl # can't have 32-bit stack operands
|
||||
insertq $4,$2,%xmm2,%ebx # The last operand must be XMM register.
|
||||
fnstsw %eax
|
||||
fnstsw %al
|
||||
fstsw %eax
|
||||
fstsw %al
|
||||
in $8,%rax
|
||||
out %rax,$8
|
||||
|
||||
.intel_syntax noprefix
|
||||
cmpxchg16b dword ptr [rax] # Must be oword
|
||||
movq xmm1, XMMWORD PTR [rsp]
|
||||
|
|
@ -60,3 +67,9 @@ foo: jcxz foo # No prefix exists to select CX as a counter
|
|||
movq DWORD PTR [rsp],xmm1
|
||||
movq WORD PTR [rsp],xmm1
|
||||
movq BYTE PTR [rsp],xmm1
|
||||
fnstsw eax
|
||||
fnstsw al
|
||||
fstsw eax
|
||||
fstsw al
|
||||
in rax,8
|
||||
out 8,rax
|
||||
|
|
|
|||
|
|
@ -191,4 +191,12 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: f3 0f 7e 0c 24 movq \(%rsp\),%xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f d6 0c 24 movq %xmm1,\(%rsp\)
|
||||
[ ]*[a-f0-9]+: 66 0f d6 0c 24 movq %xmm1,\(%rsp\)
|
||||
[ ]*[a-f0-9]+: df e0 fnstsw %ax
|
||||
[ ]*[a-f0-9]+: df e0 fnstsw %ax
|
||||
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
|
||||
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
|
||||
[ ]*[a-f0-9]+: df e0 fnstsw %ax
|
||||
[ ]*[a-f0-9]+: df e0 fnstsw %ax
|
||||
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
|
||||
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -233,5 +233,14 @@ cmpxchg16b oword ptr [rax]
|
|||
movq QWORD PTR [rsp],xmm1
|
||||
movq [rsp],xmm1
|
||||
|
||||
# Get a good alignment.
|
||||
.p2align 4,0
|
||||
.att_syntax
|
||||
fnstsw
|
||||
fnstsw %ax
|
||||
fstsw
|
||||
fstsw %ax
|
||||
|
||||
.intel_syntax noprefix
|
||||
fnstsw
|
||||
fnstsw ax
|
||||
fstsw
|
||||
fstsw ax
|
||||
|
|
|
|||
|
|
@ -1,3 +1,40 @@
|
|||
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
PR gas/5534
|
||||
* i386-gen.c (operand_type_init): Add Dword to
|
||||
OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
|
||||
(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
|
||||
Qword and Xmmword.
|
||||
(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
|
||||
Xmmword, Unspecified and Anysize.
|
||||
(set_bitfield): Make Mmword an alias of Qword. Make Oword
|
||||
an alias of Xmmword.
|
||||
|
||||
* i386-opc.h (CheckSize): Removed.
|
||||
(Byte): Updated.
|
||||
(Word): Likewise.
|
||||
(Dword): Likewise.
|
||||
(Qword): Likewise.
|
||||
(Xmmword): Likewise.
|
||||
(FWait): Updated.
|
||||
(OTMax): Likewise.
|
||||
(i386_opcode_modifier): Remove checksize, byte, word, dword,
|
||||
qword and xmmword.
|
||||
(Fword): New.
|
||||
(TBYTE): Likewise.
|
||||
(Unspecified): Likewise.
|
||||
(Anysize): Likewise.
|
||||
(i386_operand_type): Add byte, word, dword, fword, qword,
|
||||
tbyte xmmword, unspecified and anysize.
|
||||
|
||||
* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
|
||||
Tbyte, Xmmword, Unspecified and Anysize.
|
||||
|
||||
* i386-reg.tbl: Add size for accumulator.
|
||||
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Likewise.
|
||||
|
||||
2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
|
||||
|
|
|
|||
|
|
@ -179,9 +179,9 @@ static initializer operand_type_init [] =
|
|||
{ "OPERAND_TYPE_ESSEG",
|
||||
"EsSeg" },
|
||||
{ "OPERAND_TYPE_ACC32",
|
||||
"Reg32|Acc" },
|
||||
"Reg32|Acc|Dword" },
|
||||
{ "OPERAND_TYPE_ACC64",
|
||||
"Reg64|Acc" },
|
||||
"Reg64|Acc|Qword" },
|
||||
{ "OPERAND_TYPE_REG16_INOUTPORTREG",
|
||||
"Reg16|InOutPortReg" },
|
||||
{ "OPERAND_TYPE_DISP16_32",
|
||||
|
|
@ -273,12 +273,6 @@ static bitfield opcode_modifiers[] =
|
|||
BITFIELD (No_sSuf),
|
||||
BITFIELD (No_qSuf),
|
||||
BITFIELD (No_ldSuf),
|
||||
BITFIELD (CheckSize),
|
||||
BITFIELD (Byte),
|
||||
BITFIELD (Word),
|
||||
BITFIELD (Dword),
|
||||
BITFIELD (Qword),
|
||||
BITFIELD (Xmmword),
|
||||
BITFIELD (FWait),
|
||||
BITFIELD (IsString),
|
||||
BITFIELD (RegKludge),
|
||||
|
|
@ -334,6 +328,15 @@ static bitfield operand_types[] =
|
|||
BITFIELD (JumpAbsolute),
|
||||
BITFIELD (EsSeg),
|
||||
BITFIELD (RegMem),
|
||||
BITFIELD (Byte),
|
||||
BITFIELD (Word),
|
||||
BITFIELD (Dword),
|
||||
BITFIELD (Fword),
|
||||
BITFIELD (Qword),
|
||||
BITFIELD (Tbyte),
|
||||
BITFIELD (Xmmword),
|
||||
BITFIELD (Unspecified),
|
||||
BITFIELD (Anysize),
|
||||
#ifdef OTUnused
|
||||
BITFIELD (OTUnused),
|
||||
#endif
|
||||
|
|
@ -443,6 +446,10 @@ set_bitfield (const char *f, bitfield *array, unsigned int size)
|
|||
|
||||
if (strcmp (f, "CpuSledgehammer") == 0)
|
||||
f= "CpuK8";
|
||||
else if (strcmp (f, "Mmword") == 0)
|
||||
f= "Qword";
|
||||
else if (strcmp (f, "Oword") == 0)
|
||||
f= "Xmmword";
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
if (strcasecmp (array[i].name, f) == 0)
|
||||
|
|
|
|||
|
|
@ -161,176 +161,220 @@
|
|||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG8 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16 \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM1 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_BASEINDEX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SHIFTCOUNT \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_CONTROL \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_TEST \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DEBUG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG2 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG3 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_JUMPABSOLUTE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMMX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGXMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16_INOUTPORTREG \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
|
|
|||
|
|
@ -189,20 +189,8 @@ typedef union i386_cpu_flags
|
|||
#define No_qSuf (No_sSuf + 1)
|
||||
/* long double suffix on instruction illegal */
|
||||
#define No_ldSuf (No_qSuf + 1)
|
||||
/* check memory size on instruction in Intel mode if it is specified. */
|
||||
#define CheckSize (No_ldSuf + 1)
|
||||
/* BYTE memory on instruction */
|
||||
#define Byte (CheckSize + 1)
|
||||
/* WORD memory on instruction */
|
||||
#define Word (Byte + 1)
|
||||
/* DWORD memory on instruction */
|
||||
#define Dword (Word + 1)
|
||||
/* QWORD memory on instruction */
|
||||
#define Qword (Dword + 1)
|
||||
/* XMMWORD memory on instruction */
|
||||
#define Xmmword (Qword + 1)
|
||||
/* instruction needs FWAIT */
|
||||
#define FWait (Xmmword + 1)
|
||||
#define FWait (No_ldSuf + 1)
|
||||
/* quick test for string instructions */
|
||||
#define IsString (FWait + 1)
|
||||
/* fake an extra reg operand for clr, imul and special register
|
||||
|
|
@ -266,12 +254,6 @@ typedef struct i386_opcode_modifier
|
|||
unsigned int no_ssuf:1;
|
||||
unsigned int no_qsuf:1;
|
||||
unsigned int no_ldsuf:1;
|
||||
unsigned int checksize:1;
|
||||
unsigned int byte:1;
|
||||
unsigned int word:1;
|
||||
unsigned int dword:1;
|
||||
unsigned int qword:1;
|
||||
unsigned int xmmword:1;
|
||||
unsigned int fwait:1;
|
||||
unsigned int isstring:1;
|
||||
unsigned int regkludge:1;
|
||||
|
|
@ -295,21 +277,34 @@ typedef struct i386_opcode_modifier
|
|||
|
||||
/* Position of operand_type bits. */
|
||||
|
||||
/* Registers */
|
||||
|
||||
/* 8 bit reg */
|
||||
/* 8bit register */
|
||||
#define Reg8 0
|
||||
/* 16 bit reg */
|
||||
/* 16bit register */
|
||||
#define Reg16 (Reg8 + 1)
|
||||
/* 32 bit reg */
|
||||
/* 32bit register */
|
||||
#define Reg32 (Reg16 + 1)
|
||||
/* 64 bit reg */
|
||||
/* 64bit register */
|
||||
#define Reg64 (Reg32 + 1)
|
||||
|
||||
/* immediate */
|
||||
|
||||
/* Floating pointer stack register */
|
||||
#define FloatReg (Reg64 + 1)
|
||||
/* MMX register */
|
||||
#define RegMMX (FloatReg + 1)
|
||||
/* SSE register */
|
||||
#define RegXMM (RegMMX + 1)
|
||||
/* Control register */
|
||||
#define Control (RegXMM + 1)
|
||||
/* Debug register */
|
||||
#define Debug (Control + 1)
|
||||
/* Test register */
|
||||
#define Test (Debug + 1)
|
||||
/* 2 bit segment register */
|
||||
#define SReg2 (Test + 1)
|
||||
/* 3 bit segment register */
|
||||
#define SReg3 (SReg2 + 1)
|
||||
/* 1 bit immediate */
|
||||
#define Imm1 (SReg3 + 1)
|
||||
/* 8 bit immediate */
|
||||
#define Imm8 (Reg64 + 1)
|
||||
#define Imm8 (Imm1 + 1)
|
||||
/* 8 bit immediate sign extended */
|
||||
#define Imm8S (Imm8 + 1)
|
||||
/* 16 bit immediate */
|
||||
|
|
@ -320,20 +315,15 @@ typedef struct i386_opcode_modifier
|
|||
#define Imm32S (Imm32 + 1)
|
||||
/* 64 bit immediate */
|
||||
#define Imm64 (Imm32S + 1)
|
||||
/* 1 bit immediate */
|
||||
#define Imm1 (Imm64 + 1)
|
||||
|
||||
/* memory */
|
||||
|
||||
#define BaseIndex (Imm1 + 1)
|
||||
/* Disp8,16,32 are used in different ways, depending on the
|
||||
instruction. For jumps, they specify the size of the PC relative
|
||||
displacement, for baseindex type instructions, they specify the
|
||||
size of the offset relative to the base register, and for memory
|
||||
offset instructions such as `mov 1234,%al' they specify the size of
|
||||
the offset relative to the segment base. */
|
||||
/* 8bit/16bit/32bit displacements are used in different ways,
|
||||
depending on the instruction. For jumps, they specify the
|
||||
size of the PC relative displacement, for instructions with
|
||||
memory operand, they specify the size of the offset relative
|
||||
to the base register, and for instructions with memory offset
|
||||
such as `mov 1234,%al' they specify the size of the offset
|
||||
relative to the segment base. */
|
||||
/* 8 bit displacement */
|
||||
#define Disp8 (BaseIndex + 1)
|
||||
#define Disp8 (Imm64 + 1)
|
||||
/* 16 bit displacement */
|
||||
#define Disp16 (Disp8 + 1)
|
||||
/* 32 bit displacement */
|
||||
|
|
@ -342,46 +332,47 @@ typedef struct i386_opcode_modifier
|
|||
#define Disp32S (Disp32 + 1)
|
||||
/* 64 bit displacement */
|
||||
#define Disp64 (Disp32S + 1)
|
||||
|
||||
/* specials */
|
||||
|
||||
/* register to hold in/out port addr = dx */
|
||||
#define InOutPortReg (Disp64 + 1)
|
||||
/* register to hold shift count = cl */
|
||||
/* Accumulator %al/%ax/%eax/%rax */
|
||||
#define Acc (Disp64 + 1)
|
||||
/* Floating pointer top stack register %st(0) */
|
||||
#define FloatAcc (Acc + 1)
|
||||
/* Register which can be used for base or index in memory operand. */
|
||||
#define BaseIndex (FloatAcc + 1)
|
||||
/* Register to hold in/out port addr = dx */
|
||||
#define InOutPortReg (BaseIndex + 1)
|
||||
/* Register to hold shift count = cl */
|
||||
#define ShiftCount (InOutPortReg + 1)
|
||||
/* Control register */
|
||||
#define Control (ShiftCount + 1)
|
||||
/* Debug register */
|
||||
#define Debug (Control + 1)
|
||||
/* Test register */
|
||||
#define Test (Debug + 1)
|
||||
/* Float register */
|
||||
#define FloatReg (Test + 1)
|
||||
/* Float stack top %st(0) */
|
||||
#define FloatAcc (FloatReg + 1)
|
||||
/* 2 bit segment register */
|
||||
#define SReg2 (FloatAcc + 1)
|
||||
/* 3 bit segment register */
|
||||
#define SReg3 (SReg2 + 1)
|
||||
/* Accumulator %al or %ax or %eax */
|
||||
#define Acc (SReg3 + 1)
|
||||
#define JumpAbsolute (Acc + 1)
|
||||
/* MMX register */
|
||||
#define RegMMX (JumpAbsolute + 1)
|
||||
/* XMM registers in PIII */
|
||||
#define RegXMM (RegMMX + 1)
|
||||
/* Absolute address for jump. */
|
||||
#define JumpAbsolute (ShiftCount + 1)
|
||||
/* String insn operand with fixed es segment */
|
||||
#define EsSeg (RegXMM + 1)
|
||||
|
||||
#define EsSeg (JumpAbsolute + 1)
|
||||
/* RegMem is for instructions with a modrm byte where the register
|
||||
destination operand should be encoded in the mod and regmem fields.
|
||||
Normally, it will be encoded in the reg field. We add a RegMem
|
||||
flag to the destination register operand to indicate that it should
|
||||
be encoded in the regmem field. */
|
||||
#define RegMem (EsSeg + 1)
|
||||
/* BYTE memory. */
|
||||
#define Byte (RegMem)
|
||||
/* WORD memory. 2 byte */
|
||||
#define Word (Byte + 1)
|
||||
/* DWORD memory. 4 byte */
|
||||
#define Dword (Word + 1)
|
||||
/* FWORD memory. 6 byte */
|
||||
#define Fword (Dword + 1)
|
||||
/* QWORD memory. 8 byte */
|
||||
#define Qword (Fword + 1)
|
||||
/* TBYTE memory. 10 byte */
|
||||
#define Tbyte (Qword + 1)
|
||||
/* XMMWORD memory. */
|
||||
#define Xmmword (Tbyte + 1)
|
||||
/* Unspecified memory size. */
|
||||
#define Unspecified (Xmmword + 1)
|
||||
/* Any memory size. */
|
||||
#define Anysize (Unspecified + 1)
|
||||
|
||||
/* The last bitfield in i386_operand_type. */
|
||||
#define OTMax RegMem
|
||||
#define OTMax Anysize
|
||||
|
||||
#define OTNumOfUints \
|
||||
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
||||
|
|
@ -390,9 +381,7 @@ typedef struct i386_opcode_modifier
|
|||
|
||||
/* If you get a compiler error for zero width of the unused field,
|
||||
comment it out. */
|
||||
#if 0
|
||||
#define OTUnused (OTMax + 1)
|
||||
#endif
|
||||
|
||||
typedef union i386_operand_type
|
||||
{
|
||||
|
|
@ -402,34 +391,43 @@ typedef union i386_operand_type
|
|||
unsigned int reg16:1;
|
||||
unsigned int reg32:1;
|
||||
unsigned int reg64:1;
|
||||
unsigned int floatreg:1;
|
||||
unsigned int regmmx:1;
|
||||
unsigned int regxmm:1;
|
||||
unsigned int control:1;
|
||||
unsigned int debug:1;
|
||||
unsigned int test:1;
|
||||
unsigned int sreg2:1;
|
||||
unsigned int sreg3:1;
|
||||
unsigned int imm1:1;
|
||||
unsigned int imm8:1;
|
||||
unsigned int imm8s:1;
|
||||
unsigned int imm16:1;
|
||||
unsigned int imm32:1;
|
||||
unsigned int imm32s:1;
|
||||
unsigned int imm64:1;
|
||||
unsigned int imm1:1;
|
||||
unsigned int baseindex:1;
|
||||
unsigned int disp8:1;
|
||||
unsigned int disp16:1;
|
||||
unsigned int disp32:1;
|
||||
unsigned int disp32s:1;
|
||||
unsigned int disp64:1;
|
||||
unsigned int acc:1;
|
||||
unsigned int floatacc:1;
|
||||
unsigned int baseindex:1;
|
||||
unsigned int inoutportreg:1;
|
||||
unsigned int shiftcount:1;
|
||||
unsigned int control:1;
|
||||
unsigned int debug:1;
|
||||
unsigned int test:1;
|
||||
unsigned int floatreg:1;
|
||||
unsigned int floatacc:1;
|
||||
unsigned int sreg2:1;
|
||||
unsigned int sreg3:1;
|
||||
unsigned int acc:1;
|
||||
unsigned int jumpabsolute:1;
|
||||
unsigned int regmmx:1;
|
||||
unsigned int regxmm:1;
|
||||
unsigned int esseg:1;
|
||||
unsigned int regmem:1;
|
||||
unsigned int byte:1;
|
||||
unsigned int word:1;
|
||||
unsigned int dword:1;
|
||||
unsigned int fword:1;
|
||||
unsigned int qword:1;
|
||||
unsigned int tbyte:1;
|
||||
unsigned int xmmword:1;
|
||||
unsigned int unspecified:1;
|
||||
unsigned int anysize:1;
|
||||
#ifdef OTUnused
|
||||
unsigned int unused:(OTNumOfBits - OTUnused);
|
||||
#endif
|
||||
|
|
|
|||
1961
opcodes/i386-opc.tbl
1961
opcodes/i386-opc.tbl
File diff suppressed because it is too large
Load diff
|
|
@ -22,7 +22,7 @@
|
|||
// Make %st first as we test for it.
|
||||
st, FloatReg|FloatAcc, 0, 0
|
||||
// 8 bit regs
|
||||
al, Reg8|Acc, 0, 0
|
||||
al, Reg8|Acc|Byte, 0, 0
|
||||
cl, Reg8|ShiftCount, 0, 1
|
||||
dl, Reg8, 0, 2
|
||||
bl, Reg8, 0, 3
|
||||
|
|
@ -30,7 +30,7 @@ ah, Reg8, 0, 4
|
|||
ch, Reg8, 0, 5
|
||||
dh, Reg8, 0, 6
|
||||
bh, Reg8, 0, 7
|
||||
axl, Reg8|Acc, RegRex64, 0
|
||||
axl, Reg8|Acc|Byte, RegRex64, 0
|
||||
cxl, Reg8, RegRex64, 1
|
||||
dxl, Reg8, RegRex64, 2
|
||||
bxl, Reg8, RegRex64, 3
|
||||
|
|
@ -47,7 +47,7 @@ r13b, Reg8, RegRex|RegRex64, 5
|
|||
r14b, Reg8, RegRex|RegRex64, 6
|
||||
r15b, Reg8, RegRex|RegRex64, 7
|
||||
// 16 bit regs
|
||||
ax, Reg16|Acc, 0, 0
|
||||
ax, Reg16|Acc|Word, 0, 0
|
||||
cx, Reg16, 0, 1
|
||||
dx, Reg16|InOutPortReg, 0, 2
|
||||
bx, Reg16|BaseIndex, 0, 3
|
||||
|
|
@ -64,7 +64,7 @@ r13w, Reg16, RegRex, 5
|
|||
r14w, Reg16, RegRex, 6
|
||||
r15w, Reg16, RegRex, 7
|
||||
// 32 bit regs
|
||||
eax, Reg32|BaseIndex|Acc, 0, 0
|
||||
eax, Reg32|BaseIndex|Acc|Dword, 0, 0
|
||||
ecx, Reg32|BaseIndex, 0, 1
|
||||
edx, Reg32|BaseIndex, 0, 2
|
||||
ebx, Reg32|BaseIndex, 0, 3
|
||||
|
|
@ -80,7 +80,7 @@ r12d, Reg32|BaseIndex, RegRex, 4
|
|||
r13d, Reg32|BaseIndex, RegRex, 5
|
||||
r14d, Reg32|BaseIndex, RegRex, 6
|
||||
r15d, Reg32|BaseIndex, RegRex, 7
|
||||
rax, Reg64|BaseIndex|Acc, 0, 0
|
||||
rax, Reg64|BaseIndex|Acc|Qword, 0, 0
|
||||
rcx, Reg64|BaseIndex, 0, 1
|
||||
rdx, Reg64|BaseIndex, 0, 2
|
||||
rbx, Reg64|BaseIndex, 0, 3
|
||||
|
|
|
|||
17483
opcodes/i386-tbl.h
17483
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue