2003-01-02 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c: Update copyright years.
(print_insn_arg): Rename to...
(print_insn_args): This, returning void. Process the whole
string of args rather than a single one. Reindent.
(print_insn_mips): Update to match the above.
This commit is contained in:
Chris Demetriou
parent
b0ff34ea24
commit
794ac9d074
2 changed files with 319 additions and 317 deletions
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@ -1,3 +1,11 @@
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2003-01-02 Chris Demetriou <cgd@broadcom.com>
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* mips-dis.c: Update copyright years.
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(print_insn_arg): Rename to...
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(print_insn_args): This, returning void. Process the whole
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string of args rather than a single one. Reindent.
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(print_insn_mips): Update to match the above.
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2002-12-31 Chris Demetriou <cgd@broadcom.com>
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* mips-opc.c (mips_builtin_opcodes): Move "di" into the
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@ -1,6 +1,6 @@
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/* Print mips instructions for GDB, the GNU debugger, or for objdump.
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002
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2000, 2001, 2002, 2003
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Free Software Foundation, Inc.
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Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
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@ -50,7 +50,7 @@ static int _print_insn_mips
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PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
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static int print_insn_mips
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PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
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static int print_insn_arg
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static void print_insn_args
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PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
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static int print_insn_mips16
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PARAMS ((bfd_vma, struct disassemble_info *));
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@ -664,342 +664,344 @@ lookup_mips_cp0sel_name(names, len, cp0reg, sel)
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/* Print insn arguments for 32/64-bit code. */
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static int
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print_insn_arg (d, l, pc, info)
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static void
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print_insn_args (d, l, pc, info)
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const char *d;
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register unsigned long int l;
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bfd_vma pc;
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struct disassemble_info *info;
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{
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int op, delta, consumed;
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int op, delta;
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consumed = 1;
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switch (*d)
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for (; *d != '\0'; d++)
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{
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case ',':
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case '(':
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case ')':
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case '[':
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case ']':
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(*info->fprintf_func) (info->stream, "%c", *d);
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break;
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case '+':
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/* Extension character; switch for second char. */
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d++;
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consumed++;
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switch (*d)
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{
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case 'A':
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case ',':
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case '(':
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case ')':
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case '[':
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case ']':
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(*info->fprintf_func) (info->stream, "%c", *d);
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break;
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case '+':
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/* Extension character; switch for second char. */
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d++;
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switch (*d)
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{
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case '\0':
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/* xgettext:c-format */
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(*info->fprintf_func) (info->stream,
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_("# internal error, incomplete extension sequence (+)"));
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return;
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case 'A':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
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break;
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case 'B':
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(*info->fprintf_func) (info->stream, "0x%x",
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(((l >> OP_SH_INSMSB) & OP_MASK_INSMSB)
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- ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT)
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+ 1));
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break;
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case 'C':
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(*info->fprintf_func) (info->stream, "0x%x",
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(((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD)
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+ 1));
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break;
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case 'D':
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{
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const struct mips_cp0sel_name *n;
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unsigned int cp0reg, sel;
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cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
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sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
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/* CP0 register including 'sel' code for mtcN (et al.), to be
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printed textually if known. If not known, print both
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CP0 register name and sel numerically since CP0 register
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with sel 0 may have a name unrelated to register being
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printed. */
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n = lookup_mips_cp0sel_name(mips_cp0sel_names,
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mips_cp0sel_names_len, cp0reg, sel);
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if (n != NULL)
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(*info->fprintf_func) (info->stream, "%s", n->name);
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else
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(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
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break;
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}
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default:
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/* xgettext:c-format */
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(*info->fprintf_func) (info->stream,
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_("# internal error, undefined extension sequence (+%c)"),
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*d);
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return;
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}
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break;
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case 's':
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case 'b':
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case 'r':
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case 'v':
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(*info->fprintf_func) (info->stream, "%s",
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mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
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break;
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case 't':
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case 'w':
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(*info->fprintf_func) (info->stream, "%s",
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mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
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break;
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case 'i':
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case 'u':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
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break;
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case 'j': /* Same as i, but sign-extended. */
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case 'o':
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delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
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if (delta & 0x8000)
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delta |= ~0xffff;
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(*info->fprintf_func) (info->stream, "%d",
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delta);
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break;
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case 'h':
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(*info->fprintf_func) (info->stream, "0x%x",
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(unsigned int) ((l >> OP_SH_PREFX)
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& OP_MASK_PREFX));
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break;
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case 'k':
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(*info->fprintf_func) (info->stream, "0x%x",
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(unsigned int) ((l >> OP_SH_CACHE)
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& OP_MASK_CACHE));
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break;
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case 'a':
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info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
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| (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
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(*info->print_address_func) (info->target, info);
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break;
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case 'p':
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/* Sign extend the displacement. */
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delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
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if (delta & 0x8000)
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delta |= ~0xffff;
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info->target = (delta << 2) + pc + INSNLEN;
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(*info->print_address_func) (info->target, info);
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break;
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case 'd':
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(*info->fprintf_func) (info->stream, "%s",
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mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
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break;
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case 'U':
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{
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/* First check for both rd and rt being equal. */
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unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
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if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
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(*info->fprintf_func) (info->stream, "%s",
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mips_gpr_names[reg]);
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else
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{
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/* If one is zero use the other. */
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if (reg == 0)
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(*info->fprintf_func) (info->stream, "%s",
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mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
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else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
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(*info->fprintf_func) (info->stream, "%s",
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mips_gpr_names[reg]);
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else /* Bogus, result depends on processor. */
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(*info->fprintf_func) (info->stream, "%s or %s",
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mips_gpr_names[reg],
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mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
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}
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}
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break;
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case 'z':
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(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
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break;
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case '<':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
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break;
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case 'B':
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case 'c':
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(*info->fprintf_func) (info->stream, "0x%x",
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(((l >> OP_SH_INSMSB) & OP_MASK_INSMSB)
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- ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT)
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+ 1));
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(l >> OP_SH_CODE) & OP_MASK_CODE);
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break;
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case 'q':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_CODE2) & OP_MASK_CODE2);
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break;
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case 'C':
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(*info->fprintf_func) (info->stream, "0x%x",
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(((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD)
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+ 1));
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(l >> OP_SH_COPZ) & OP_MASK_COPZ);
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break;
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case 'B':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_CODE20) & OP_MASK_CODE20);
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break;
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case 'J':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_CODE19) & OP_MASK_CODE19);
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break;
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case 'S':
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case 'V':
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(*info->fprintf_func) (info->stream, "%s",
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mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
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break;
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case 'T':
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case 'W':
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(*info->fprintf_func) (info->stream, "%s",
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mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
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break;
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case 'D':
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(*info->fprintf_func) (info->stream, "%s",
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mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
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break;
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case 'R':
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(*info->fprintf_func) (info->stream, "%s",
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mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
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break;
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case 'E':
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/* Coprocessor register for lwcN instructions, et al.
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Note that there is no load/store cp0 instructions, and
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that FPU (cp1) instructions disassemble this field using
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'T' format. Therefore, until we gain understanding of
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cp2 register names, we can simply print the register
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numbers. */
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(*info->fprintf_func) (info->stream, "$%d",
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(l >> OP_SH_RT) & OP_MASK_RT);
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break;
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case 'G':
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/* Coprocessor register for mtcN instructions, et al. Note
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that FPU (cp1) instructions disassemble this field using
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'S' format. Therefore, we only need to worry about cp0,
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cp2, and cp3. */
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op = (l >> OP_SH_OP) & OP_MASK_OP;
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if (op == OP_OP_COP0)
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(*info->fprintf_func) (info->stream, "%s",
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mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
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else
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(*info->fprintf_func) (info->stream, "$%d",
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(l >> OP_SH_RD) & OP_MASK_RD);
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break;
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case 'K':
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(*info->fprintf_func) (info->stream, "%s",
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mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
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break;
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case 'N':
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(*info->fprintf_func) (info->stream, "$fcc%d",
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(l >> OP_SH_BCC) & OP_MASK_BCC);
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break;
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case 'M':
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(*info->fprintf_func) (info->stream, "$fcc%d",
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(l >> OP_SH_CCC) & OP_MASK_CCC);
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break;
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case 'P':
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(*info->fprintf_func) (info->stream, "%d",
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(l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
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break;
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case 'e':
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(*info->fprintf_func) (info->stream, "%d",
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(l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
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break;
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case '%':
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(*info->fprintf_func) (info->stream, "%d",
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(l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
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break;
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case 'H':
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(*info->fprintf_func) (info->stream, "%d",
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(l >> OP_SH_SEL) & OP_MASK_SEL);
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break;
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case 'O':
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(*info->fprintf_func) (info->stream, "%d",
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(l >> OP_SH_ALN) & OP_MASK_ALN);
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break;
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case 'Q':
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{
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const struct mips_cp0sel_name *n;
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unsigned int cp0reg, sel;
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cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
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sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
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/* CP0 register including 'sel' code for mtcN (et al.), to be
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printed textually if known. If not known, print both
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CP0 register name and sel numerically since CP0 register
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with sel 0 may have a name unrelated to register being
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printed. */
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n = lookup_mips_cp0sel_name(mips_cp0sel_names,
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mips_cp0sel_names_len, cp0reg, sel);
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if (n != NULL)
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(*info->fprintf_func) (info->stream, "%s", n->name);
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unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
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if ((vsel & 0x10) == 0)
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{
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int fmt;
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vsel &= 0x0f;
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for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
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if ((vsel & 1) == 0)
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break;
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(*info->fprintf_func) (info->stream, "$v%d[%d]",
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(l >> OP_SH_FT) & OP_MASK_FT,
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vsel >> 1);
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}
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else if ((vsel & 0x08) == 0)
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{
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(*info->fprintf_func) (info->stream, "$v%d",
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(l >> OP_SH_FT) & OP_MASK_FT);
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}
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else
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(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
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break;
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{
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_FT) & OP_MASK_FT);
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}
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}
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break;
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case 'X':
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(*info->fprintf_func) (info->stream, "$v%d",
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(l >> OP_SH_FD) & OP_MASK_FD);
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break;
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case 'Y':
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(*info->fprintf_func) (info->stream, "$v%d",
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(l >> OP_SH_FS) & OP_MASK_FS);
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break;
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case 'Z':
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(*info->fprintf_func) (info->stream, "$v%d",
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(l >> OP_SH_FT) & OP_MASK_FT);
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break;
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default:
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/* xgettext:c-format */
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(*info->fprintf_func) (info->stream,
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_("# internal error, undefined extension sequence (+%c)"),
|
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_("# internal error, undefined modifier(%c)"),
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*d);
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||||
/* Do not eat the trailing newline. */
|
||||
if (*d == '\0')
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consumed--;
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||||
break;
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return;
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||||
}
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||||
break;
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case 's':
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case 'b':
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case 'r':
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case 'v':
|
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(*info->fprintf_func) (info->stream, "%s",
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mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
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break;
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case 't':
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case 'w':
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(*info->fprintf_func) (info->stream, "%s",
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mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
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break;
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case 'i':
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case 'u':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
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break;
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case 'j': /* Same as i, but sign-extended. */
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case 'o':
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delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
|
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if (delta & 0x8000)
|
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delta |= ~0xffff;
|
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(*info->fprintf_func) (info->stream, "%d",
|
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delta);
|
||||
break;
|
||||
|
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case 'h':
|
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(*info->fprintf_func) (info->stream, "0x%x",
|
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(unsigned int) ((l >> OP_SH_PREFX)
|
||||
& OP_MASK_PREFX));
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break;
|
||||
|
||||
case 'k':
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
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(unsigned int) ((l >> OP_SH_CACHE)
|
||||
& OP_MASK_CACHE));
|
||||
break;
|
||||
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case 'a':
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||||
info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
|
||||
| (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
|
||||
(*info->print_address_func) (info->target, info);
|
||||
break;
|
||||
|
||||
case 'p':
|
||||
/* Sign extend the displacement. */
|
||||
delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
|
||||
if (delta & 0x8000)
|
||||
delta |= ~0xffff;
|
||||
info->target = (delta << 2) + pc + INSNLEN;
|
||||
(*info->print_address_func) (info->target, info);
|
||||
break;
|
||||
|
||||
case 'd':
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
|
||||
break;
|
||||
|
||||
case 'U':
|
||||
{
|
||||
/* First check for both rd and rt being equal. */
|
||||
unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
|
||||
if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_gpr_names[reg]);
|
||||
else
|
||||
{
|
||||
/* If one is zero use the other. */
|
||||
if (reg == 0)
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
|
||||
else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_gpr_names[reg]);
|
||||
else /* Bogus, result depends on processor. */
|
||||
(*info->fprintf_func) (info->stream, "%s or %s",
|
||||
mips_gpr_names[reg],
|
||||
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 'z':
|
||||
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
|
||||
break;
|
||||
|
||||
case '<':
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
||||
(l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
|
||||
break;
|
||||
|
||||
case 'c':
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
||||
(l >> OP_SH_CODE) & OP_MASK_CODE);
|
||||
break;
|
||||
|
||||
case 'q':
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
||||
(l >> OP_SH_CODE2) & OP_MASK_CODE2);
|
||||
break;
|
||||
|
||||
case 'C':
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
||||
(l >> OP_SH_COPZ) & OP_MASK_COPZ);
|
||||
break;
|
||||
|
||||
case 'B':
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
||||
(l >> OP_SH_CODE20) & OP_MASK_CODE20);
|
||||
break;
|
||||
|
||||
case 'J':
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
||||
(l >> OP_SH_CODE19) & OP_MASK_CODE19);
|
||||
break;
|
||||
|
||||
case 'S':
|
||||
case 'V':
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
|
||||
break;
|
||||
|
||||
case 'T':
|
||||
case 'W':
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
|
||||
break;
|
||||
|
||||
case 'D':
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
|
||||
break;
|
||||
|
||||
case 'R':
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
|
||||
break;
|
||||
|
||||
case 'E':
|
||||
/* Coprocessor register for lwcN instructions, et al.
|
||||
|
||||
Note that there is no load/store cp0 instructions, and
|
||||
that FPU (cp1) instructions disassemble this field using
|
||||
'T' format. Therefore, until we gain understanding of
|
||||
cp2 register names,
|
||||
we can simply print the register numbers. */
|
||||
(*info->fprintf_func) (info->stream, "$%d",
|
||||
(l >> OP_SH_RT) & OP_MASK_RT);
|
||||
break;
|
||||
|
||||
case 'G':
|
||||
/* Coprocessor register for mtcN instructions, et al.
|
||||
Note that FPU (cp1) instructions disassemble this field using
|
||||
'S' format. Therefore, we only need to worry about cp0, cp2,
|
||||
and cp3. */
|
||||
op = (l >> OP_SH_OP) & OP_MASK_OP;
|
||||
if (op == OP_OP_COP0)
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "$%d",
|
||||
(l >> OP_SH_RD) & OP_MASK_RD);
|
||||
break;
|
||||
|
||||
case 'K':
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
|
||||
break;
|
||||
|
||||
case 'N':
|
||||
(*info->fprintf_func) (info->stream, "$fcc%d",
|
||||
(l >> OP_SH_BCC) & OP_MASK_BCC);
|
||||
break;
|
||||
|
||||
case 'M':
|
||||
(*info->fprintf_func) (info->stream, "$fcc%d",
|
||||
(l >> OP_SH_CCC) & OP_MASK_CCC);
|
||||
break;
|
||||
|
||||
case 'P':
|
||||
(*info->fprintf_func) (info->stream, "%d",
|
||||
(l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
|
||||
break;
|
||||
|
||||
case 'e':
|
||||
(*info->fprintf_func) (info->stream, "%d",
|
||||
(l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
|
||||
break;
|
||||
|
||||
case '%':
|
||||
(*info->fprintf_func) (info->stream, "%d",
|
||||
(l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
|
||||
break;
|
||||
|
||||
case 'H':
|
||||
(*info->fprintf_func) (info->stream, "%d",
|
||||
(l >> OP_SH_SEL) & OP_MASK_SEL);
|
||||
break;
|
||||
|
||||
case 'O':
|
||||
(*info->fprintf_func) (info->stream, "%d",
|
||||
(l >> OP_SH_ALN) & OP_MASK_ALN);
|
||||
break;
|
||||
|
||||
case 'Q':
|
||||
{
|
||||
unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
|
||||
if ((vsel & 0x10) == 0)
|
||||
{
|
||||
int fmt;
|
||||
vsel &= 0x0f;
|
||||
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
|
||||
if ((vsel & 1) == 0)
|
||||
break;
|
||||
(*info->fprintf_func) (info->stream, "$v%d[%d]",
|
||||
(l >> OP_SH_FT) & OP_MASK_FT,
|
||||
vsel >> 1);
|
||||
}
|
||||
else if ((vsel & 0x08) == 0)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "$v%d",
|
||||
(l >> OP_SH_FT) & OP_MASK_FT);
|
||||
}
|
||||
else
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "0x%x",
|
||||
(l >> OP_SH_FT) & OP_MASK_FT);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 'X':
|
||||
(*info->fprintf_func) (info->stream, "$v%d",
|
||||
(l >> OP_SH_FD) & OP_MASK_FD);
|
||||
break;
|
||||
|
||||
case 'Y':
|
||||
(*info->fprintf_func) (info->stream, "$v%d",
|
||||
(l >> OP_SH_FS) & OP_MASK_FS);
|
||||
break;
|
||||
|
||||
case 'Z':
|
||||
(*info->fprintf_func) (info->stream, "$v%d",
|
||||
(l >> OP_SH_FT) & OP_MASK_FT);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* xgettext:c-format */
|
||||
(*info->fprintf_func) (info->stream,
|
||||
_("# internal error, undefined modifier(%c)"),
|
||||
*d);
|
||||
break;
|
||||
}
|
||||
|
||||
return consumed;
|
||||
}
|
||||
|
||||
/* Check if the object uses NewABI conventions. */
|
||||
|
|
@ -1106,16 +1108,8 @@ print_insn_mips (memaddr, word, info)
|
|||
d = op->args;
|
||||
if (d != NULL && *d != '\0')
|
||||
{
|
||||
int consumed;
|
||||
|
||||
(*info->fprintf_func) (info->stream, "\t");
|
||||
while (*d != '\0')
|
||||
{
|
||||
/* print_insn_arg will not eat the trailing NUL
|
||||
of (erroneous) multi-character strings. */
|
||||
consumed = print_insn_arg (d, word, memaddr, info);
|
||||
d += consumed;
|
||||
}
|
||||
print_insn_args (d, word, memaddr, info);
|
||||
}
|
||||
|
||||
return INSNLEN;
|
||||
|
|
|
|||
Loading…
Reference in a new issue