* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
vector unit operands. (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector unit instruction formats. (PPCVEC): New macro, mask for vector instructions. (powerpc_operands): Add table entries for above operand types. (powerpc_opcodes): Add table entries for vector instructions. * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask. (print_insn_little_powerpc): Likewise. (print_insn_powerpc): Prepend 'v' when printing vector registers.
This commit is contained in:
J.T. Conklin
parent
7a899fff9a
commit
786e2c0f62
3 changed files with 247 additions and 4 deletions
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@ -1,3 +1,17 @@
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2000-05-03 J.T. Conklin <jtc@redback.com>
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* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
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vector unit operands.
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(VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
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unit instruction formats.
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(PPCVEC): New macro, mask for vector instructions.
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(powerpc_operands): Add table entries for above operand types.
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(powerpc_opcodes): Add table entries for vector instructions.
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* ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
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(print_insn_little_powerpc): Likewise.
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(print_insn_powerpc): Prepend 'v' when printing vector registers.
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Sun Apr 23 17:54:14 2000 Denis Chertykov <denisc@overta.ru>
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* avr-dis.c (reg_fmul_d): New. Extract destination register from
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@ -33,7 +33,8 @@ static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
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int bigendian, int dialect));
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/* Print a big endian PowerPC instruction. For convenience, also
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disassemble instructions supported by the Motorola PowerPC 601. */
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disassemble instructions supported by the Motorola PowerPC 601
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and the Altivec vector unit. */
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int
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print_insn_big_powerpc (memaddr, info)
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@ -41,11 +42,13 @@ print_insn_big_powerpc (memaddr, info)
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struct disassemble_info *info;
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{
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return print_insn_powerpc (memaddr, info, 1,
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PPC_OPCODE_PPC | PPC_OPCODE_601);
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PPC_OPCODE_PPC | PPC_OPCODE_601 |
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PPC_OPCODE_ALTIVEC);
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}
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/* Print a little endian PowerPC instruction. For convenience, also
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disassemble instructions supported by the Motorola PowerPC 601. */
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disassemble instructions supported by the Motorola PowerPC 601
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and the Altivec vector unit. */
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int
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print_insn_little_powerpc (memaddr, info)
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@ -53,7 +56,8 @@ print_insn_little_powerpc (memaddr, info)
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struct disassemble_info *info;
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{
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return print_insn_powerpc (memaddr, info, 0,
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PPC_OPCODE_PPC | PPC_OPCODE_601);
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PPC_OPCODE_PPC | PPC_OPCODE_601 |
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PPC_OPCODE_ALTIVEC);
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}
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/* Print a POWER (RS/6000) instruction. */
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@ -181,6 +185,8 @@ print_insn_powerpc (memaddr, info, bigendian, dialect)
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(*info->fprintf_func) (info->stream, "r%ld", value);
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else if ((operand->flags & PPC_OPERAND_FPR) != 0)
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(*info->fprintf_func) (info->stream, "f%ld", value);
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else if ((operand->flags & PPC_OPERAND_VR) != 0)
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(*info->fprintf_func) (info->stream, "v%ld", value);
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else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
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(*info->print_address_func) (memaddr + value, info);
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else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
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@ -396,6 +396,39 @@ const struct powerpc_operand powerpc_operands[] =
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/* The UI field in a D form instruction. */
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#define UI U + 1
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{ 16, 0, 0, 0, 0 },
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/* The VA field in a VA, VX or VXR form instruction. */
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#define VA UI + 1
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#define VA_MASK (0x1f << 16)
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{5, 16, 0, 0, PPC_OPERAND_VR},
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/* The VB field in a VA, VX or VXR form instruction. */
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#define VB VA + 1
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#define VB_MASK (0x1f << 11)
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{5, 11, 0, 0, PPC_OPERAND_VR},
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/* The VC field in a VA form instruction. */
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#define VC VB + 1
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#define VC_MASK (0x1f << 6)
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{5, 6, 0, 0, PPC_OPERAND_VR},
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/* The VD or VS field in a VA, VX, VXR or X form instruction. */
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#define VD VC + 1
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#define VS VD
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#define VD_MASK (0x1f << 21)
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{5, 21, 0, 0, PPC_OPERAND_VR},
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/* The SIMM field in a VX form instruction. */
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#define SIMM VD + 1
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{ 5, 16, 0, 0, PPC_OPERAND_SIGNED},
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/* The UIMM field in a VX form instruction. */
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#define UIMM SIMM + 1
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{ 5, 16, 0, 0, 0 },
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/* The SHB field in a VA form instruction. */
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#define SHB UIMM + 1
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{ 4, 6, 0, 0, 0 },
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};
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/* The functions used to insert and extract complicated operands. */
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@ -1105,6 +1138,24 @@ extract_tbr (insn, invalid)
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#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
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#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
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/* An VX form instruction. */
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#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
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/* The mask for an VX form instruction. */
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#define VX_MASK VX(0x3f, 0x7ff)
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/* An VA form instruction. */
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#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
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/* The mask for an VA form instruction. */
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#define VXA_MASK VXA(0x3f, 0x7f)
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/* An VXR form instruction. */
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#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
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/* The mask for a VXR form instruction. */
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#define VXR_MASK VXR(0x3f, 0x3ff, 1)
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/* An X form instruction. */
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#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
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@ -1272,6 +1323,7 @@ extract_tbr (insn, invalid)
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#define PPC403 PPC
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#define PPC750 PPC
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#define PPC860 PPC
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#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
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#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
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#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
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#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
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@ -1349,6 +1401,164 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
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{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
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{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
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{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
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{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
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{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
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{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
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{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
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{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
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{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
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{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
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{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
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{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
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{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
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{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
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{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
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{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
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{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
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{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
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{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
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{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vslw", VX(4, 338), VX_MASK, PPCVEC, { VD, VA, VB } },
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||||
{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
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{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
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{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
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{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
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{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
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||||
{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
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||||
{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
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||||
{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
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||||
{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
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||||
{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
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||||
{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
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||||
{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
|
||||
{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
|
||||
{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
|
||||
{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
|
||||
{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
|
||||
{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
|
||||
{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
|
||||
|
||||
{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
|
||||
{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
|
||||
|
||||
|
|
@ -2854,6 +3064,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
|
||||
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
|
||||
|
||||
{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
|
||||
{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
|
||||
{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
|
||||
{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
|
||||
{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
|
||||
{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
|
||||
{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
|
||||
{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
|
||||
{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
|
||||
{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
|
||||
{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
|
||||
{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
|
||||
|
||||
{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
|
||||
{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue