Add emulation of double word load and store instructions.
This commit is contained in:
Nick Clifton
parent
0aec643be7
commit
760a7bbec5
2 changed files with 348 additions and 3 deletions
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@ -1,3 +1,11 @@
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2000-12-07 Nick Clifton <nickc@redhat.com>
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* armemu.c (ARMul_Emulate26): Detect double word load and
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store instructions and call emulation routines.
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(Handle_Load_Double): Emulate a double word load instruction.
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(Handle_Store_Double): Emulate a double word store
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instruction.
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2000-12-03 Nick Clifton <nickc@redhat.com>
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* armos.c: Fix formatting.
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343
sim/arm/armemu.c
343
sim/arm/armemu.c
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@ -39,6 +39,8 @@ static unsigned StoreHalfWord (ARMul_State * state, ARMword instr,
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ARMword address);
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static unsigned StoreByte (ARMul_State * state, ARMword instr,
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ARMword address);
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static unsigned StoreDoubleWord (ARMul_State * state, ARMword instr,
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ARMword address);
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static void LoadMult (ARMul_State * state, ARMword address, ARMword instr,
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ARMword WBBase);
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static void StoreMult (ARMul_State * state, ARMword address, ARMword instr,
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@ -51,6 +53,8 @@ static unsigned Multiply64 (ARMul_State * state, ARMword instr,
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int signextend, int scc);
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static unsigned MultiplyAdd64 (ARMul_State * state, ARMword instr,
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int signextend, int scc);
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static void Handle_Load_Double (ARMul_State * state, ARMword instr);
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static void Handle_Store_Double (ARMul_State * state, ARMword instr);
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#define LUNSIGNED (0) /* unsigned operation */
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#define LSIGNED (1) /* signed operation */
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@ -407,7 +411,7 @@ ARMul_Emulate26 (register ARMul_State * state)
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}
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if (state->Debug)
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{
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fprintf (stderr, "At %08lx Instr %08lx Mode %02lx\n", pc, instr,
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fprintf (stderr, "sim: At %08lx Instr %08lx Mode %02lx\n", pc, instr,
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state->Mode);
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(void) fgetc (stdin);
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}
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@ -610,7 +614,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHDOWNWB ();
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break;
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}
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/* TODO: CHECK: should 0xD and 0xF generate undefined intruction aborts? */
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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if (BITS (4, 7) == 9)
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{ /* MUL */
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@ -769,6 +782,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHDOWNWB ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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rhs = DPRegRHS;
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dest = LHS - rhs;
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@ -847,6 +870,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHUPWB ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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#ifdef MODET
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if (BITS (4, 7) == 0x9)
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@ -971,6 +1004,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHUPWB ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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#ifdef MODET
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if (BITS (4, 7) == 0x9)
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@ -1130,6 +1173,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHPREDOWN ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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if (BITS (4, 11) == 9)
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{ /* SWP */
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@ -1274,6 +1327,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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WriteR15Branch (state, state->Reg[RHSReg]);
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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if (state->is_v5)
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{
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@ -1428,6 +1491,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHPREDOWN ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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if (BITS (4, 11) == 9)
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{ /* SWP */
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@ -1573,6 +1646,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHPREDOWNWB ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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if (DESTReg == 15)
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{ /* MSR */
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@ -1635,6 +1718,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHPREUP ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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rhs = DPRegRHS;
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dest = LHS | rhs;
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@ -1663,6 +1756,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHPREUPWB ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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dest = DPRegRHS;
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WRITEDEST (dest);
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@ -1689,6 +1792,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHPREUP ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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else if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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rhs = DPRegRHS;
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dest = LHS & ~rhs;
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@ -1717,6 +1830,16 @@ ARMul_Emulate26 (register ARMul_State * state)
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SHPREUPWB ();
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break;
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}
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if (BITS (4, 7) == 0xD)
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{
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Handle_Load_Double (state, instr);
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break;
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}
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if (BITS (4, 7) == 0xE)
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{
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Handle_Store_Double (state, instr);
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break;
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}
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#endif
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dest = ~DPRegRHS;
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WRITEDEST (dest);
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@ -3830,6 +3953,220 @@ LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend)
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return (DESTReg != LHSReg);
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}
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/***************************************************************************\
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* This function does the work of loading two words for a LDRD instruction. *
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\***************************************************************************/
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static void
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Handle_Load_Double (ARMul_State * state, ARMword instr)
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{
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ARMword dest_reg;
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ARMword addr_reg;
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ARMword write_back = BIT (21);
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ARMword immediate = BIT (22);
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ARMword add_to_base = BIT (23);
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ARMword pre_indexed = BIT (24);
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ARMword offset;
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ARMword addr;
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ARMword sum;
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ARMword base;
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ARMword value1;
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ARMword value2;
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BUSUSEDINCPCS;
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/* If the writeback bit is set, the pre-index bit must be clear. */
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if (write_back && ! pre_indexed)
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{
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ARMul_UndefInstr (state, instr);
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return;
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}
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/* Extract the base address register. */
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addr_reg = LHSReg;
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/* Extract the destination register and check it. */
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dest_reg = DESTReg;
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/* Destination register must be even. */
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if ((dest_reg & 1)
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/* Destination register cannot be LR. */
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|| (dest_reg == 14))
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{
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ARMul_UndefInstr (state, instr);
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return;
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}
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/* Compute the base address. */
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base = state->Reg[addr_reg];
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/* Compute the offset. */
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offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg];
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/* Compute the sum of the two. */
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if (add_to_base)
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sum = base + offset;
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else
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sum = base - offset;
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/* If this is a pre-indexed mode use the sum. */
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if (pre_indexed)
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addr = sum;
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else
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addr = base;
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/* The address must be aligned on a 8 byte boundary. */
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if (addr & 0x7)
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{
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#ifdef ABORTS
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ARMul_DATAABORT (addr);
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#else
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ARMul_UndefInstr (state, instr);
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#endif
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return;
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}
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/* For pre indexed or post indexed addressing modes,
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check that the destination registers do not overlap
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the address registers. */
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if ((! pre_indexed || write_back)
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&& ( addr_reg == dest_reg
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|| addr_reg == dest_reg + 1))
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{
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ARMul_UndefInstr (state, instr);
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return;
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}
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/* Load the words. */
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value1 = ARMul_LoadWordN (state, addr);
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value2 = ARMul_LoadWordN (state, addr + 4);
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/* Check for data aborts. */
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if (state->Aborted)
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{
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TAKEABORT;
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return;
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}
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ARMul_Icycles (state, 2, 0L);
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/* Store the values. */
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state->Reg[dest_reg] = value1;
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state->Reg[dest_reg + 1] = value2;
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/* Do the post addressing and writeback. */
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if (! pre_indexed)
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addr = sum;
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if (! pre_indexed || write_back)
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state->Reg[addr_reg] = addr;
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}
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/***************************************************************************\
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* This function does the work of storing two words for a STRD instruction. *
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\***************************************************************************/
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static void
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Handle_Store_Double (ARMul_State * state, ARMword instr)
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{
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ARMword src_reg;
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ARMword addr_reg;
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ARMword write_back = BIT (21);
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ARMword immediate = BIT (22);
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ARMword add_to_base = BIT (23);
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ARMword pre_indexed = BIT (24);
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ARMword offset;
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ARMword addr;
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ARMword sum;
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ARMword base;
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BUSUSEDINCPCS;
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/* If the writeback bit is set, the pre-index bit must be clear. */
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if (write_back && ! pre_indexed)
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{
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ARMul_UndefInstr (state, instr);
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return;
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}
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/* Extract the base address register. */
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addr_reg = LHSReg;
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/* Base register cannot be PC. */
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if (addr_reg == 15)
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{
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ARMul_UndefInstr (state, instr);
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return;
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}
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/* Extract the source register. */
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src_reg = DESTReg;
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/* Source register must be even. */
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if (src_reg & 1)
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{
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ARMul_UndefInstr (state, instr);
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return;
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}
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/* Compute the base address. */
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base = state->Reg[addr_reg];
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/* Compute the offset. */
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offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg];
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/* Compute the sum of the two. */
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if (add_to_base)
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sum = base + offset;
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else
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sum = base - offset;
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/* If this is a pre-indexed mode use the sum. */
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if (pre_indexed)
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addr = sum;
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else
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addr = base;
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/* The address must be aligned on a 8 byte boundary. */
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if (addr & 0x7)
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{
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#ifdef ABORTS
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ARMul_DATAABORT (addr);
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#else
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ARMul_UndefInstr (state, instr);
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#endif
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return;
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}
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/* For pre indexed or post indexed addressing modes,
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check that the destination registers do not overlap
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the address registers. */
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if ((! pre_indexed || write_back)
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&& ( addr_reg == src_reg
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|| addr_reg == src_reg + 1))
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{
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ARMul_UndefInstr (state, instr);
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return;
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}
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/* Load the words. */
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ARMul_StoreWordN (state, addr, state->Reg[src_reg]);
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ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]);
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if (state->Aborted)
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{
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TAKEABORT;
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return;
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}
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/* Do the post addressing and writeback. */
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if (! pre_indexed)
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addr = sum;
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if (! pre_indexed || write_back)
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state->Reg[addr_reg] = addr;
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}
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/***************************************************************************\
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* This function does the work of storing a word from a STR instruction. *
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\***************************************************************************/
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@ -4325,7 +4662,7 @@ Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
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state->Reg[nRdHi] = RdHi;
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} /* else undefined result */
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else
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fprintf (stderr, "MULTIPLY64 - INVALID ARGUMENTS\n");
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fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS\n");
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if (scc)
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{
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