darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

2008-01-23 Tristan Gingold <gingold@adacore.com>

Browse source 
* gas/ia64/regs.d: Updated as the ia64 disassembler now displays
        symbolic names for all ar registers.
This commit is contained in:
Tristan Gingold 2008-01-23 08:57:11 +00:00
parent 80098f5188
commit 73f4030dfa
2 changed files with 13 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
gas/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2008-01-23 Tristan Gingold <gingold@adacore.com>
* gas/ia64/regs.d: Updated as the ia64 disassembler now displays
symbolic names for all ar registers.
2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.d: New.

16
gas/testsuite/gas/ia64/regs.d
View file

@ -1952,28 +1952,28 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+: 10 00 4c 44 08 00 mov.m r1=ar.rnat
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 54 44 08 00 mov.m r1=ar21
[ ]*[a-f0-9]+: 10 00 54 44 08 00 mov.m r1=ar.fcr
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 60 44 08 00 mov.m r1=ar24
[ ]*[a-f0-9]+: 10 00 60 44 08 00 mov.m r1=ar.eflag
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 64 44 08 00 mov.m r1=ar25
[ ]*[a-f0-9]+: 10 00 64 44 08 00 mov.m r1=ar.csd
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 68 44 08 00 mov.m r1=ar26
[ ]*[a-f0-9]+: 10 00 68 44 08 00 mov.m r1=ar.ssd
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 6c 44 08 00 mov.m r1=ar27
[ ]*[a-f0-9]+: 10 00 6c 44 08 00 mov.m r1=ar.cflg
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 70 44 08 00 mov.m r1=ar28
[ ]*[a-f0-9]+: 10 00 70 44 08 00 mov.m r1=ar.fsr
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 74 44 08 00 mov.m r1=ar29
[ ]*[a-f0-9]+: 10 00 74 44 08 00 mov.m r1=ar.fir
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 78 44 08 00 mov.m r1=ar30
[ ]*[a-f0-9]+: 10 00 78 44 08 00 mov.m r1=ar.fdr
[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;;
[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0
[ ]*[a-f0-9]+: 10 00 80 44 08 00 mov.m r1=ar.ccv