* config/tc-alpha.c (alpha_ip): Delay calls to emit_add64 until after any
remaining operands are also known to match.
This commit is contained in:
Ken Raeburn
parent
2a6978af8d
commit
71f9b3c097
2 changed files with 77 additions and 55 deletions
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@ -2,6 +2,9 @@ Fri Jan 6 16:59:41 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
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* gasp.c: Include string.h. Put config.h before other includes.
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* config/tc-alpha.c (alpha_ip): Delay calls to emit_add64 until
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after any remaining operands are also known to match.
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Fri Dec 30 18:21:41 1994 Ken Raeburn <raeburn@cujo.cygnus.com>
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* listing.c (list_symbol_table): Build a format string based on
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@ -130,7 +130,7 @@ static void emit_ldah_num PARAMS ((int, bfd_vma, int));
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static void emit_addq_r PARAMS ((int, int, int));
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static void emit_lda_n PARAMS ((int, bfd_vma, int));
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static void emit_add64 PARAMS ((int, int, bfd_vma));
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static int in_range PARAMS ((bfd_vma, int, int));
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static int in_range_signed PARAMS ((bfd_vma, int));
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const pseudo_typeS md_pseudo_table[] =
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{
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@ -430,9 +430,9 @@ s_base ()
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demand_empty_rest_of_line ();
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}
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static int in_range (val, nbits, unsignedness)
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static int in_range_signed (val, nbits)
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bfd_vma val;
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int nbits, unsignedness;
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int nbits;
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{
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/* Look at top bit of value that would be stored, figure out how it
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would be extended by the hardware, and see if that matches the
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@ -445,27 +445,40 @@ static int in_range (val, nbits, unsignedness)
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stored_value = val & mask;
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top_bit = stored_value & (one << nbits - 1);
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missing_bits = val & ~mask;
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if (unsignedness)
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/* will sign-extend */
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if (top_bit)
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{
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return missing_bits == 0;
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/* all remaining bits beyond mask should be one */
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missing_bits |= mask;
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return missing_bits + 1 == 0;
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}
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else
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{
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/* will sign-extend */
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if (top_bit)
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{
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/* all remaining bits beyond mask should be one */
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missing_bits |= mask;
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return missing_bits + 1 == 0;
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}
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else
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{
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/* all other bits should be zero */
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return missing_bits == 0;
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}
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/* all other bits should be zero */
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return missing_bits == 0;
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}
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}
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#if 0
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static int in_range_unsigned (val, nbits)
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bfd_vma val;
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int nbits;
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{
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/* Look at top bit of value that would be stored, figure out how it
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would be extended by the hardware, and see if that matches the
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original supplied value. */
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bfd_vma mask;
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bfd_vma one = 1;
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bfd_vma top_bit, stored_value, missing_bits;
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mask = (one << nbits) - 1;
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stored_value = val & mask;
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top_bit = stored_value & (one << nbits - 1);
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missing_bits = val & ~mask;
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return missing_bits == 0;
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}
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#endif
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static void
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s_gprel32 ()
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{
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@ -509,8 +522,6 @@ create_literal_section (secp, name)
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| SEC_DATA);
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}
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#define create_lita_section() create_literal_section (&lita_sec, ".lita")
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static valueT
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get_lit8_offset (val)
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bfd_vma val;
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@ -648,7 +659,7 @@ md_begin ()
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/* So .sbss will get used for tiny objects. */
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bfd_set_gp_size (stdoutput, 8);
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create_lita_section ();
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create_literal_section (&lita_sec, ".lita");
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/* For handling the GP, create a symbol that won't be output in the
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symbol table. We'll edit it out of relocs later. */
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gp = symbol_create ("<GP value>", lita_sec, 0x8000, &zero_address_frag);
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@ -1136,14 +1147,14 @@ emit_add64 (in, out, num)
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{
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bfd_signed_vma snum = num;
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if (in_range (num, 16, 0))
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if (in_range_signed (num, 16))
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{
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emit_lda_n (out, num, in);
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return;
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}
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if ((num & 0xffff) == 0
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&& in == ZERO
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&& in_range (snum >> 16, 16, 0))
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&& in_range_signed (snum >> 16, 16))
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{
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emit_ldah_num (out, snum >> 16, in);
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return;
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@ -1151,21 +1162,21 @@ emit_add64 (in, out, num)
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/* I'm not sure this one is getting invoked when it could. */
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if ((num & 1) == 0 && in == ZERO)
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{
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if (in_range (snum >> 1, 16, 0))
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if (in_range_signed (snum >> 1, 16))
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{
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emit_lda_n (out, snum >> 1, in);
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emit_addq_r (out, out, out);
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return;
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}
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else if (num & 0x1fffe == 0
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&& in_range (snum >> 17, 16, 0))
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&& in_range_signed (snum >> 17, 16))
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{
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emit_ldah_num (out, snum >> 17, in);
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emit_addq_r (out, out, out);
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return;
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}
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}
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if (in_range (num, 32, 0))
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if (in_range_signed (num, 32))
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{
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bfd_vma lo = num & 0xffff;
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if (lo & 0x8000)
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@ -1202,12 +1213,6 @@ emit_add64 (in, out, num)
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}
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}
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/* Note that for now, this function is called recursively (by way of
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calling md_assemble again). Some of the macros defined as part of
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the assembly language are currently rewritten as sequences of
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strings to be assembled. See, for example, the handling of "divq".
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For efficiency, this should be fixed someday. */
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static int
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alpha_ip (str, insns)
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char *str;
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@ -1223,6 +1228,8 @@ alpha_ip (str, insns)
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unsigned int mask;
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int match = 0, num_gen = 1;
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int comma = 0;
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int do_add64, add64_in, add64_out;
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bfd_vma add64_addend;
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for (s = str;
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islower (*s) || *s == '_' || *s == '/' || *s == '4' || *s == '8';
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@ -1248,7 +1255,7 @@ alpha_ip (str, insns)
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}
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if ((pattern = (struct alpha_opcode *) hash_find (op_hash, str)) == NULL)
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{
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as_warn ("Unknown opcode: `%s'", str);
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as_bad ("Unknown opcode: `%s'", str);
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return -1;
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}
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if (comma)
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@ -1257,6 +1264,7 @@ alpha_ip (str, insns)
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argsStart = s;
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for (;;)
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{
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do_add64 = 0;
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opcode = pattern->match;
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num_gen = 1;
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for (i = 0; i < MAX_INSNS; i++)
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@ -1465,24 +1473,14 @@ alpha_ip (str, insns)
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insns[0].reloc[0].code = BFD_RELOC_26;
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goto immediate;
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#if 0
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case 't': /* 12 bit 0...11 */
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insns[0].reloc = RELOC_0_12;
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case 't': /* 12 bit displacement, for PALcode */
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insns[0].reloc[0].code = BFD_RELOC_12_PCREL;
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goto immediate;
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case '8': /* 8 bit 0...7 */
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insns[0].reloc = RELOC_0_8;
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insns[0].reloc[0].code = BFD_RELOC_8;
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goto immediate;
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case 'I': /* 26 bit immediate */
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insns[0].reloc = RELOC_0_25;
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#else
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case 't':
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case '8':
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abort ();
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#endif
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/*FALLTHROUGH*/
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immediate:
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if (*s == ' ')
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s++;
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@ -1523,8 +1521,10 @@ alpha_ip (str, insns)
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else if (at_ok && macro_ok)
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{
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/* Constant value supplied, but it's too large. */
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emit_add64 (ZERO, AT,
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insns[0].reloc[0].exp.X_add_number);
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do_add64 = 1;
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add64_in = ZERO;
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add64_out = AT;
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add64_addend = insns[0].reloc[0].exp.X_add_number;
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opcode &= ~ 0x1000;
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opcode |= (AT << SB);
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insns[0].reloc[0].code = BFD_RELOC_NONE;
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@ -1534,19 +1534,22 @@ alpha_ip (str, insns)
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}
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else if (insns[0].reloc[0].code == BFD_RELOC_16
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&& insns[0].reloc[0].exp.X_op == O_constant
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&& !in_range (insns[0].reloc[0].exp.X_add_number,
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16, 0))
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&& !in_range_signed (insns[0].reloc[0].exp.X_add_number,
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16))
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{
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bfd_vma val = insns[0].reloc[0].exp.X_add_number;
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if (OPCODE (opcode) == 0x08)
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{
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emit_add64 (ZERO, AT, val);
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do_add64 = 1;
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add64_in = ZERO;
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add64_out = AT;
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add64_addend = val;
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opcode &= ~0x1000;
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opcode |= (AT << SB);
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insns[0].reloc[0].code = BFD_RELOC_NONE;
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}
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else if (OPCODE (opcode) == 0x09
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&& in_range (val >> 16, 16, 0))
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&& in_range_signed (val >> 16, 16))
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{
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/* ldah with high operand - convert to low */
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insns[0].reloc[0].exp.X_add_number >>= 16;
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@ -1667,7 +1670,10 @@ alpha_ip (str, insns)
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top = val - low;
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if (top)
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{
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emit_add64 (ZERO, AT, top);
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do_add64 = 1;
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add64_in = ZERO;
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add64_out = AT;
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add64_addend = top;
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opcode |= AT << SB;
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}
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else
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@ -1821,7 +1827,7 @@ alpha_ip (str, insns)
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note_gpreg (PV);
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jsr = &insns[num_gen++];
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jsr->opcode = (0x68004000 /* jsr */
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jsr->opcode = (pattern->match
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| (mask << SA)
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| (PV << SB)
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| 0);
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@ -2136,6 +2142,11 @@ alpha_ip (str, insns)
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break;
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}
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if (do_add64)
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{
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emit_add64 (add64_in, add64_out, add64_addend);
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}
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insns[0].opcode = opcode;
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return num_gen;
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}
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@ -2361,7 +2372,7 @@ s_alpha_set (x)
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else if (!strcmp ("volatile", s))
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/* ignore */ ;
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else
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as_warn ("Tried to set unrecognized symbol: %s", name);
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as_warn ("Tried to .set unrecognized mode `%s'", name);
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*input_line_pointer = ch;
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demand_empty_rest_of_line ();
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}
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@ -2531,6 +2542,13 @@ md_apply_fix (fixP, valueP)
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*p |= (value & 0x1f);
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goto done;
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case BFD_RELOC_12_PCREL:
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*p++ = value & 0xff;
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value >>= 8;
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*p &= 0xf0;
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*p |= (value & 0x0f);
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goto done;
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case BFD_RELOC_ALPHA_LITERAL:
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case BFD_RELOC_ALPHA_LITUSE:
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return 2;
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@ -2551,7 +2569,8 @@ md_apply_fix (fixP, valueP)
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return 2;
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default:
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as_fatal ("unknown relocation type %d?", fixP->fx_r_type);
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as_fatal ("unhandled relocation type %s",
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bfd_get_reloc_code_name (fixP->fx_r_type));
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return 9;
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}
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