Fix interrupt settings for mn103002, not mn10300 implementation.
This commit is contained in:
Joyce Janczyn
parent
6adf5185c1
commit
7146013910
1 changed files with 52 additions and 66 deletions
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@ -1,4 +1,4 @@
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/* This file is part of the program GDB, the GU debugger.
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/* This file is part of the program GDB, the GNU debugger.
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Copyright (C) 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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@ -21,19 +21,19 @@
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#include "sim-main.h"
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#include "hw-base.h"
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#include "hw-main.h"
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/* DEVICE
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mn103int - mn10300 interrupt controller
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mn103int - mn103002 interrupt controller
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DESCRIPTION
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Implements the mn10300 interrupt controller described in the
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mn10300 user guide.
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Implements the mn103002 interrupt controller described in the
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mn103002 user guide.
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PROPERTIES
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@ -44,9 +44,9 @@
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Specify the address of the ICR (total of 25 registers), IAGR and
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EXTMD registers (within the parent bus).
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The reg property value `0x34000100 0x68 0x34000200 0x8 0x3400280
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The reg property value `0x34000100 0x7C 0x34000200 0x8 0x3400280
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0x8' locates the interrupt controller at the addresses specified in
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the mn10300 interrupt controller user guide.
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the mn103002 interrupt controller user guide.
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PORTS
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@ -83,8 +83,8 @@
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int[0..100] (input)
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Level or edge triggered interrupt input port. Each of the 25
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groups (0..24) can have up to 4 (0..3) interrupt inputs. The
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Level or edge triggered interrupt input port. Each of the 30
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groups (0..30) can have up to 4 (0..3) interrupt inputs. The
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interpretation of a port event/value is determined by the
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configuration of the corresponding interrupt group.
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@ -100,15 +100,15 @@
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edges. Instead any input port event is considered to be an
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interrupt trigger.
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For level sensative interrupts, the interrupt controller ignores
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For level sensitive interrupts, the interrupt controller ignores
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active HIGH/LOW settings and instead always interprets a nonzero
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port value as an interupt assertion and a zero port value as a
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port value as an interrupt assertion and a zero port value as a
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negation.
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*/
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/* The interrupt groups - numbered according to mn10300 convention */
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/* The interrupt groups - numbered according to mn103002 convention */
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enum mn103int_trigger {
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ACTIVE_LOW,
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@ -136,7 +136,7 @@ enum {
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FIRST_NMI_GROUP = 0,
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LAST_NMI_GROUP = 1,
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FIRST_LEVEL_GROUP = 2,
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LAST_LEVEL_GROUP = 24,
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LAST_LEVEL_GROUP = 30,
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NR_GROUPS,
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};
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@ -198,7 +198,13 @@ enum {
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G22_PORT = 88,
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G23_PORT = 92,
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G24_PORT = 96,
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NR_G_PORTS = 100,
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G25_PORT = 100,
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G26_PORT = 104,
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G27_PORT = 108,
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G28_PORT = 112,
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G29_PORT = 116,
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G30_PORT = 120,
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NR_G_PORTS = 124,
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ACK_PORT,
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};
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@ -219,62 +225,42 @@ static const struct hw_port_descriptor mn103int_ports[] = {
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{ "watchdog", G0_PORT + 1, 0, input_port, },
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{ "syserr", G0_PORT + 2, 0, input_port, },
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{ "timer-0-underflow", G2_PORT + 0, 0, input_port, },
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{ "timer-1-underflow", G2_PORT + 1, 0, input_port, },
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{ "timer-2-underflow", G2_PORT + 2, 0, input_port, },
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{ "timer-3-underflow", G2_PORT + 3, 0, input_port, },
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{ "timer-4-underflow", G3_PORT + 0, 0, input_port, },
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{ "timer-5-underflow", G3_PORT + 1, 0, input_port, },
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{ "timer-6-underflow", G3_PORT + 2, 0, input_port, },
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{ "timer-7-underflow", G3_PORT + 3, 0, input_port, },
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{ "timer-0-underflow", G2_PORT, 0, input_port, },
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{ "timer-1-underflow", G3_PORT, 0, input_port, },
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{ "timer-2-underflow", G4_PORT, 0, input_port, },
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{ "timer-3-underflow", G5_PORT, 0, input_port, },
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{ "timer-4-underflow", G6_PORT, 0, input_port, },
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{ "timer-5-underflow", G7_PORT, 0, input_port, },
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{ "timer-6-underflow", G8_PORT, 0, input_port, },
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{ "timer-8-underflow", G4_PORT + 0, 0, input_port, },
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{ "timer-8-compare-a", G4_PORT + 1, 0, input_port, },
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{ "timer-8-compare-b", G4_PORT + 2, 0, input_port, },
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{ "timer-6-compare-a", G9_PORT, 0, input_port, },
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{ "timer-6-compare-b", G10_PORT, 0, input_port, },
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{ "timer-9-underflow", G5_PORT + 0, 0, input_port, },
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{ "timer-9-compare-a", G5_PORT + 1, 0, input_port, },
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{ "timer-9-compare-b", G5_PORT + 2, 0, input_port, },
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{ "dma-0-end", G12_PORT, 0, input_port, },
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{ "dma-1-end", G13_PORT, 0, input_port, },
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{ "dma-2-end", G14_PORT, 0, input_port, },
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{ "dma-3-end", G15_PORT, 0, input_port, },
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{ "timer-10-underflow", G6_PORT + 0, 0, input_port, },
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{ "timer-10-compare-a", G6_PORT + 1, 0, input_port, },
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{ "timer-10-compare-b", G6_PORT + 2, 0, input_port, },
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{ "timer-10-compare-c", G6_PORT + 3, 0, input_port, },
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{ "serial-0-receive", G16_PORT, 0, input_port, },
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{ "serial-0-transmit", G17_PORT, 0, input_port, },
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{ "timer-11-underflow", G7_PORT + 0, 0, input_port, },
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{ "timer-11-compare-a", G7_PORT + 1, 0, input_port, },
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{ "timer-11-compare-b", G7_PORT + 2, 0, input_port, },
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{ "timer-11-compare-c", G7_PORT + 3, 0, input_port, },
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{ "serial-1-receive", G18_PORT, 0, input_port, },
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{ "serial-1-transmit", G19_PORT, 0, input_port, },
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{ "timer-12-underflow", G8_PORT + 0, 0, input_port, },
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{ "timer-12-compare-a", G8_PORT + 1, 0, input_port, },
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{ "timer-12-compare-b", G8_PORT + 2, 0, input_port, },
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{ "timer-12-compare-c", G8_PORT + 3, 0, input_port, },
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{ "serial-2-receive", G20_PORT, 0, input_port, },
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{ "serial-2-transmit", G21_PORT, 0, input_port, },
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{ "timer-11-compare-d", G9_PORT + 0, 0, input_port, },
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{ "timer-12-compare-d", G9_PORT + 1, 0, input_port, },
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{ "irq-0", G23_PORT, 0, input_port, },
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{ "irq-1", G24_PORT, 0, input_port, },
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{ "irq-2", G25_PORT, 0, input_port, },
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{ "irq-3", G26_PORT, 0, input_port, },
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{ "irq-4", G27_PORT, 0, input_port, },
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{ "irq-5", G28_PORT, 0, input_port, },
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{ "irq-6", G29_PORT, 0, input_port, },
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{ "irq-7", G30_PORT, 0, input_port, },
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{ "dma-0-end", G10_PORT, 0, input_port, },
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{ "dma-1-end", G11_PORT, 0, input_port, },
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{ "dma-2-end", G12_PORT, 0, input_port, },
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{ "dma-3-end", G13_PORT, 0, input_port, },
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/* { "ad-end", G24_PORT, 0, input_port, }, a/d conversion end, not in 103002? */
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{ "serial-0-recieve", G14_PORT + 0, 0, input_port, },
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{ "serial-0-transmit", G14_PORT + 1, 0, input_port, },
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{ "serial-1-recieve", G15_PORT + 0, 0, input_port, },
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{ "serial-1-transmit", G15_PORT + 1, 0, input_port, },
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{ "irq-0", G16_PORT, 0, input_port, },
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{ "irq-1", G17_PORT, 0, input_port, },
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{ "irq-2", G18_PORT, 0, input_port, },
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{ "irq-3", G19_PORT, 0, input_port, },
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{ "irq-4", G20_PORT, 0, input_port, },
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{ "irq-5", G21_PORT, 0, input_port, },
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{ "irq-6", G22_PORT, 0, input_port, },
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{ "irq-7", G23_PORT, 0, input_port, },
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{ "ad-end", G24_PORT, 0, input_port, },
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/* interrupt inputs (as generic numbers) */
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@ -303,9 +289,9 @@ static const struct hw_port_descriptor mn103int_ports[] = {
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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static hw_io_read_buffer_callback mn103int_io_read_buffer;
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static hw_io_write_buffer_callback mn103int_io_write_buffer;
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static hw_port_event_callback mn103int_port_event;
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static hw_io_read_buffer_method mn103int_io_read_buffer;
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static hw_io_write_buffer_method mn103int_io_write_buffer;
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static hw_port_event_method mn103int_port_event;
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static void
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attach_mn103int_regs (struct hw *me,
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@ -817,7 +803,7 @@ mn103int_io_write_buffer (struct hw *me,
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}
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const struct hw_device_descriptor dv_mn103int_descriptor[] = {
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const struct hw_descriptor dv_mn103int_descriptor[] = {
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{ "mn103int", mn103int_finish, },
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{ NULL },
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};
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