2006-10-26 Ben Elliston <bje@au.ibm.com>
Anton Blanchard <anton@samba.org> Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH, AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define. (POWER6): Define. (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.", "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.". Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd", "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr", "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix", "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul", "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.", "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc", "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix", "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.", "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.", "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.", "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.", "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.", "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq", "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.", "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.", "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq", "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.", "diexq" and "diexq." opcodes.
This commit is contained in:
Peter Bergner
parent
a3202ebb06
commit
702f0fb48f
2 changed files with 277 additions and 12 deletions
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@ -1,3 +1,31 @@
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2006-10-26 Ben Elliston <bje@au.ibm.com>
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Anton Blanchard <anton@samba.org>
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Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
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AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
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(POWER6): Define.
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(powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
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"frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
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Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
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"mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
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"lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
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"stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
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"dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
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"dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
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"dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
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"dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
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"ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
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"denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
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"dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
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"drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
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"dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
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"dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
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"dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
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"dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
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"drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
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"diexq" and "diexq." opcodes.
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2006-10-26 Daniel Jacobowitz <dan@codesourcery.com>
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* h8300-dis.c (bfd_h8_disassemble): Add missing consts.
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@ -559,10 +559,45 @@ const struct powerpc_operand powerpc_operands[] =
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#define WS_MASK (0x7 << 11)
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{ 3, 11, NULL, NULL, 0 },
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/* The L field in an mtmsrd instruction */
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/* The L field in an mtmsrd or A form instruction. */
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#define MTMSRD_L WS + 1
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#define A_L MTMSRD_L
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{ 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The DCM field in a Z form instruction. */
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#define DCM MTMSRD_L + 1
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{ 6, 16, NULL, NULL, 0 },
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/* Likewise, the DGM field in a Z form instruction. */
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#define DGM DCM + 1
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{ 6, 16, NULL, NULL, 0 },
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#define TE DGM + 1
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{ 5, 11, NULL, NULL, 0 },
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#define RMC TE + 1
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{ 2, 21, NULL, NULL, 0 },
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#define R RMC + 1
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{ 1, 15, NULL, NULL, 0 },
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#define SP R + 1
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{ 2, 11, NULL, NULL, 0 },
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#define S SP + 1
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{ 1, 11, NULL, NULL, 0 },
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/* SH field starting at bit position 16. */
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#define SH16 S + 1
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{ 6, 10, NULL, NULL, 0 },
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/* The L field in an X form with the RT field fixed instruction. */
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#define XRT_L SH16 + 1
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{ 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The EH field in larx instruction. */
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#define EH XRT_L + 1
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{ 1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
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};
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/* The functions used to insert and extract complicated operands. */
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@ -1509,6 +1544,9 @@ extract_tbr (unsigned long insn,
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/* An A_MASK with the FRA and FRC fields fixed. */
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#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
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/* An AFRAFRC_MASK, but with L bit clear. */
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#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
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/* A B form instruction. */
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#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
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#define B_MASK B (0x3f, 1, 1)
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@ -1619,12 +1657,21 @@ extract_tbr (unsigned long insn,
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/* An X form instruction. */
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#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
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/* A Z form instruction. */
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#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
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/* An X form instruction with the RC bit specified. */
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#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
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/* A Z form instruction with the RC bit specified. */
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#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
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/* The mask for an X form instruction. */
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#define X_MASK XRC (0x3f, 0x3ff, 1)
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/* The mask for a Z form instruction. */
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#define Z_MASK ZRC (0x3f, 0x1ff, 1)
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/* An X_MASK with the RA field fixed. */
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#define XRA_MASK (X_MASK | RA_MASK)
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@ -1634,6 +1681,9 @@ extract_tbr (unsigned long insn,
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/* An X_MASK with the RT field fixed. */
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#define XRT_MASK (X_MASK | RT_MASK)
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/* An XRT_MASK mask with the L bits clear. */
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#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
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/* An X_MASK with the RA and RB fields fixed. */
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#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
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@ -1670,6 +1720,9 @@ extract_tbr (unsigned long insn,
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/* An X form sync instruction with everything filled in except the LS field. */
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#define XSYNC_MASK (0xff9fffff)
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/* An X_MASK, but with the EH bit clear. */
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#define XEH_MASK (X_MASK & ~((unsigned long )1))
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/* An X form AltiVec dss instruction. */
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#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
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#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
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@ -1823,6 +1876,7 @@ extract_tbr (unsigned long insn,
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#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
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#define POWER4 PPC_OPCODE_POWER4
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#define POWER5 PPC_OPCODE_POWER5
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#define POWER6 PPC_OPCODE_POWER6
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#define CELL PPC_OPCODE_CELL
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#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
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#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
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@ -3020,11 +3074,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
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{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
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{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
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{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
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{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
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{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
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{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
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{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
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{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
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{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
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{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
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{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
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@ -3325,7 +3386,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
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{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
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{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
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{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
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{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
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@ -3418,9 +3479,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
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{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
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{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
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{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
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{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
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{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
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{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
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@ -3502,6 +3564,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
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{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
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{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
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{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
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{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
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@ -3517,6 +3581,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
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{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
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{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
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{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
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{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
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@ -3704,6 +3770,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
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{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
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{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
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{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
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{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
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{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
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{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
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@ -3925,12 +3992,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
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{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
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{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
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{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
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{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
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{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
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{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
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{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
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{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
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@ -4020,6 +4093,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
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{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
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{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
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{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
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{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
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{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
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{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
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@ -4258,6 +4332,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
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{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
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{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
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{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
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@ -4308,6 +4384,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
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{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
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{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
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{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
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@ -4322,6 +4400,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
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{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
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{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
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{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
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{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
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@ -4339,6 +4419,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
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{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
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{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
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{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
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@ -4349,9 +4431,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
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{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
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{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
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{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
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{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
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{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
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{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
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{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
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{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
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|
@ -4359,6 +4447,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
|
||||
|
||||
{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
|
||||
|
||||
{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
|
||||
|
||||
{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
|
||||
|
|
@ -4380,6 +4470,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
|
||||
|
||||
{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
|
||||
|
||||
{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
|
||||
{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
|
||||
|
||||
|
|
@ -4395,6 +4487,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
|
||||
{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
|
||||
|
||||
{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
|
||||
|
||||
{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
|
||||
|
||||
{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
|
||||
|
|
@ -4409,6 +4503,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
|
||||
|
||||
{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
|
||||
|
||||
{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
|
||||
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
|
||||
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
|
||||
|
|
@ -4498,6 +4594,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
|
||||
|
||||
{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
|
||||
|
||||
{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
|
||||
{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
|
||||
{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
|
||||
|
|
@ -4519,6 +4617,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
|
||||
|
||||
{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "dqua", ZRC(59,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
{ "dqua.", ZRC(59,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
|
||||
{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
|
||||
{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
|
||||
|
||||
|
|
@ -4531,14 +4635,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
|
||||
{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
|
||||
|
||||
{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
|
||||
{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
|
||||
{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
|
||||
{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
|
||||
|
||||
{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
|
||||
{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
|
||||
|
||||
{ "frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
|
||||
{ "frsqrtes.",A(59,26,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
|
||||
{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
|
||||
{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
|
||||
|
||||
{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
|
||||
{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
|
||||
|
|
@ -4552,10 +4656,73 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
|
||||
{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
|
||||
|
||||
{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "drrnd", ZRC(59,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
{ "drrnd.", ZRC(59,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
|
||||
{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
|
||||
{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
|
||||
|
||||
{ "dquai", ZRC(59,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
|
||||
{ "dquai.", ZRC(59,67,1), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
|
||||
|
||||
{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
|
||||
{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
|
||||
|
||||
{ "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
|
||||
{ "drintx.", ZRC(59,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
|
||||
|
||||
{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
|
||||
|
||||
{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
|
||||
{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
|
||||
{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
|
||||
|
||||
{ "drintn", ZRC(59,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
|
||||
{ "drintn.", ZRC(59,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
|
||||
|
||||
{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
|
||||
{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
|
||||
|
||||
{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
|
||||
|
||||
{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
|
||||
|
||||
{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
|
||||
{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
|
||||
|
||||
{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
|
||||
|
||||
{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
|
||||
|
||||
{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
|
||||
|
||||
{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
|
||||
{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
|
||||
{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
|
||||
|
|
@ -4577,6 +4744,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
|
||||
|
||||
{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "dquaq", ZRC(63,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
{ "dquaq.", ZRC(63,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
|
||||
{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
|
||||
{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
|
||||
|
||||
|
|
@ -4611,16 +4787,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
|
||||
{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
|
||||
|
||||
{ "fre", A(63,24,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
|
||||
{ "fre.", A(63,24,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
|
||||
{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
|
||||
{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
|
||||
|
||||
{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
|
||||
{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
|
||||
{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
|
||||
{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
|
||||
|
||||
{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
|
||||
{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
|
||||
{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
|
||||
{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
|
||||
|
||||
{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
|
||||
{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
|
||||
|
|
@ -4644,6 +4820,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
|
||||
|
||||
{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "drrndq", ZRC(63,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
{ "drrndq.", ZRC(63,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
|
||||
{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
|
||||
{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
|
||||
|
||||
|
|
@ -4652,21 +4834,54 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
|
||||
|
||||
{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
|
||||
{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
|
||||
|
||||
{ "dquaiq", ZRC(63,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
|
||||
{ "dquaiq.", ZRC(63,67,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
|
||||
|
||||
{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
|
||||
{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
|
||||
|
||||
{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
|
||||
{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
|
||||
|
||||
{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
|
||||
{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
|
||||
|
||||
{ "drintxq", ZRC(63,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
|
||||
{ "drintxq.",ZRC(63,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
|
||||
|
||||
{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
|
||||
|
||||
{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
|
||||
{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
|
||||
|
||||
{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
|
||||
{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
|
||||
|
||||
{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
|
||||
{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
|
||||
{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
|
||||
|
||||
{ "drintnq", ZRC(63,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
|
||||
{ "drintnq.",ZRC(63,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
|
||||
|
||||
{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
|
||||
{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
|
||||
|
||||
{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
|
||||
{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
|
||||
|
||||
{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
|
||||
{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
|
||||
{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
|
||||
|
|
@ -4676,21 +4891,43 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
|
||||
{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
|
||||
|
||||
{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
|
||||
{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
|
||||
|
||||
{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
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||||
{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
|
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{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
|
||||
{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
|
||||
|
||||
{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
|
||||
{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
|
||||
|
||||
{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
|
||||
{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
|
||||
|
||||
{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
|
||||
{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
|
||||
|
||||
{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
|
||||
{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
|
||||
|
||||
{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
|
||||
{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
|
||||
|
||||
{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
|
||||
|
||||
};
|
||||
|
||||
const int powerpc_num_opcodes =
|
||||
|
|
|
|||
Loading…
Reference in a new issue