* config/tc-sparc.c (sparc_relax): New.
(md_longopts): Add -relax and -no-relax options. (md_parse_options, md_show_usage): Likewise. (md_apply_fix3): Optimize tail call into branch always if possible.
This commit is contained in:
Jakub Jelinek
parent
f7775d95e6
commit
6faf3d667f
2 changed files with 109 additions and 1 deletions
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@ -1,3 +1,10 @@
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2000-05-26 Jakub Jelinek <jakub@redhat.com>
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* config/tc-sparc.c (sparc_relax): New.
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(md_longopts): Add -relax and -no-relax options.
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(md_parse_options, md_show_usage): Likewise.
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(md_apply_fix3): Optimize tail call into branch always if possible.
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Thu May 4 15:27:07 2000 Donald Lindsay <dlindsay@cygnus.com>
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* config/tc-d10v.c (write_2_short, parallel_ok, md_assemble,
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@ -91,6 +91,9 @@ static enum sparc_opcode_arch_val warn_after_architecture;
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has been used in -64. */
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static int no_undeclared_regs;
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/* Non-zero if we should try to relax jumps and calls. */
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static int sparc_relax;
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/* Non-zero if we are generating PIC code. */
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int sparc_pic_code;
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@ -415,6 +418,10 @@ struct option md_longopts[] = {
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#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
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{"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
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#endif
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#define OPTION_RELAX (OPTION_MD_BASE + 14)
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{"relax", no_argument, NULL, OPTION_RELAX},
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#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
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{"no-relax", no_argument, NULL, OPTION_NO_RELAX},
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{NULL, no_argument, NULL, 0}
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};
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size_t md_longopts_size = sizeof(md_longopts);
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@ -574,6 +581,14 @@ md_parse_option (c, arg)
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break;
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#endif
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case OPTION_RELAX:
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sparc_relax = 1;
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break;
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case OPTION_NO_RELAX:
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sparc_relax = 0;
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break;
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default:
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return 0;
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}
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@ -605,7 +620,9 @@ md_show_usage (stream)
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specify variant of SPARC architecture\n\
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-bump warn when assembler switches architectures\n\
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-sparc ignored\n\
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--enforce-aligned-data force .long, etc., to be aligned correctly\n"));
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--enforce-aligned-data force .long, etc., to be aligned correctly\n\
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-relax relax jumps and branches (default)\n\
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-no-relax avoid changing any jumps and branches\n"));
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#ifdef OBJ_AOUT
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fprintf (stream, _("\
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-k generate PIC\n"));
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@ -2915,7 +2932,91 @@ md_apply_fix3 (fixP, value, segment)
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|| fixP->fx_addsy == NULL
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|| symbol_section_p (fixP->fx_addsy))
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++val;
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insn |= val & 0x3fffffff;
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/* See if we have a delay slot */
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if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
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{
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#define G0 0
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#define O7 15
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#define XCC (2 << 20)
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#define COND(x) (((x)&0xf)<<25)
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#define CONDA COND(0x8)
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#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
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#define INSN_BA (F2(0,2) | CONDA)
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#define INSN_OR F3(2, 0x2, 0)
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#define INSN_NOP F2(0,4)
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long delay;
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/* If the instruction is a call with either:
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restore
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arithmetic instruction with rd == %o7
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where rs1 != %o7 and rs2 if it is register != %o7
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then we can optimize if the call destination is near
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by changing the call into a branch always. */
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if (INSN_BIG_ENDIAN)
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delay = bfd_getb32 ((unsigned char *) buf + 4);
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else
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delay = bfd_getl32 ((unsigned char *) buf + 4);
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if ((insn & OP(~0)) != OP(1) || (delay & OP(~0)) != OP(2))
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break;
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if ((delay & OP3(~0)) != OP3(0x3d) /* restore */
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&& ((delay & OP3(0x28)) != 0 /* arithmetic */
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|| ((delay & RD(~0)) != RD(O7))))
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break;
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if ((delay & RS1(~0)) == RS1(O7)
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|| ((delay & F3I(~0)) == 0
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&& (delay & RS2(~0)) == RS2(O7)))
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break;
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/* Ensure the branch will fit into simm22. */
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if ((val & 0x3fe00000)
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&& (val & 0x3fe00000) != 0x3fe00000)
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break;
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/* Check if the arch is v9 and branch will fit
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into simm19. */
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if (((val & 0x3c0000) == 0
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|| (val & 0x3c0000) == 0x3c0000)
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&& (sparc_arch_size == 64
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|| current_architecture >= SPARC_OPCODE_ARCH_V9))
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/* ba,pt %xcc */
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insn = INSN_BPA | (val & 0x7ffff);
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else
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/* ba */
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insn = INSN_BA | (val & 0x3fffff);
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if (fixP->fx_where >= 4
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&& ((delay & (0xffffffff ^ RS1(~0)))
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== (INSN_OR | RD(O7) | RS2(G0))))
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{
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long setter;
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int reg;
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if (INSN_BIG_ENDIAN)
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setter = bfd_getb32 ((unsigned char *) buf - 4);
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else
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setter = bfd_getl32 ((unsigned char *) buf - 4);
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if ((setter & (0xffffffff ^ RD(~0)))
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!= (INSN_OR | RS1(O7) | RS2(G0)))
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break;
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/* The sequence was
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or %o7, %g0, %rN
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call foo
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or %rN, %g0, %o7
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If call foo was replaced with ba, replace
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or %rN, %g0, %o7 with nop. */
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reg = (delay & RS1(~0)) >> 14;
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if (reg != ((setter & RD(~0)) >> 25)
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|| reg == G0 || reg == O7)
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break;
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if (INSN_BIG_ENDIAN)
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bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
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else
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bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
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}
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}
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break;
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case BFD_RELOC_SPARC_11:
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