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* disassemble.c: Formatting.

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(disassemble_init_for_target <ARCH_m32c>): Comment on endian.
This commit is contained in:
Alan Modra 2010-08-06 03:59:49 +00:00
parent 1e0061d22e
commit 6ca4eb7789
2 changed files with 14 additions and 9 deletions
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7
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2010-08-06 Alan Modra <amodra@gmail.com>
* disassemble.c: Formatting.
(disassemble_init_for_target <ARCH_m32c>): Comment on endian.
2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
@ -16,7 +21,7 @@
(rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
r0,r0) and NOP3 (max r0,r0) special cases.
* rx-decode.c: Regenerate.
2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c: Add 0F to VEX opcode enums.

16
opcodes/disassemble.c
View file

@ -114,10 +114,8 @@ disassembler (abfd)
#endif
#ifdef ARCH_arc
case bfd_arch_arc:
{
disassemble = arc_get_disassembler (abfd);
break;
}
disassemble = arc_get_disassembler (abfd);
break;
#endif
#ifdef ARCH_arm
case bfd_arch_arm:
@ -317,9 +315,9 @@ disassembler (abfd)
#ifdef ARCH_or32
case bfd_arch_or32:
if (bfd_big_endian (abfd))
disassemble = print_insn_big_or32;
disassemble = print_insn_big_or32;
else
disassemble = print_insn_little_or32;
disassemble = print_insn_little_or32;
break;
#endif
#ifdef ARCH_pdp11
@ -361,9 +359,9 @@ disassembler (abfd)
#ifdef ARCH_score
case bfd_arch_score:
if (bfd_big_endian (abfd))
disassemble = print_insn_big_score;
disassemble = print_insn_big_score;
else
disassemble = print_insn_little_score;
disassemble = print_insn_little_score;
break;
#endif
#ifdef ARCH_sh
@ -530,6 +528,8 @@ disassemble_init_for_target (struct disassemble_info * info)
#endif
#ifdef ARCH_m32c
case bfd_arch_m32c:
/* This processor in fact is little endian. The value set here
reflects the way opcodes are written in the cgen description. */
info->endian = BFD_ENDIAN_BIG;
if (! info->insn_sets)
{