X86: Add ptwrite instruction
Implement ptwrite instruction defined in Intel64 and IA-32 Architectures Software Developer’s Manual, June 2016. gas/ * config/tc-i386.c (cpu_arch): Add .ptwrite. * doc/c-i386.texi: Document ptwrite and .ptwrite. * testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel, x86-64-ptwrite and x86-64-ptwrite-intel. * testsuite/gas/i386/ptwrite-intel.d: New file. * testsuite/gas/i386/ptwrite.d: Likewise. * testsuite/gas/i386/ptwrite.s: Likewise. * testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.s: Likewise. opcodes/ * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. (PREFIX_MOD_3_0FAE_REG_4): Likewise. (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. (cpu_flags): Add CpuPTWRITE. * i386-opc.h (CpuPTWRITE): New. (i386_cpu_flags): Add cpuptwrite. * i386-opc.tbl: Add ptwrite instruction. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
bb1fe4acb8
commit
6b40c46231
17 changed files with 5524 additions and 5329 deletions
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@ -1,3 +1,16 @@
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2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Add .ptwrite.
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* doc/c-i386.texi: Document ptwrite and .ptwrite.
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* testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel,
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x86-64-ptwrite and x86-64-ptwrite-intel.
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* testsuite/gas/i386/ptwrite-intel.d: New file.
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* testsuite/gas/i386/ptwrite.d: Likewise.
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* testsuite/gas/i386/ptwrite.s: Likewise.
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* testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise.
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* testsuite/gas/i386/x86-64-ptwrite.d: Likewise.
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* testsuite/gas/i386/x86-64-ptwrite.s: Likewise.
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2016-08-19 Tamar Christina <tamar.christina@arm.com>
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* config/tc-arm.c (do_co_reg2c): Added constraint.
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@ -972,6 +972,8 @@ static const arch_entry cpu_arch[] =
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CPU_OSPKE_FLAGS, 0 },
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{ STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
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CPU_RDPID_FLAGS, 0 },
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{ STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
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CPU_PTWRITE_FLAGS, 0 },
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};
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static const noarch_entry cpu_noarch[] =
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@ -166,6 +166,7 @@ accept various extension mnemonics. For example,
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@code{mpx},
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@code{sha},
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@code{rdpid},
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@code{ptwrite},
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@code{prefetchwt1},
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@code{clflushopt},
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@code{se1},
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@ -1195,6 +1196,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
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@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpid}
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@item @samp{.ptwrite}
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@end multitable
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Apart from the warning, there are only two other effects on
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@ -366,6 +366,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "ospke"
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run_dump_test "rdpid"
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run_dump_test "rdpid-intel"
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run_dump_test "ptwrite"
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run_dump_test "ptwrite-intel"
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run_list_test "avx512vl-1" "-al"
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run_list_test "avx512vl-2" "-al"
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@ -767,6 +769,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-ospke"
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run_dump_test "x86-64-rdpid"
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run_dump_test "x86-64-rdpid-intel"
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run_dump_test "x86-64-ptwrite"
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run_dump_test "x86-64-ptwrite-intel"
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run_dump_test "x86-64-fence-as-lock-add-yes"
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run_dump_test "x86-64-fence-as-lock-add-no"
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run_dump_test "x86-64-pr20141"
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18
gas/testsuite/gas/i386/ptwrite-intel.d
Normal file
18
gas/testsuite/gas/i386/ptwrite-intel.d
Normal file
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@ -0,0 +1,18 @@
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#as:
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#objdump: -dw -Mintel
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#name: i386 PTWRITE insns (Intel disassembly)
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#source: ptwrite.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
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+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
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+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[ecx\]
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+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[ecx\]
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+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
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+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[ecx\]
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#pass
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18
gas/testsuite/gas/i386/ptwrite.d
Normal file
18
gas/testsuite/gas/i386/ptwrite.d
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@ -0,0 +1,18 @@
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#as:
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#objdump: -dw
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#name: i386 PTWRITE insns
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#source: ptwrite.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
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+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
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+[a-f0-9]+: f3 0f ae 21 ptwritel \(%ecx\)
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+[a-f0-9]+: f3 0f ae 21 ptwritel \(%ecx\)
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+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
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+[a-f0-9]+: f3 0f ae 21 ptwritel \(%ecx\)
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#pass
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12
gas/testsuite/gas/i386/ptwrite.s
Normal file
12
gas/testsuite/gas/i386/ptwrite.s
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@ -0,0 +1,12 @@
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# Check 32bit PTWRITE instructions
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.text
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_start:
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ptwrite %ecx
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ptwritel %ecx
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ptwrite (%ecx)
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ptwritel (%ecx)
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.intel_syntax noprefix
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ptwrite ecx
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ptwrite DWORD PTR [ecx]
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23
gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
Normal file
23
gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
Normal file
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@ -0,0 +1,23 @@
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#as:
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#objdump: -dw -Mintel
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#name: x86_64 PTWRITE insns (Intel disassembly)
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#source: x86-64-ptwrite.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
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+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
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+[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
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+[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
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+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[rcx\]
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+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[rcx\]
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+[a-f0-9]+: f3 48 0f ae 21 ptwrite QWORD PTR \[rcx\]
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+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
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+[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
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+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[rcx\]
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+[a-f0-9]+: f3 48 0f ae 21 ptwrite QWORD PTR \[rcx\]
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#pass
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23
gas/testsuite/gas/i386/x86-64-ptwrite.d
Normal file
23
gas/testsuite/gas/i386/x86-64-ptwrite.d
Normal file
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@ -0,0 +1,23 @@
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#as:
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#objdump: -dw
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#name: x86_64 PTWRITE insns
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#source: x86-64-ptwrite.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
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+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
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+[a-f0-9]+: f3 48 0f ae e1 ptwrite %rcx
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+[a-f0-9]+: f3 48 0f ae e1 ptwrite %rcx
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+[a-f0-9]+: f3 0f ae 21 ptwritel \(%rcx\)
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+[a-f0-9]+: f3 0f ae 21 ptwritel \(%rcx\)
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+[a-f0-9]+: f3 48 0f ae 21 ptwriteq \(%rcx\)
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+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
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+[a-f0-9]+: f3 48 0f ae e1 ptwrite %rcx
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+[a-f0-9]+: f3 0f ae 21 ptwritel \(%rcx\)
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+[a-f0-9]+: f3 48 0f ae 21 ptwriteq \(%rcx\)
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#pass
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17
gas/testsuite/gas/i386/x86-64-ptwrite.s
Normal file
17
gas/testsuite/gas/i386/x86-64-ptwrite.s
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@ -0,0 +1,17 @@
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# Check 64bit PTWRITE instructions
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.text
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_start:
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ptwrite %ecx
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ptwritel %ecx
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ptwrite %rcx
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ptwriteq %rcx
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ptwrite (%rcx)
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ptwritel (%rcx)
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ptwriteq (%rcx)
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.intel_syntax noprefix
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ptwrite ecx
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ptwrite rcx
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ptwrite DWORD PTR [rcx]
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ptwrite QWORD PTR [rcx]
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@ -1,3 +1,19 @@
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2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
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(PREFIX_MOD_3_0FAE_REG_4): Likewise.
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(prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
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PREFIX_MOD_3_0FAE_REG_4.
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(mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
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PREFIX_MOD_3_0FAE_REG_4.
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* i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
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(cpu_flags): Add CpuPTWRITE.
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* i386-opc.h (CpuPTWRITE): New.
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(i386_cpu_flags): Add cpuptwrite.
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* i386-opc.tbl: Add ptwrite instruction.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
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* arc-dis.h: Wrap around in extern "C".
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@ -984,6 +984,8 @@ enum
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PREFIX_0FAE_REG_1,
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PREFIX_0FAE_REG_2,
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PREFIX_0FAE_REG_3,
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PREFIX_MOD_0_0FAE_REG_4,
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PREFIX_MOD_3_0FAE_REG_4,
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PREFIX_0FAE_REG_6,
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PREFIX_0FAE_REG_7,
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PREFIX_RM_0_0FAE_REG_7,
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@ -4066,6 +4068,18 @@ static const struct dis386 prefix_table[][4] = {
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{ "wrgsbase", { Ev }, 0 },
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},
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/* PREFIX_MOD_0_0FAE_REG_4 */
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{
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{ "xsave", { FXSAVE }, 0 },
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{ "ptwrite%LQ", { Edq }, 0 },
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},
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/* PREFIX_MOD_3_0FAE_REG_4 */
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{
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{ Bad_Opcode },
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{ "ptwrite%LQ", { Edq }, 0 },
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},
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/* PREFIX_0FAE_REG_6 */
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{
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{ "xsaveopt", { FXSAVE }, 0 },
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@ -11869,7 +11883,8 @@ static const struct dis386 mod_table[][2] = {
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},
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{
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/* MOD_0FAE_REG_4 */
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{ "xsave", { FXSAVE }, 0 },
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{ PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
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{ PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
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},
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{
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/* MOD_0FAE_REG_5 */
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@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
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"CpuOSPKE" },
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{ "CPU_RDPID_FLAGS",
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"CpuRDPID" },
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{ "CPU_PTWRITE_FLAGS",
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"CpuPTWRITE" },
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{ "CPU_ANY_X87_FLAGS",
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"CPU_ANY_287_FLAGS|Cpu8087" },
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{ "CPU_ANY_287_FLAGS",
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@ -511,6 +513,7 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuCLZERO),
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BITFIELD (CpuOSPKE),
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BITFIELD (CpuRDPID),
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BITFIELD (CpuPTWRITE),
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BITFIELD (CpuRegMMX),
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BITFIELD (CpuRegXMM),
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BITFIELD (CpuRegYMM),
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File diff suppressed because it is too large
Load diff
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@ -202,6 +202,8 @@ enum
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CpuOSPKE,
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/* RDPID instruction required */
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CpuRDPID,
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/* PTWRITE instruction required */
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CpuPTWRITE,
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/* MMX register support required */
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CpuRegMMX,
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/* XMM register support required */
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@ -320,6 +322,7 @@ typedef union i386_cpu_flags
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unsigned int cpuclzero:1;
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unsigned int cpuospke:1;
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unsigned int cpurdpid:1;
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unsigned int cpuptwrite:1;
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unsigned int cpuregmmx:1;
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unsigned int cpuregxmm:1;
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unsigned int cpuregymm:1;
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@ -5958,3 +5958,9 @@ rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|N
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rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
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// RDPID instructions end.
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// PTWRITE instructions.
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ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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// PTWRITE instructions end.
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10411
opcodes/i386-tbl.h
10411
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load diff
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