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m32r simulator testsuite

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This commit is contained in:
Doug Evans 1998-02-17 21:52:53 +00:00
parent ed063d525f
commit 6b35d9dd89
94 changed files with 1212 additions and 0 deletions
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16
sim/testsuite/sim/m32r/add.cgs Normal file
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# m32r testcase for add $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global add
add:
mvi_h_gr r4, 1
mvi_h_gr r5, 2
add r4, r5
test_h_gr r4, 3
pass

15
sim/testsuite/sim/m32r/add3.cgs Normal file
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# m32r testcase for add3 $dr,$sr,#$slo16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global add3
add3:
mvi_h_gr r5, 1
add3 r4, r5, 2
test_h_gr r4, 3
pass

16
sim/testsuite/sim/m32r/addi.cgs Normal file
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# m32r testcase for addi $dr,#$simm8
# mach(): m32r m32rx
.include "testutils.inc"
start
.global addi
addi:
mvi_h_gr r5, 1
addi r5, 2
test_h_gr r5, 3
pass

11
sim/testsuite/sim/m32r/addv.cgs Normal file
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# m32r testcase for addv $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global addv
addv:
pass

11
sim/testsuite/sim/m32r/addv3.cgs Normal file
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# m32r testcase for addv3 $dr,$sr,#$simm16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global addv3
addv3:
pass

11
sim/testsuite/sim/m32r/and.cgs Normal file
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# m32r testcase for and $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global and
and:
pass

11
sim/testsuite/sim/m32r/and3.cgs Normal file
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# m32r testcase for and3 $dr,$sr,#$uimm16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global and3
and3:
pass

24
sim/testsuite/sim/m32r/bc24.cgs Normal file
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# m32r testcase for bc $disp24
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bc24
bc24:
mvi_h_condbit 0
bc.l test0fail
bra test0pass
test0fail:
fail
test0pass:
mvi_h_condbit 1
bc.l test1pass
fail
test1pass:
pass

23
sim/testsuite/sim/m32r/bc8.cgs Normal file
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# m32r testcase for bc $disp8
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bc8
bc8:
mvi_h_condbit 0
bc.s test0fail
bra test0pass
test0fail:
fail
test0pass:
mvi_h_condbit 1
bc.s test1pass
fail
test1pass:
pass

11
sim/testsuite/sim/m32r/beq.cgs Normal file
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# m32r testcase for beq $src1,$src2,$disp16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global beq
beq:
pass

11
sim/testsuite/sim/m32r/beqz.cgs Normal file
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# m32r testcase for beqz $src2,$disp16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global beqz
beqz:
pass

11
sim/testsuite/sim/m32r/bgez.cgs Normal file
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# m32r testcase for bgez $src2,$disp16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bgez
bgez:
pass

11
sim/testsuite/sim/m32r/bgtz.cgs Normal file
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# m32r testcase for bgtz $src2,$disp16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bgtz
bgtz:
pass

11
sim/testsuite/sim/m32r/blez.cgs Normal file
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# m32r testcase for blez $src2,$disp16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global blez
blez:
pass

11
sim/testsuite/sim/m32r/bltz.cgs Normal file
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# m32r testcase for bltz $src2,$disp16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bltz
bltz:
pass

11
sim/testsuite/sim/m32r/bnc24.cgs Normal file
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# m32r testcase for bnc $disp24
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bnc24
bnc24:
pass

11
sim/testsuite/sim/m32r/bnc8.cgs Normal file
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# m32r testcase for bnc $disp8
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bnc8
bnc8:
pass

11
sim/testsuite/sim/m32r/bne.cgs Normal file
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# m32r testcase for bne $src1,$src2,$disp16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bne
bne:
pass

11
sim/testsuite/sim/m32r/bnez.cgs Normal file
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# m32r testcase for bnez $src2,$disp16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bnez
bnez:
pass

11
sim/testsuite/sim/m32r/bra24.cgs Normal file
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# m32r testcase for bra $disp24
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bra24
bra24:
pass

11
sim/testsuite/sim/m32r/bra8.cgs Normal file
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# m32r testcase for bra $disp8
# mach(): m32r m32rx
.include "testutils.inc"
start
.global bra8
bra8:
pass

11
sim/testsuite/sim/m32r/cmp.cgs Normal file
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# m32r testcase for cmp $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global cmp
cmp:
pass

11
sim/testsuite/sim/m32r/cmpi.cgs Normal file
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# m32r testcase for cmpi $src2,#$simm16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global cmpi
cmpi:
pass

11
sim/testsuite/sim/m32r/cmpu.cgs Normal file
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# m32r testcase for cmpu $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global cmpu
cmpu:
pass

11
sim/testsuite/sim/m32r/cmpui.cgs Normal file
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# m32r testcase for cmpui $src2,#$uimm16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global cmpui
cmpui:
pass

11
sim/testsuite/sim/m32r/div.cgs Normal file
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# m32r testcase for div $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global div
div:
pass

11
sim/testsuite/sim/m32r/divu.cgs Normal file
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# m32r testcase for divu $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global divu
divu:
pass

18
sim/testsuite/sim/m32r/hello.ms Normal file
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# output: Hello world!
.globl _start
_start:
; write (hello world)
ldi8 r3,#14
ld24 r2,#hello
ldi8 r1,#1
ldi8 r0,#5
trap #0
; exit (0)
ldi8 r1,#0
ldi8 r0,#1
trap #0
length: .long 14
hello: .ascii "Hello world!\r\n"

11
sim/testsuite/sim/m32r/ld-d.cgs Normal file
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# m32r testcase for ld $dr,@($slo16,$sr)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ld_d
ld_d:
pass

11
sim/testsuite/sim/m32r/ld-plus.cgs Normal file
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# m32r testcase for ld $dr,@$sr+
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ld_plus
ld_plus:
pass

11
sim/testsuite/sim/m32r/ld.cgs Normal file
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# m32r testcase for ld $dr,@$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ld
ld:
pass

11
sim/testsuite/sim/m32r/ld24.cgs Normal file
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# m32r testcase for ld24 $dr,#$uimm24
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ld24
ld24:
pass

11
sim/testsuite/sim/m32r/ldb-d.cgs Normal file
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# m32r testcase for ldb $dr,@($slo16,$sr)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ldb_d
ldb_d:
pass

11
sim/testsuite/sim/m32r/ldb.cgs Normal file
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# m32r testcase for ldb $dr,@$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ldb
ldb:
pass

11
sim/testsuite/sim/m32r/ldh-d.cgs Normal file
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# m32r testcase for ldh $dr,@($slo16,$sr)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ldh_d
ldh_d:
pass

11
sim/testsuite/sim/m32r/ldh.cgs Normal file
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# m32r testcase for ldh $dr,@$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ldh
ldh:
pass

11
sim/testsuite/sim/m32r/ldi16.cgs Normal file
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# m32r testcase for ldi $dr,$slo16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ldi16
ldi16:
pass

11
sim/testsuite/sim/m32r/ldi8.cgs Normal file
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# m32r testcase for ldi $dr,#$simm8
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ldi8
ldi8:
pass

11
sim/testsuite/sim/m32r/ldub-d.cgs Normal file
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# m32r testcase for ldub $dr,@($slo16,$sr)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ldub_d
ldub_d:
pass

11
sim/testsuite/sim/m32r/ldub.cgs Normal file
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# m32r testcase for ldub $dr,@$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global ldub
ldub:
pass

11
sim/testsuite/sim/m32r/lduh-d.cgs Normal file
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# m32r testcase for lduh $dr,@($slo16,$sr)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global lduh_d
lduh_d:
pass

11
sim/testsuite/sim/m32r/lduh.cgs Normal file
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# m32r testcase for lduh $dr,@$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global lduh
lduh:
pass

11
sim/testsuite/sim/m32r/lock.cgs Normal file
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# m32r testcase for lock $dr,@$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global lock
lock:
pass

17
sim/testsuite/sim/m32r/machi.cgs Normal file
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# m32r testcase for machi $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global machi
machi:
mvi_h_accum0 0, 1
mvi_h_gr r4, 0x10123
mvi_h_gr r5, 0x20456
machi r4, r5
test_h_accum0 0, 0x20001
pass

17
sim/testsuite/sim/m32r/maclo.cgs Normal file
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# m32r testcase for maclo $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global maclo
maclo:
mvi_h_accum0 0, 1
mvi_h_gr r4, 0x1230001
mvi_h_gr r5, 0x4560002
maclo r4, r5
test_h_accum0 0, 0x20001
pass

11
sim/testsuite/sim/m32r/macwhi.cgs Normal file
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# m32r testcase for macwhi $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global macwhi
macwhi:
pass

11
sim/testsuite/sim/m32r/macwlo.cgs Normal file
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# m32r testcase for macwlo $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global macwlo
macwlo:
pass

11
sim/testsuite/sim/m32r/mul.cgs Normal file
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# m32r testcase for mul $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mul
mul:
pass

16
sim/testsuite/sim/m32r/mulhi.cgs Normal file
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# m32r testcase for mulhi $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mulhi
mulhi:
mvi_h_gr r4, 0x40000
mvi_h_gr r5, 0x50000
mulhi r4, r5
test_h_accum0 0, 0x140000
pass

16
sim/testsuite/sim/m32r/mullo.cgs Normal file
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# m32r testcase for mullo $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mullo
mullo:
mvi_h_gr r4, 4
mvi_h_gr r5, 5
mullo r4, r5
test_h_accum0 0, 0x140000
pass

11
sim/testsuite/sim/m32r/mulwhi.cgs Normal file
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# m32r testcase for mulwhi $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mulwhi
mulwhi:
pass

11
sim/testsuite/sim/m32r/mulwlo.cgs Normal file
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# m32r testcase for mulwlo $src1,$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mulwlo
mulwlo:
pass

11
sim/testsuite/sim/m32r/mv.cgs Normal file
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# m32r testcase for mv $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mv
mv:
pass

11
sim/testsuite/sim/m32r/mvfachi.cgs Normal file
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# m32r testcase for mvfachi $dr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mvfachi
mvfachi:
pass

11
sim/testsuite/sim/m32r/mvfaclo.cgs Normal file
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# m32r testcase for mvfaclo $dr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mvfaclo
mvfaclo:
pass

15
sim/testsuite/sim/m32r/mvfacmi.cgs Normal file
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# m32r testcase for mvfacmi $dr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mvfacmi
mvfacmi:
mvi_h_accum0 0x12345678, 0x87654321
mvfacmi r4
test_h_gr r4, 0x56788765
pass

11
sim/testsuite/sim/m32r/mvtachi.cgs Normal file
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# m32r testcase for mvtachi $src1
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mvtachi
mvtachi:
pass

11
sim/testsuite/sim/m32r/mvtaclo.cgs Normal file
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# m32r testcase for mvtaclo $src1
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mvtaclo
mvtaclo:
pass

11
sim/testsuite/sim/m32r/mvtc.cgs Normal file
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# m32r testcase for mvtc $sr,$dcr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global mvtc
mvtc:
pass

11
sim/testsuite/sim/m32r/neg.cgs Normal file
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# m32r testcase for neg $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global neg
neg:
pass

11
sim/testsuite/sim/m32r/nop.cgs Normal file
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# m32r testcase for nop
# mach(): m32r m32rx
.include "testutils.inc"
start
.global nop
nop:
pass

11
sim/testsuite/sim/m32r/not.cgs Normal file
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# m32r testcase for not $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global not
not:
pass

11
sim/testsuite/sim/m32r/or.cgs Normal file
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# m32r testcase for or $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global or
or:
pass

11
sim/testsuite/sim/m32r/or3.cgs Normal file
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# m32r testcase for or3 $dr,$sr,#$ulo16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global or3
or3:
pass

11
sim/testsuite/sim/m32r/rac-d.cgs Normal file
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# m32r testcase for rac $accd
# mach(): m32r m32rx
.include "testutils.inc"
start
.global rac_d
rac_d:
pass

11
sim/testsuite/sim/m32r/rac-ds.cgs Normal file
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# m32r testcase for rac $accd,$accs
# mach(): m32r m32rx
.include "testutils.inc"
start
.global rac_ds
rac_ds:
pass

23
sim/testsuite/sim/m32r/rac.cgs Normal file
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# m32r testcase for rac
# mach(): m32r m32rx
.include "testutils.inc"
start
.global rac
rac:
mvi_h_accum0 1, 0x4001
rac
test_h_accum0 2, 0x10000
mvi_h_accum0 0x3fff, 0xffff4000
rac
test_h_accum0 0x7fff, 0xffff0000
mvi_h_accum0 0xffff8000, 0
rac
test_h_accum0 0xffff8000, 0
pass

11
sim/testsuite/sim/m32r/rach-d.cgs Normal file
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# m32r testcase for rach $accd
# mach(): m32r m32rx
.include "testutils.inc"
start
.global rach_d
rach_d:
pass

11
sim/testsuite/sim/m32r/rach-ds.cgs Normal file
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# m32r testcase for rach $accd,$accs
# mach(): m32r m32rx
.include "testutils.inc"
start
.global rach_ds
rach_ds:
pass

11
sim/testsuite/sim/m32r/rach.cgs Normal file
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# m32r testcase for rach
# mach(): m32r m32rx
.include "testutils.inc"
start
.global rach
rach:
pass

11
sim/testsuite/sim/m32r/rem.cgs Normal file
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# m32r testcase for rem $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global rem
rem:
pass

11
sim/testsuite/sim/m32r/seth.cgs Normal file
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# m32r testcase for seth $dr,#$hi16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global seth
seth:
pass

11
sim/testsuite/sim/m32r/sll.cgs Normal file
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# m32r testcase for sll $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global sll
sll:
pass

11
sim/testsuite/sim/m32r/sll3.cgs Normal file
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# m32r testcase for sll3 $dr,$sr,#$simm16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global sll3
sll3:
pass

11
sim/testsuite/sim/m32r/slli.cgs Normal file
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# m32r testcase for slli $dr,#$uimm5
# mach(): m32r m32rx
.include "testutils.inc"
start
.global slli
slli:
pass

11
sim/testsuite/sim/m32r/sra.cgs Normal file
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# m32r testcase for sra $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global sra
sra:
pass

11
sim/testsuite/sim/m32r/sra3.cgs Normal file
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# m32r testcase for sra3 $dr,$sr,#$simm16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global sra3
sra3:
pass

11
sim/testsuite/sim/m32r/srai.cgs Normal file
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# m32r testcase for srai $dr,#$uimm5
# mach(): m32r m32rx
.include "testutils.inc"
start
.global srai
srai:
pass

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# m32r testcase for srl $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global srl
srl:
pass

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# m32r testcase for srl3 $dr,$sr,#$simm16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global srl3
srl3:
pass

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# m32r testcase for srli $dr,#$uimm5
# mach(): m32r m32rx
.include "testutils.inc"
start
.global srli
srli:
pass

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# m32r testcase for st $src1,@($slo16,$src2)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global st_d
st_d:
pass

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# m32r testcase for st $src1,@-$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global st_minus
st_minus:
pass

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# m32r testcase for st $src1,@+$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global st_plus
st_plus:
pass

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# m32r testcase for st $src1,@$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global st
st:
pass

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# m32r testcase for stb $src1,@($slo16,$src2)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global stb_d
stb_d:
pass

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# m32r testcase for stb $src1,@$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global stb
stb:
pass

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# m32r testcase for sth $src1,@($slo16,$src2)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global sth_d
sth_d:
pass

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# m32r testcase for sth $src1,@$src2
# mach(): m32r m32rx
.include "testutils.inc"
start
.global sth
sth:
pass

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# m32r testcase for sub $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global sub
sub:
pass

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# m32r testcase for subv $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global subv
subv:
pass

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sim/testsuite/sim/m32r/subx.cgs Normal file
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# m32r testcase for subx $dr,$sr
# mach(): m32r m32rx
.include "testutils.inc"
start
.global subx
subx:
pass

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# r0-r3 are used as tmps, consider them call clobbered by these macros.
.macro start
.data
failmsg:
.ascii "fail\n"
passmsg:
.ascii "pass\n"
.text
.global _start
_start:
.endm
.macro exit rc
ldi8 r1, \rc
ldi8 r0, #1
trap #0
.endm
.macro pass
ldi8 r3, 5
ld24 r2, passmsg
ldi8 r1, 1
ldi8 r0, 5
trap #0
exit 0
.endm
.macro fail
ldi8 r3, 5
ld24 r2, failmsg
ldi8 r1, 1
ldi8 r0, 5
trap #0
exit 1
.endm
.macro mvi_h_gr reg, val
.if (\val >= -128) && (\val <= 127)
ldi8 \reg, \val
.else
seth \reg, high(\val)
or3 \reg, \reg, low(\val)
.endif
.endm
# Other macros know this only clobbers r0.
.macro test_h_gr reg, val
mvi_h_gr r0, \val
beq \reg, r0, test_gr\@
fail
test_gr\@:
.endm
.macro mvi_h_condbit val
ldi8 r0, 0
ldi8 r1, 1
.if \val
cmp r0, r1
.else
cmp r1, r0
.endif
.endm
.macro test_h_condbit val
.if \val
bc test_c1\@
fail
test_c1\@:
.else
bnc test_c0\@
fail
test_c0\@:
.endif
.endm
.macro mvi_h_accum0 hi, lo
mvi_h_gr r0, \hi
mvtachi r0
mvi_h_gr r0, \lo
mvtaclo r0
.endm
.macro test_h_accum0 hi, lo
mvfachi r1
test_h_gr r1, \hi
mvfaclo r1
test_h_gr r1, \lo
.endm
# start-sanitize-m32rx
.macro mvi_h_accum1 hi, lo
mvi_h_gr r0, \hi
mvtachi r0, a1
mvi_h_gr r0, \lo
mvtaclo r0, a1
.endm
.macro test_h_accum1 hi, lo
mvfachi r1, a1
test_h_gr r1, \hi
mvfaclo r1, a1
test_h_gr r1, \lo
.endm
# end-sanitize-m32rx

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# m32r testcase for xor3 $dr,$sr,#$uimm16
# mach(): m32r m32rx
.include "testutils.inc"
start
.global xor3
xor3:
pass