(PR14907) Fix HI16S/LO16 relocations when buf[-1] is evaluated.
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Nick Clifton
parent
dc4e95adcc
commit
6aa32b907b
2 changed files with 133 additions and 77 deletions
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@ -1,3 +1,8 @@
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Mon Feb 9 19:40:59 1998 Nick Clifton <nickc@cygnus.com>
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* elf32-v850.c (v850_elf_store_addend_in_insn): Fix another
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LO16/HI16S bug and improve comments about what is going on.
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Sat Feb 7 15:27:03 1998 Ian Lance Taylor <ian@cygnus.com>
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* configure, aclocal.m4: Rebuild with new libtool.
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205
bfd/elf32-v850.c
205
bfd/elf32-v850.c
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@ -713,107 +713,158 @@ v850_elf_store_addend_in_insn (abfd, r_type, addend, address, replace)
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case R_V850_LO16:
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/* Calculate the sum of the value stored in the instruction and the
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addend and check for overflow from the low 16 bits into the high
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16 bits. This can occur if the computation sets the 16th bit when
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before it was clear, since the 16th bit will be sign extended into
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the high part, thus reducing its value by one, but since the 16th bit
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was originally clear, the previous R_V850_HI16_S relocation will not
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have added in an additional 1 to the high part to compensate for this
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effect. Overflow can also occur if the compuation carries into the
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17th bit and it also results in the 16th bit having the same value as
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the 16th bit of the original value. What happens is that the
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R_V850_HI16_S relocation will have already examined the 16th bit of
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the original value and added 1 to the high part if the bit is set.
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This compensates for the sign extension of 16th bit of the result of
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the computation. But now there is a carry into the 17th bit, and this
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has not been allowed for. Note - there is no need to change anything
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if a carry occurs, and the 16th bit changes its value, (this can only
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happen if the bit was set in the original value, but is clear in the
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result of the computation), as the R_V850_HI16_S relocation will have
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already added in 1 to the high part for us. Here are some examples:
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16 bits. The assembler has already done some of this: If the
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value stored in the instruction has its 15th bit set, then the
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assembler will have added 1 to the value stored in the associated
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HI16S reloc. So for example, these relocations:
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original value = 0x12345
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addend = 0x01234
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-------
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0x13579 => R_V850_HI16_S stores 0x0001
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R_V850_LO16 stores 0x3579
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This is OK.
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movhi hi( fred ), r0, r1
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movea lo( fred ), r1, r1
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original value = 0x12345
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addend = 0x07000
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-------
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0x19345 => R_V850_HI16_S stores 0x0001
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R_V850_LO16 stores 0x9345
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will store 0 in the value fields for the MOVHI and MOVEA instructions
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and addend will be the address of fred, but for these instructions:
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but the 0x9345 value gets sign
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extended, so the sum becomes:
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movhi hi( fred + 0x123456), r0, r1
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movea lo( fred + 0x123456), r1, r1
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0x00010000
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0xffff9345
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----------
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0x00009345 which is wrong.
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the value stored in the MOVHI instruction will be 0x12 and the value
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stored in the MOVEA instruction will be 0x3456. If however the
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instructions were:
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This is the first example of overflow.
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movhi hi( fred + 0x10ffff), r0, r1
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movea lo( fred + 0x10ffff), r1, r1
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original value = 0x18888
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addend = 0x08888
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-------
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0x21110 => R_V850_HI16_S stores 0x0002 (because 16th bit of the original value is set)
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R_V850_LO16 stores 0x1110
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then the value stored in the MOVHI instruction would be 0x11 (not
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0x10) and the value stored in the MOVEA instruction would be 0xffff.
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Thus (assuming for the moment that the addend is 0), at run time the
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MOVHI instruction loads 0x110000 into r1, then the MOVEA instruction
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adds 0xffffffff (sign extension!) producing 0x10ffff. Similarly if
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the instructions were:
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and the sum is now:
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movhi hi( fred - 1), r0, r1
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movea lo( fred - 1), r1, r1
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0x00020000
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0x00001110
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----------
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0x00021110 which is OK.
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then 0 is stored in the MOVHI instruction and -1 is stored in the
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MOVEA instruction.
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original value = 0x1ffff
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addend = 0x08888
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-------
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0x28887 => R_V850_HI16_S stores 0x0002
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R_V850_LO16 stores 0x8887
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Overflow can occur if the addition of the value stored in the
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instruction plus the addend sets the 15th bit (counting from 0) when
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before it was clear. This is because the 15th bit will be sign
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extended into the high part, thus reducing its value by one, but
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since the 15th bit was originally clear, the previous HI16S
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relocation will not have added in an additional 1 to the high part
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to compensate for this effect. For example:
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and the sum is now:
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movhi hi( fred + 0x123456), r0, r1
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movea lo( fred + 0x123456), r1, r1
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0x00020000
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0xffff8887
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----------
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0x00018887 which is wrong.
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The value stored in HI16S reloc is 0x12, the value stored in the LO16
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reloc is 0x3456. If we assume that the address of fred is 0x00007000
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then the relocations become:
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This is the second example of overflow.
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(The 16th bit remains set).
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HI16S: 0x0012 + (0x00007000 >> 16) = 0x12
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LO16: 0x3456 + (0x00007000 & 0xffff) = 0xa456
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original value = 0x15555
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addend = 0x0ffff
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-------
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0x25554 => R_V850_HI16_S stores 0x0001
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R_V850_LO16 stores 0x5554
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but when the instructions are executed, the MOVEA instruction's value
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is signed extended, so the sum becomes:
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the sum is now:
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0x00120000
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+ 0xffffa456
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------------
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0x0011a456 but 'fred + 0x123456' = 0x0012a456
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0x00010000
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0x00005554
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----------
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0x00015554 which is wrong.
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Note that if the 15th bit was set in the value stored in the LO16
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reloc, then we do not have to do anything:
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This is the other form of the second
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example of overflow. (The 16th bit
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remains clear)
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movhi hi( fred + 0x10ffff), r0, r1
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movea lo( fred + 0x10ffff), r1, r1
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HI16S: 0x0011 + (0x00007000 >> 16) = 0x11
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LO16: 0xffff + (0x00007000 & 0xffff) = 0x6fff
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0x00110000
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+ 0x00006fff
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------------
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0x00116fff = fred + 0x10ffff = 0x7000 + 0x10ffff
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Overflow can also occur if the computation carries into the 16th bit
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and it also results in the 15th bit having the same value as the 15th
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bit of the original value. What happens is that the HI16S reloc
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will have already examined the 15th bit of the original value and
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added 1 to the high part if the bit is set. This compensates for the
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sign extension of 15th bit of the result of the computation. But now
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there is a carry into the 16th bit, and this has not been allowed for.
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So, for example if fred is at address 0xf000:
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movhi hi( fred + 0xffff), r0, r1 [bit 15 of the offset is 1]
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movea lo( fred + 0xffff), r1, r1
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HI16S: 0x0001 + (0x0000f000 >> 16) = 0x0001
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LO16: 0xffff + (0x0000f000 & 0xffff) = 0xefff (carry into bit 16)
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0x00010000
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+ 0xffffefff
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------------
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0x0000efff but 'fred + 0xffff' = 0x0001efff
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Similarly, if the 15th bit remains clear, but overflow occurs into
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the 16th bit then (assuming the address of fred is 0xf000):
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movhi hi( fred + 0x7000), r0, r1 [bit 15 of the offset is 0]
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movea lo( fred + 0x7000), r1, r1
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HI16S: 0x0000 + (0x0000f000 >> 16) = 0x0000
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LO16: 0x7000 + (0x0000f000 & 0xffff) = 0x6fff (carry into bit 16)
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0x00000000
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+ 0x00006fff
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------------
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0x00006fff but 'fred + 0x7000' = 0x00016fff
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Note - there is no need to change anything if a carry occurs, and the
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15th bit changes its value from being set to being clear, as the HI16S
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reloc will have already added in 1 to the high part for us:
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movhi hi( fred + 0xffff), r0, r1 [bit 15 of the offset is 1]
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movea lo( fred + 0xffff), r1, r1
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HI16S: 0x0001 + (0x00007000 >> 16)
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LO16: 0xffff + (0x00007000 & 0xffff) = 0x6fff (carry into bit 16)
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0x00010000
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+ 0x00006fff (bit 15 not set, so the top half is zero)
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------------
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0x00016fff which is right (assuming that fred is at 0x7000)
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but if the 15th bit goes from being clear to being set, then we must
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once again handle overflow:
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movhi hi( fred + 0x7000), r0, r1 [bit 15 of the offset is 0]
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movea lo( fred + 0x7000), r1, r1
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HI16S: 0x0000 + (0x0000ffff >> 16)
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LO16: 0x7000 + (0x0000ffff & 0xffff) = 0x6fff (carry into bit 16)
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0x00000000
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+ 0x00006fff (bit 15 not set, so the top half is zero)
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------------
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0x00006fff which is wrong (assuming that fred is at 0xffff)
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*/
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{
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long result;
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insn = bfd_get_16 (abfd, address);
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result = insn + addend;
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#define BIT16_SET(x) ((x) & 0x8000)
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#define OVERFLOWS(a,i) (((a) & 0xffff) + (i) > 0xffff)
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#define BIT15_SET(x) ((x) & 0x8000)
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#define OVERFLOWS(a,i) ((((a) & 0xffff) + (i)) > 0xffff)
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if ((BIT16_SET (result) && ! BIT16_SET (addend))
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|| (OVERFLOWS (addend, insn)
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&& (BIT16_SET (result) == BIT16_SET (addend))))
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if ((BIT15_SET (result) && ! BIT15_SET (addend))
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|| (OVERFLOWS (addend, insn)
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&& ((! BIT15_SET (insn)) || (BIT15_SET (addend)))))
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{
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/* Amend the preceding HI16_S relocation, allowing for
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an intervening instruction, which does occasionally happen. */
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