* arm-dis.c (print_insn_arm): Constify "insn". Formatting.
(print_insn_thumb): Likewise. * h8500-dis.c (print_insn_h8500): Constify "opcode". * mcore-dis.c (print_insn_mcore): Constify "op". Formatting. * ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid type-punned pointer warnings. <case 'L'>: Likewise. Fix error message too. * pdp11-dis.c (print_reg): Warning fix. * sh-dis.c (print_movxy): Constify "op" param. (print_insn_ddt): Constify sh_opcode_info vars. (print_insn_ppi): Likewise. (print_insn_sh): Likewise. * tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid type-punned pointer warnings. * w65-dis.c (print_insn_w65): Constify "op".
This commit is contained in:
Alan Modra
parent
4c83186b76
commit
6a51a8a8d3
9 changed files with 123 additions and 61 deletions
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@ -1,3 +1,21 @@
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2002-12-02 Alan Modra <amodra@bigpond.net.au>
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* arm-dis.c (print_insn_arm): Constify "insn". Formatting.
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(print_insn_thumb): Likewise.
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* h8500-dis.c (print_insn_h8500): Constify "opcode".
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* mcore-dis.c (print_insn_mcore): Constify "op". Formatting.
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* ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid
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type-punned pointer warnings.
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<case 'L'>: Likewise. Fix error message too.
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* pdp11-dis.c (print_reg): Warning fix.
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* sh-dis.c (print_movxy): Constify "op" param.
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(print_insn_ddt): Constify sh_opcode_info vars.
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(print_insn_ppi): Likewise.
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(print_insn_sh): Likewise.
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* tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid
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type-punned pointer warnings.
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* w65-dis.c (print_insn_w65): Constify "op".
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2002-12-01 Stephane Carrez <stcarrez@nerim.fr>
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* m68hc11-dis.c (PC_REGNUM): Define.
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@ -172,13 +172,13 @@ arm_decode_shift (given, func, stream)
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static int
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print_insn_arm (pc, info, given)
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bfd_vma pc;
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struct disassemble_info * info;
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long given;
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bfd_vma pc;
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struct disassemble_info *info;
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long given;
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{
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struct arm_opcode * insn;
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void * stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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const struct arm_opcode *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = arm_opcodes; insn->assembler; insn++)
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{
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@ -753,13 +753,13 @@ print_insn_arm (pc, info, given)
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static int
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print_insn_thumb (pc, info, given)
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bfd_vma pc;
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struct disassemble_info * info;
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long given;
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bfd_vma pc;
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struct disassemble_info *info;
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long given;
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{
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struct thumb_opcode * insn;
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void * stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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const struct thumb_opcode *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = thumb_opcodes; insn->assembler; insn++)
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{
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@ -1,5 +1,5 @@
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/* Disassemble h8500 instructions.
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Copyright 1993, 1998, 2000, 2001 Free Software Foundation, Inc.
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Copyright 1993, 1998, 2000, 2001, 2002 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -78,7 +78,7 @@ print_insn_h8500 (addr, info)
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bfd_vma addr;
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disassemble_info *info;
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{
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h8500_opcode_info *opcode;
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const h8500_opcode_info *opcode;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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@ -1,5 +1,5 @@
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/* Disassemble Motorola M*Core instructions.
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Copyright 1993, 1999, 2000 Free Software Foundation, Inc.
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Copyright 1993, 1999, 2000, 2002 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -89,12 +89,12 @@ print_insn_mcore (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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unsigned char ibytes[4];
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fprintf_ftype fprintf = info->fprintf_func;
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void * stream = info->stream;
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unsigned short inst;
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mcore_opcode_info * op;
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int status;
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unsigned char ibytes[4];
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fprintf_ftype fprintf = info->fprintf_func;
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void *stream = info->stream;
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unsigned short inst;
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const mcore_opcode_info *op;
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int status;
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info->bytes_per_chunk = 2;
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@ -128,19 +128,48 @@ print_insn_mcore (memaddr, info)
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switch (op->opclass)
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{
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case O0: break;
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case OT: fprintf (stream, "\t%d", inst & 0x3); break;
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case O0:
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break;
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case OT:
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fprintf (stream, "\t%d", inst & 0x3);
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break;
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case O1:
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case JMP:
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case JSR: fprintf (stream, "\t%s", name); break;
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case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
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case O1R1: fprintf (stream, "\t%s, r1", name); break;
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case JSR:
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fprintf (stream, "\t%s", name);
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break;
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case OC:
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fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
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break;
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case O1R1:
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fprintf (stream, "\t%s, r1", name);
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break;
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case MULSH:
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case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
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case X1: fprintf (stream, "\tr1, %s", name); break;
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case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
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case RM: fprintf (stream, "\t%s-r15, (r0)", name); break;
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case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break;
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case O2:
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fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
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break;
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case X1:
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fprintf (stream, "\tr1, %s", name);
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break;
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case OI:
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fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
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break;
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case RM:
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fprintf (stream, "\t%s-r15, (r0)", name);
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break;
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case RQ:
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fprintf (stream, "\tr4-r7, (%s)", name);
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break;
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case OB:
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case OBRa:
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case OBRb:
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@ -149,10 +178,17 @@ print_insn_mcore (memaddr, info)
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case SIa:
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case OMa:
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case OMb:
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case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break;
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case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break;
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case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
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name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
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case OMc:
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fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F);
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break;
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case I7:
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fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F);
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break;
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case LS:
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fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
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name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
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break;
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case BR:
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@ -1,5 +1,5 @@
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/* Print National Semiconductor 32000 instructions.
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Copyright 1986, 1988, 1991, 1992, 1994, 1998, 2001
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Copyright 1986, 1988, 1991, 1992, 1994, 1998, 2001, 2002
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Free Software Foundation, Inc.
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This file is part of opcodes library.
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@ -556,10 +556,13 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
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char *result;
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int index_offset;
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{
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int addr_mode;
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float Fvalue;
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double Lvalue;
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union {
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float f;
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double d;
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int i[2];
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} value;
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int Ivalue;
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int addr_mode;
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int disp1, disp2;
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int index;
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int size;
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sprintf (result, "$%d", Ivalue);
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break;
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case 'F':
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bit_copy (buffer, *aoffsetp, 32, (char *) &Fvalue);
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flip_bytes ((char *) & Fvalue, 4);
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bit_copy (buffer, *aoffsetp, 32, (char *) &value.f);
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flip_bytes ((char *) &value.f, 4);
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*aoffsetp += 32;
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if (INVALID_FLOAT (&Fvalue, 4))
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sprintf (result, "<<invalid float 0x%.8x>>", *(int *) &Fvalue);
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if (INVALID_FLOAT (&value.f, 4))
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sprintf (result, "<<invalid float 0x%.8x>>", value.i[0]);
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else /* assume host has ieee float */
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sprintf (result, "$%g", Fvalue);
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sprintf (result, "$%g", value.f);
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break;
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case 'L':
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bit_copy (buffer, *aoffsetp, 64, (char *) &Lvalue);
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flip_bytes ((char *) & Lvalue, 8);
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bit_copy (buffer, *aoffsetp, 64, (char *) &value.d);
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flip_bytes ((char *) &value.d, 8);
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*aoffsetp += 64;
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if (INVALID_FLOAT (&Lvalue, 8))
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sprintf (result, "<<invalid long 0x%.8x%.8x>>",
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*(((int *) &Lvalue) + 1), *(int *) &Lvalue);
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if (INVALID_FLOAT (&value.d, 8))
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sprintf (result, "<<invalid double 0x%.8x%.8x>>",
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value.i[1], value.i[0]);
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else /* assume host has ieee float */
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sprintf (result, "$%g", Lvalue);
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sprintf (result, "$%g", value.d);
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break;
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}
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break;
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@ -84,7 +84,7 @@ print_reg (reg, info)
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FPRINTF (F, "r%d", reg); break;
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case 6: FPRINTF (F, "sp"); break;
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case 7: FPRINTF (F, "pc"); break;
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default: /* error */
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default: ; /* error */
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}
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}
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@ -29,14 +29,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#endif
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static void print_movxy
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PARAMS ((sh_opcode_info *, int, int, fprintf_ftype, void *));
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PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *));
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static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
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static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
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static void print_insn_ppi PARAMS ((int, struct disassemble_info *));
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static void
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print_movxy (op, rn, rm, fprintf_fn, stream)
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sh_opcode_info *op;
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const sh_opcode_info *op;
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int rn, rm;
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fprintf_ftype fprintf_fn;
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void *stream;
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@ -105,8 +105,8 @@ print_insn_ddt (insn, info)
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fprintf_fn (stream, ".word 0x%x", insn);
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else
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{
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static sh_opcode_info *first_movx, *first_movy;
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sh_opcode_info *opx, *opy;
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static const sh_opcode_info *first_movx, *first_movy;
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const sh_opcode_info *opx, *opy;
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unsigned int insn_x, insn_y;
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if (! first_movx)
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@ -192,7 +192,7 @@ print_insn_ppi (field_b, info)
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void *stream = info->stream;
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unsigned int nib1, nib2, nib3;
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char *dc = NULL;
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sh_opcode_info *op;
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const sh_opcode_info *op;
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if ((field_b & 0xe800) == 0)
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{
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@ -298,7 +298,7 @@ print_insn_sh (memaddr, info)
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unsigned char nibs[4];
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int status;
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bfd_vma relmask = ~(bfd_vma) 0;
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sh_opcode_info *op;
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const sh_opcode_info *op;
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int target_arch;
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switch (info->mach)
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@ -1,5 +1,5 @@
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/* Disassembly routines for TMS320C30 architecture
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Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
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Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
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Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
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This program is free software; you can redistribute it and/or modify
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@ -663,6 +663,10 @@ cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat)
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float *ieeefloat;
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{
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unsigned long exp, sign, mant;
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union {
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unsigned long l;
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float f;
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} val;
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if (size == 2)
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{
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@ -705,6 +709,7 @@ cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat)
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if (tmsfloat == 0x80000000)
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sign = mant = exp = 0;
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tmsfloat = sign | exp | mant;
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*ieeefloat = *((float *) &tmsfloat);
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val.l = tmsfloat;
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*ieeefloat = val.f;
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return 1;
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}
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@ -1,5 +1,5 @@
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/* Disassemble WDC 65816 instructions.
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Copyright 1995, 1998, 2000, 2001 Free Software Foundation, Inc.
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Copyright 1995, 1998, 2000, 2001, 2002 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -84,7 +84,7 @@ print_insn_w65 (memaddr, info)
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{
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int status = 0;
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unsigned char insn[4];
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register struct opinfo *op;
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const struct opinfo *op;
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int i;
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int X = 0;
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int M = 0;
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Loading…
Reference in a new issue