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2004-04-10  Chris Demetriou  <cgd@broadcom.com>

        * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.

[ sim/testsuite/sim/mips/ChangeLog ]
2004-04-10  Chris Demetriou  <cgd@broadcom.com>

        * fpu64-ps-sb1.s: New file.
        * basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s
        if appropriate.
This commit is contained in:
Chris Demetriou 2004-04-10 07:11:29 +00:00
parent 55dc1ac473
commit 5dbb7b5a1d
5 changed files with 137 additions and 1 deletions
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4
sim/mips/ChangeLog
View file

@ -1,3 +1,7 @@
2004-04-10 Chris Demetriou <cgd@broadcom.com>
* sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.

50
sim/mips/sb1.igen
View file

@ -192,3 +192,53 @@
check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
}
// Paired-Single Extension Instructions
// ------------------------------------
//
// The SB-1 implements several .PS format instructions that are
// extensions to the MIPS64 architecture.
010001,10,3.FMT=6,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.PS
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
*sb1:
{
int fmt = FMT;
check_fpu (SD_);
check_sbx (SD_, instruction_0);
StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
010001,10,3.FMT=6,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.PS
"recip.%s<FMT> f<FD>, f<FS>"
*sb1:
{
int fmt = FMT;
check_fpu (SD_);
check_sbx (SD_, instruction_0);
StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
}
010001,10,3.FMT=6,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.PS
"rsqrt.%s<FMT> f<FD>, f<FS>"
*sb1:
{
int fmt = FMT;
check_fpu (SD_);
check_sbx (SD_, instruction_0);
StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
}
010001,10,3.FMT=6,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.PS
"sqrt.%s<FMT> f<FD>, f<FS>"
*sb1:
{
int fmt = FMT;
check_fpu (SD_);
check_sbx (SD_, instruction_0);
StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
}

6
sim/testsuite/sim/mips/ChangeLog
View file

@ -1,3 +1,9 @@
2004-04-10 Chris Demetriou <cgd@broadcom.com>
* fpu64-ps-sb1.s: New file.
* basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s
if appropriate.
2004-04-10 Chris Demetriou <cgd@broadcom.com>
* fpu64-ps.s: New file.

6
sim/testsuite/sim/mips/basic.exp
View file

@ -36,7 +36,10 @@ proc run_hilo_test {testfile models nops} {
# board really is a simulator (sim tests don't work on real HW).
if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
if {[istarget mipsisa64*-elf]} {
if {[istarget mipsisa64sb1*-elf]} {
set models "sb1"
set submodels "mips1 mips2 mips3 mips4 mips32 mips64"
} elseif {[istarget mipsisa64*-elf]} {
set models "mips32 mips64"
set submodels "mips1 mips2 mips3 mips4"
} elseif {[istarget mipsisa32*-elf]} {
@ -64,4 +67,5 @@ if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
run_hilo_test hilo-hazard-3.s $models 2
run_sim_test fpu64-ps.s $submodels
run_sim_test fpu64-ps-sb1.s $submodels
}

72
sim/testsuite/sim/mips/fpu64-ps-sb1.s Normal file
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@ -0,0 +1,72 @@
# mips test sanity, expected to pass.
# mach: sb1
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.macro check_ps psval, upperval, lowerval
.set push
.set noreorder
cvt.s.pu $f0, \psval # upper
cvt.s.pl $f2, \psval # lower
li.s $f4, \upperval
li.s $f6, \lowerval
c.eq.s $fcc0, $f0, $f4
bc1f $fcc0, _fail
c.eq.s $fcc0, $f2, $f6
bc1f $fcc0, _fail
nop
.set pop
.endm
setup
.set noreorder
.ent DIAG
DIAG:
# make sure that Status.FR, .CU1, and .SBX are set.
mfc0 $2, $12
or $2, $2, (1 << 26) | (1 << 29) | (1 << 16)
mtc0 $2, $12
li.s $f10, 4.0
li.s $f12, 16.0
cvt.ps.s $f20, $f10, $f12 # $f20: u=4.0, l=16.0
li.s $f10, -1.0
li.s $f12, 2.0
cvt.ps.s $f22, $f10, $f12 # $f22: u=-1.0, l=2.0
writemsg "div.ps"
div.ps $f8, $f20, $f22
check_ps $f8, -4.0, 8.0
writemsg "recip.ps"
recip.ps $f8, $f20
check_ps $f8, 0.25, 0.0625
writemsg "rsqrt.ps"
rsqrt.ps $f8, $f20
check_ps $f8, 0.5, 0.25
writemsg "sqrt.ps"
sqrt.ps $f8, $f20
check_ps $f8, 2.0, 4.0
pass
.end DIAG