epiphany/gas: Update expected test results for 0 offset loads
In commit 02a79b89fd some of the load
instructions with a zero offset (where the offset is not mentioned) were
marked as NO-DIS, meaning that the disassembler must display the offset,
even though it is zero.
This change seems a little strange to me as it was only applied to some
loads, not all, and the same change was not applied to the stores.
However, I'm reluctant to revert a specific change to the assembler,
when the output is obviously correct. With this commit then I simply
bring the expected assembler test results into line with what is
actually produced.
gas/ChangeLog:
* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
some load instructions.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
This commit is contained in:
Andrew Burgess
parent
a012b298ba
commit
5d7a901176
4 changed files with 21 additions and 14 deletions
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@ -1,3 +1,10 @@
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
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some load instructions.
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* testsuite/gas/epiphany/allinsn.d: Likewise.
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* testsuite/gas/epiphany/regression.d: Likewise.
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l'
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@ -11,5 +11,5 @@ Disassembly of section \.text:
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0: 2bcc 01ff ldr r1,\[r2,-0x7ff\]
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4: 4c4c 0301 ldr r2,\[r3\],-0x8
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8: 107c 2201 strd r8,\[r4\],\+0x8
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c: 506c 2400 ldrd r10,\[r12\]
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c: 506c 2400 ldrd r10,\[r12,\+0x0\]
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10: 587c 2400 strd r10,\[lr\]
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@ -240,7 +240,7 @@ Disassembly of section .text:
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1d4: 4c8d e580 ldrb r58,\[fp],\+r25
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000001d8 \<ldrbd16\>:
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1d8: 900c 2400 ldrb r12,\[r12]
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1d8: 900c 2400 ldrb r12,\[r12,\+0x0]
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1dc: 6f84 ldrb r3,\[r3,0x7]
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1de: 0204 ldrb r0,\[r0,0x4]
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1e0: 6d8c 2400 ldrb fp,\[fp,\+0x3]
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@ -250,7 +250,7 @@ Disassembly of section .text:
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1ee: 2484 ldrb r1,\[r1,0x1]
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000001f0 \<ldrbd\>:
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1f0: 900c 2400 ldrb r12,\[r12]
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1f0: 900c 2400 ldrb r12,\[r12,\+0x0]
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1f4: 6f8c fcff ldrb r59,\[r59,\+0x7ff]
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1f8: 900c 6c80 ldrb r28,\[r28,\+0x400]
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1fc: 6f8c 6c7f ldrb r27,\[r27,\+0x3ff]
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@ -289,17 +289,17 @@ Disassembly of section .text:
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25c: e1ad 7400 ldrh r31,\[r40],\+r3
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00000260 \<ldrhd16\>:
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260: 902c 2400 ldrh r12,\[r12]
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260: 902c 2400 ldrh r12,\[r12,\+0x0]
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264: 6fa4 ldrh r3,\[r3,0x7]
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266: 0224 ldrh r0,\[r0,0x4]
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268: 6dac 2400 ldrh fp,\[fp,\+0x3]
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26c: b4ac 2400 ldrh sp,\[sp,\+0x1]
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270: c82c 2000 ldrh lr,\[r2]
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270: c82c 2000 ldrh lr,\[r2,\+0x0]
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274: 63a4 ldrh r3,\[r0,0x7]
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276: 0f24 ldrh r0,\[r3,0x6]
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00000278 \<ldrhd\>:
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278: 902c 2400 ldrh r12,\[r12]
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278: 902c 2400 ldrh r12,\[r12,\+0x0]
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27c: 6fac fcff ldrh r59,\[r59,\+0x7ff]
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280: 902c 6c80 ldrh r28,\[r28,\+0x400]
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284: 6fac 6c7f ldrh r27,\[r27,\+0x3ff]
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@ -339,17 +339,17 @@ Disassembly of section .text:
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2e8: 91cd 2080 ldr r12,\[r4],\+fp
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000002ec \<ldrd16\>:
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2ec: 904c 2400 ldr r12,\[r12]
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2ec: 904c 2400 ldr r12,\[r12,\+0x0]
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2f0: 6fc4 ldr r3,\[r3,0x7]
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2f2: 0244 ldr r0,\[r0,0x4]
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2f4: 6dcc 2400 ldr fp,\[fp,\+0x3]
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2f8: b4cc 2400 ldr sp,\[sp,\+0x1]
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2fc: 144c 0400 ldr r0,\[sp]
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2fc: 144c 0400 ldr r0,\[sp,\+0x0]
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300: 87cc 2000 ldr r12,\[r1,\+0x7]
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304: 64cc 2000 ldr fp,\[r1,\+0x1]
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00000308 \<ldrd\>:
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308: 904c 2400 ldr r12,\[r12]
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308: 904c 2400 ldr r12,\[r12,\+0x0]
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30c: 6fcc fcff ldr r59,\[r59,\+0x7ff]
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310: 904c 6c80 ldr r28,\[r28,\+0x400]
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314: 6fcc 6c7f ldr r27,\[r27,\+0x3ff]
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@ -393,7 +393,7 @@ Disassembly of section .text:
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386: 41ed f080 ldrd r58,\[r32],\+fp
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0000038a \<ldrdd16\>:
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38a: 906c 2400 ldrd r12,\[r12]
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38a: 906c 2400 ldrd r12,\[r12,\+0x0]
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38e: 8fe4 ldrd r4,\[r3,0x7]
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390: 0264 ldrd r0,\[r0,0x4]
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392: 0dec 4400 ldrd r16,\[fp,\+0x3]
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@ -403,7 +403,7 @@ Disassembly of section .text:
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3a2: d0ec 2400 ldrd lr,\[r12,\+0x1]
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000003a6 \<ldrdd\>:
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3a6: 906c 2400 ldrd r12,\[r12]
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3a6: 906c 2400 ldrd r12,\[r12,\+0x0]
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3aa: 4fec fcff ldrd r58,\[r59,\+0x7ff]
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3ae: 906c 6c80 ldrd r28,\[r28,\+0x400]
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3b2: 4fec 0c7f ldrd r2,\[r27,\+0x3ff]
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@ -77,7 +77,7 @@ Disassembly of section \.text:
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0000006e \<NEXT\>:
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6e: 8014 strb r4,\[r0\]
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70: e00c e000 ldrb r63,\[r0\]
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70: e00c e000 ldrb r63,\[r0,\+0x0\]
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74: fe3f fc0a sub r63,r63,r4
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78: 0300 beq 7e \<STOREB\>
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7a: 0023 mov r0,0x1
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@ -93,7 +93,7 @@ Disassembly of section \.text:
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00000090 \<STORES\>:
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90: 8034 strh r4,\[r0\]
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92: e02c e000 ldrh r63,\[r0\]
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92: e02c e000 ldrh r63,\[r0,\+0x0\]
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96: fe3f fc0a sub r63,r63,r4
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9a: 0300 beq a0 \<STORES2\>
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9c: 0023 mov r0,0x1
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@ -109,7 +109,7 @@ Disassembly of section \.text:
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000000b2 \<STORE\>:
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b2: 8054 str r4,\[r0\]
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b4: e04c e000 ldr r63,\[r0\]
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b4: e04c e000 ldr r63,\[r0,\+0x0\]
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b8: fe3f fc0a sub r63,r63,r4
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bc: 0300 beq c2 \<STORE2\>
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be: 0023 mov r0,0x1
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