New stuff for SH.
This commit is contained in:
Steve Chamberlain
parent
31568a6f41
commit
594266fc8a
8 changed files with 1445 additions and 0 deletions
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@ -29,6 +29,7 @@ configure.in
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endian.c
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h8300
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h8500
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sh
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z8k
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Do-last:
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38
sim/sh/.Sanitize
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38
sim/sh/.Sanitize
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@ -0,0 +1,38 @@
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# Sanitize.in for devo.
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# $Id$
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#
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# Each directory to survive it's way into a release will need a file
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# like this one called "./.Sanitize". All keyword lines must exist,
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# and must exist in the order specified by this file. Each directory
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# in the tree will be processed, top down, in the following order.
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# Hash started lines like this one are comments and will be deleted
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# before anything else is done. Blank lines will also be squashed
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# out.
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# The lines between the "Do-first:" line and the "Things-to-keep:"
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# line are executed as a /bin/sh shell script before anything else is
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# done in this
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Do-first:
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# All files listed between the "Things-to-keep:" line and the
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# "Files-to-sed:" line will be kept. All other files will be removed.
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# Directories listed in this section will have their own Sanitize
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# called. Directories not listed will be removed in their entirety
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# with rm -rf.
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Things-to-keep:
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ChangeLog
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Makefile.in
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configure.in
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interp.c
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gencode.c
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run.c
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Do-last:
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# End of file.
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4
sim/sh/ChangeLog
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4
sim/sh/ChangeLog
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@ -0,0 +1,4 @@
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Mon Apr 26 18:01:10 1993 Steve Chamberlain (sac@thepub.cygnus.com)
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* created
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176
sim/sh/Makefile.in
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176
sim/sh/Makefile.in
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@ -0,0 +1,176 @@
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# Makefile template for Configure for the h8300sim library.
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# Copyright (C) 1990, 1991, 1992 Free Software Foundation, Inc.
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# Written by Cygnus Support.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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srcdir = .
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prefix = /usr/local
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program_transform_name =
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exec_prefix = $(prefix)
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bindir = $(exec_prefix)/bin
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libdir = $(exec_prefix)/lib
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datadir = $(prefix)/lib
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mandir = $(prefix)/man
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man1dir = $(mandir)/man1
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man2dir = $(mandir)/man2
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man3dir = $(mandir)/man3
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man4dir = $(mandir)/man4
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man5dir = $(mandir)/man5
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man6dir = $(mandir)/man6
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man7dir = $(mandir)/man7
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man8dir = $(mandir)/man8
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man9dir = $(mandir)/man9
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infodir = $(prefix)/info
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includedir = $(prefix)/include
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oldincludedir =
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docdir = $(srcdir)/doc
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SHELL = /bin/sh
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INSTALL = install -c
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INSTALL_PROGRAM = $(INSTALL)
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INSTALL_DATA = $(INSTALL)
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AR = ar
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AR_FLAGS = qc
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CFLAGS = -g
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BISON = bison
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MAKEINFO = makeinfo
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RANLIB = ranlib
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INCDIR = $(srcdir)/../../include
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CSEARCH = -I. -I$(srcdir) -I$(INCDIR) -I$(srcdir)/../../bfd
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DEP = mkdep
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#### host, target, and site specific Makefile frags come in here.
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all: run
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run: interp.o run.o table.o
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$(CC) -o run interp.o table.o run.o ../../bfd/libbfd.a ../../libiberty/libiberty.a
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interp.o:interp.c code.c table.c
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run.o:run.c
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code.c:gencode
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./gencode -x >code.c
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indent code.c
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table.c:gencode
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./gencode -s >table.c
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indent table.c
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gencode:gencode.c
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cc -o gencode -g gencode.c
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#### host and target dependent Makefile fragments come in here.
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###
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FLAGS_TO_PASS = \
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"against=$(against)" \
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"AR=$(AR)" \
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"AR_FLAGS=$(AR_FLAGS)" \
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"CC=$(CC)" \
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"CFLAGS=$(CFLAGS)" \
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"RANLIB=$(RANLIB)" \
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"MAKEINFO=$(MAKEINFO)" \
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"INSTALL=$(INSTALL)" \
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"INSTALL_DATA=$(INSTALL_DATA)" \
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"INSTALL_PROGRAM=$(INSTALL_PROGRAM)" \
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"BISON=$(BISON)"
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.c.o:
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$(CC) -c $(CFLAGS) $(HDEFINES) $(TDEFINES) $(CSEARCH) $(CSWITCHES) $<
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.NOEXPORT:
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check:
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info:
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clean-info:
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install-info:
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# HDEPFILES comes from the host config; TDEPFILES from the target config.
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tags etags: TAGS
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TAGS: force
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etags $(INCDIR)/*.h $(srcdir)/*.h $(srcdir)/*.c
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clean:
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rm -f *.[oa] *~ core *.E *.p *.ip aout-params.h gen-aout
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clobber realclean: clean
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rm -f libbfd.a TAGS
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# Mark everything as depending on config.status, since the timestamp on
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# sysdep.h might actually move backwards if we reconfig and relink it
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# to a different hosts/h-xxx.h file. This will force a recompile anyway.
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RECONFIG = config.status
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# This target should be invoked before building a new release.
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# 'VERSION' file must be present and contain a string of the form "x.y"
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#
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roll:
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@V=`cat VERSION` ; \
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MAJ=`sed 's/\..*//' VERSION` ; \
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MIN=`sed 's/.*\.//' VERSION` ; \
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V=$$MAJ.`expr $$MIN + 1` ; \
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rm -f VERSION ; \
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echo $$V >VERSION ; \
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echo Version $$V
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# Dummy target to force execution of dependent targets.
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#
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force:
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install:
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-parent=`echo $(bindir)|sed -e 's@/[^/]*$$@@'`; \
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if [ -d $$parent ] ; then true ; else mkdir $$parent ; fi
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-if [ -d $(bindir) ] ; then true ; else mkdir $(bindir) ; fi
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-parent=`echo $(man1dir)|sed -e 's@/[^/]*$$@@'`; \
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if [ -d $$parent ] ; then true ; else mkdir $$parent ; fi
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-if [ -d $(man1dir) ] ; then true ; else mkdir $(man1dir) ; fi
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-n=`t='$(program_transform_name)'; echo run | sed -e "" $$t`; \
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$(INSTALL_PROGRAM) run $(bindir)/$$n; \
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$(M_INSTALL)
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Makefile: $(srcdir)/Makefile.in $(host_makefile_frag) $(target_makefile_frag)
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$(SHELL) ./config.status
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dep: $(CFILES)
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mkdep $(CFLAGS) $?
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# What appears below is generated by a hacked mkdep using gcc -MM.
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# DO NOT DELETE THIS LINE -- mkdep uses it.
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# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
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# IF YOU PUT ANYTHING HERE IT WILL GO AWAY
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33
sim/sh/configure.in
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33
sim/sh/configure.in
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@ -0,0 +1,33 @@
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# This file is a shell script that supplies the information necessary
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# to tailor a template configure script into the configure script
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# appropriate for this directory. For more information, check any
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# existing configure script.
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srctrigger=compile.c
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srcname="shsim"
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# per-host:
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. ${srcdir}/../../bfd/configure.host
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# Set up to make a link between the host's include file and "sysdep.h".
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files="../../bfd/hosts/${my_host}.h"
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links="sysdep.h"
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if [ ! -f ${srcdir}/${files} ] ; then
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if [ -n "${my_host}" ] ; then
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echo '***' No file ${srcdir}/${files} 1>&2
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fi
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echo '***' ${srcname} does not support host ${host} 1>&2
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exit 1
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fi
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host_makefile_frag=
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if [ -f ${srcdir}/../../bfd/config/${my_host}.mh ] ; then
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host_makefile_frag=../../bfd/config/${my_host}.mh
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fi
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# per-target:
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703
sim/sh/gencode.c
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703
sim/sh/gencode.c
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@ -0,0 +1,703 @@
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/* Simulator/Opcode generator for the Hitachi Super-H architecture.
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Written by Steve Chamberlain of Cygnus Support.
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sac@cygnus.com
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This file is part of SH sim
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THIS SOFTWARE IS NOT COPYRIGHTED
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Cygnus offers the following for use in the public domain. Cygnus
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makes no warranty with regard to the software or it's performance
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and the user accepts the software "AS IS" with all faults.
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CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
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THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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/* This program generates the opcode table for the assembler and
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the simulator code
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-t prints a pretty table for the assembler manual
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-s generates the simulator code jump table
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-x generates the simulator code switch statement
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default generates the opcode tables
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*/
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typedef struct
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{
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char *name;
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char *code;
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char *stuff[10];
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int index;
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}
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op;
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op tab[] =
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{
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{"add #<imm>,<REG_N>", "0111nnnni8*1....", "R[n] += SEXT(i);"},
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{"add <REG_M>,<REG_N>", "0011nnnnmmmm1100", "R[n] += R[m];"},
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{"addc <REG_M>,<REG_N>", "0011nnnnmmmm1110", "ult = R[n]; R[n] += (R[m]+T); T = ult>R[n];"},
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{"addv <REG_M>,<REG_N>", "0011nnnnmmmm1111",
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"long ans;",
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"ans = R[n] + R[m];",
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"T = ((~R[n] & R[m] & ans) | (R[n] & R[m] & ~ans)) >>31;",
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"R[n] = ans;"},
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{"and #<imm>,R0", "11001001i8*1....", "R0&=i;"},
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{"and <REG_M>,<REG_N>", "0010nnnnmmmm1001", "R[n]&=R[m];"},
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{"and.b #<imm>,@(R0,GBR)", "11001101i8*1....", "WBAT(GBR+R0, RBAT(GBR+R0) & i);"},
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{"bf <bdisp8>", "10001011i8p1....", "if(T==0) {PC+=(SEXT(i)<<1)+2;C+=2;}"},
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{"bra <bdisp12>", "1010i12.........", "ult = PC; PC=PC+(i<<1)+2;SL(ult+2);"},
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{"bsr <bdisp12>", "1011i12.........", "PR = PC; PC=PC+(i<<1)+2;SL(PR+2);"},
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{"bt <bdisp8>", "10001001i8p1....", "if(T==1) {PC+=(SEXT(i)<<1)+2;C+=2;}"},
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{"clrmac", "0000000000101000", "MACH = MACL = 0;"},
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{"clrt", "0000000000001000", "T= 0;"},
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{"cmp/eq #<imm>,R0", "10001000i8*1....", "T = R0 == SEXT(i);"},
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{"cmp/eq <REG_M>,<REG_N>", "0011nnnnmmmm0000", "T=R[n]==R[m];"},
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{"cmp/ge <REG_M>,<REG_N>", "0011nnnnmmmm0011", "T=R[n]>=R[m];"},
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{"cmp/gt <REG_M>,<REG_N>", "0011nnnnmmmm0111", "T=R[n]>R[m];"},
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{"cmp/hi <REG_M>,<REG_N>", "0011nnnnmmmm0110", "T=UR[n]>UR[m];"},
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{"cmp/hs <REG_M>,<REG_N>", "0011nnnnmmmm0010", "T=UR[n]>=UR[m];"},
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{"cmp/pl <REG_N>", "0100nnnn00010101", "T = R[n]>0;"},
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{"cmp/pz <REG_N>", "0100nnnn00010001", "T = R[n]>=0;"},
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{"cmp/str <REG_M>,<REG_N>", "0010nnnnmmmm1100", "ult = R[n] ^ R[m]; T=((ult&0xff000000)==0) |((ult&0xff0000)==0) |((ult&0xff00)==0) |((ult&0xff)==0); "},
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{"div0s <REG_M>,<REG_N>", "0010nnnnmmmm0111", "Q=R[n]<0; M=R[m]<0; T=M!=Q;;"},
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{"div0u", "0000000000011001", "M=Q=T=0;"},
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{"div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100", "T=div1(R,n,m,T);"},
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{"exts.b <REG_M>,<REG_N>", "0110nnnnmmmm1110", "R[n] = SEXT(R[m]);"},
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{"exts.w <REG_M>,<REG_N>", "0110nnnnmmmm1111", "R[n] = SEXTW(R[m]);"},
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{"extu.b <REG_M>,<REG_N>", "0110nnnnmmmm1100", "R[n] = R[m] & 0xff;"},
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{"extu.w <REG_M>,<REG_N>", "0110nnnnmmmm1101", "R[n] = R[m] & 0xffff;"},
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{"jmp @<REG_N>", "0100nnnn00101011", "ult = PC; PC=R[n]-2; SL(ult+2);"},
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{"jsr @<REG_N>", "0100nnnn00001011", "PR = PC; PC=R[n]-2; SL(PR+2);"},
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{"ldc <REG_N>,GBR", "0100nnnn00011110", "GBR=R[n];"},
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{"ldc <REG_N>,SR", "0100nnnn00001110", "SET_SR(R[n]);"},
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{"ldc <REG_N>,VBR", "0100nnnn00101110", "VBR=R[n];"},
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{"ldc.l @<REG_N>+,GBR", "0100nnnn00010111", "GBR=RLAT(R[n]);R[n]+=4;;"},
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{"ldc.l @<REG_N>+,SR", "0100nnnn00000111", "SET_SR(RLAT(R[n]));R[n]+=4;;"},
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{"ldc.l @<REG_N>+,VBR", "0100nnnn00100111", "VBR=RLAT(R[n]);R[n]+=4;;"},
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{"lds <REG_N>,MACH", "0100nnnn00001010", "MACH = SEXT(R[n]);"},
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{"lds <REG_N>,MACL", "0100nnnn00011010", "MACL= R[n];"},
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{"lds <REG_N>,PR", "0100nnnn00101010", "PR = R[n];"},
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{"lds.l @<REG_N>+,MACH", "0100nnnn00000110", "MACH = SEXT(RLAT(R[n]));R[n]+=4;"},
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{"lds.l @<REG_N>+,MACL", "0100nnnn00010110", "MACL = RLAT(R[n]);R[n]+=4;"},
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{"lds.l @<REG_N>+,PR", "0100nnnn00100110", "PR = RLAT(R[n]);R[n]+=4;;"},
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{"mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111", "abort();"},
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{"mov #<imm>,<REG_N>", "1110nnnni8*1....", "R[n] = SEXT(i);"},
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{"mov <REG_M>,<REG_N>", "0110nnnnmmmm0011", "R[n] = R[m];"},
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{"mov.b <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0100", "WBAT(R[n]+R0, R[m]);"},
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{"mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100", "R[n]--; WBAT(R[n], R[m]);"},
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{"mov.b <REG_M>,@<REG_N>", "0010nnnnmmmm0000", "WBAT(R[n], R[m]);"},
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{"mov.b @(<disp>,<REG_M>),R0", "10000100mmmmi4*1", "R0=RBAT(i+R[m]);"},
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{"mov.b @(<disp>,GBR),R0", "11000100i8*1....", "R0=RBAT(i+GBR);"},
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{"mov.b @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1100", "R[n]=RBAT(R0+R[m]);"},
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{"mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100", "R[n] = RBAT(R[m]);R[m]++;"},
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{"mov.b @<REG_M>,<REG_N>", "0110nnnnmmmm0000", "R[n]=RBAT(R[m]);"},
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{"mov.b R0,@(<disp>,<REG_M>)", "10000000mmmmi4*1", "R0=RBAT(i+R[m]);"},
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{"mov.b R0,@(<disp>,GBR)", "11000000i8*1....", "R0 = RBAT(i+GBR);"},
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{"mov.l <REG_M>,@(<disp>,<REG_N>)", "0001nnnnmmmmi4*4", "WLAT(i+R[n],R[m]);"},
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{"mov.l <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0110", "WLAT(R0+R[n],R[m]);"},
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{"mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110", "R[n]-=4;WLAT(R[n],R[m]);"},
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{"mov.l <REG_M>,@<REG_N>", "0010nnnnmmmm0010", "WLAT(R[n], R[m]);"},
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{"mov.l @(<disp>,<REG_N>),<REG_M>", "0101nnnnmmmmi4*4", "R[m]=RLAT(i+R[n]);"},
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{"mov.l @(<disp>,GBR),R0", "11000110i4*4", "R0=RLAT(i+GBR);"},
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{"mov.l @(<disp>,PC),<REG_N>", "1101nnnni8p4....", "R[n]=RLAT(i+4+PC);"},
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{"mov.l @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1110", "R[n]=RLAT(R0+R[m]);"},
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{"mov.l @<REG_M>+,<REG_N>", "0110nnnnmmmm0110", "R[n]=RLAT(R[m]);R[m]+=4;"},
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{"mov.l @<REG_M>,<REG_N>", "0110nnnnmmmm0010", "R[n]=RLAT(R[m]);"},
|
||||
{"mov.l R0,@(<disp>,GBR)", "11000010i8*4....", "R0=RLAT(R0+GBR);"},
|
||||
{"mov.w <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0101", "WWAT(R0+R[n],R[m]);"},
|
||||
{"mov.w <REG_M>,@-<REG_N>", "0010nnnnmmmm0101", "R[n]-=2;WWAT(R[n],R[m]);"},
|
||||
{"mov.w <REG_M>,@<REG_N>", "0010nnnnmmmm0001", "WWAT(R[n],R[m]);"},
|
||||
{"mov.w @(<disp>,<REG_M>),R0", "10000101mmmmi4*2", "R0=RSWAT(i+R[m]);"},
|
||||
{"mov.w @(<disp>,GBR),R0", "11000101i8*2....", "R0=RSWAT(i+GBR);"},
|
||||
{"mov.w @(<disp>,PC),<REG_N>", "1001nnnni8p2....", "R[n]=RSWAT(PC+i+4);"},
|
||||
{"mov.w @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1101", "R[n]=RSWAT(R0+R[m]);"},
|
||||
{"mov.w @<REG_M>+,<REG_N>", "0110nnnnmmmm0101", "R[n]=RSWAT(R[m]);R[m]+=2;"},
|
||||
{"mov.w @<REG_M>,<REG_N>", "0110nnnnmmmm0001", "R[n]=RSWAT(R[m]);"},
|
||||
{"mov.w R0,@(<disp>,<REG_M>)", "10000001mmmmi4*2", "R0=RSWAT(i+R[m]);"},
|
||||
{"mov.w R0,@(<disp>,GBR)", "11000001i8*2....", "R0=RSWAT(i+GBR);"},
|
||||
{"mova @(<disp>,PC),R0", "11000111i8p4....", "R0=i+4+PC;"},
|
||||
{"movt <REG_N>", "0000nnnn00101001", "R[n]=T;"},
|
||||
{"muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
|
||||
"MACL=((long)(short)R[n])*((long)(short)R[m]);"},
|
||||
{"mulu <REG_M>,<REG_N>","0010nnnnmmmm1110", "MACL=((unsigned long)(unsigned short)R[n])*((unsigned long)(unsigned short)R[m]);"},
|
||||
{"neg <REG_M>,<REG_N>", "0110nnnnmmmm1011", "R[n] = - R[m];"},
|
||||
{"negc <REG_M>,<REG_N>", "0110nnnnmmmm1010", "ult=0-R[m];R[n]=ult-T;T=SBIT(R[n])!=SBIT(ult);"},
|
||||
{"nop", "0000000000001001", ""},
|
||||
{"not <REG_M>,<REG_N>", "0110nnnnmmmm0111", "R[n]=~R[m];"},
|
||||
{"or #<imm>,R0", "11001011i8*1....", "R0|=i;"},
|
||||
{"or <REG_M>,<REG_N>", "0010nnnnmmmm1011", "R[n]|=R[m];"},
|
||||
{"or.b #<imm>,@(R0,GBR)", "11001111i8*1....", "WBAT(R0+GBR,RBAT(R0+GBR)|i);"},
|
||||
{"rotcl <REG_N>", "0100nnnn00100100", "ult = R[n] <0;R[n] = (R[n]<<1)|T;T=ult;"},
|
||||
{"rotcr <REG_N>", "0100nnnn00100101", "ult = R[n]&1;R[n]=(UR[n]>>1)|(T<<31);T=ult;"},
|
||||
{"rotl <REG_N>", "0100nnnn00000100", "T=R[n]<0;R[n]<<=1;R[n]|=T;"},
|
||||
{"rotr <REG_N>", "0100nnnn00000101", "T=R[n]&1;UR[n]>>=1;R[n]|=(T<<31);"},
|
||||
{"rte", "0000000000101011", "abort();"},
|
||||
{"rts", "0000000000001011", "ult=PC;PC=PR+2;SL(ult+2);"},
|
||||
{"sett", "0000000000011000", "T=1;"},
|
||||
{"shal <REG_N>", "0100nnnn00100000", "T=R[n]<0; R[n]<<=1;"},
|
||||
{"shar <REG_N>", "0100nnnn00100001", "T=R[n]&1; R[n]>>=1;"},
|
||||
{"shll <REG_N>", "0100nnnn00000000", "T=R[n]<0; R[n]<<=1;"},
|
||||
{"shll16 <REG_N>", "0100nnnn00101000", "R[n]<<=16;"},
|
||||
{"shll2 <REG_N>", "0100nnnn00001000", "R[n]<<=2;"},
|
||||
{"shll8 <REG_N>", "0100nnnn00011000", "R[n]<<=8;"},
|
||||
{"shlr <REG_N>", "0100nnnn00000001", "T=R[n]&1;R[n]=UR[n]>>1;"},
|
||||
{"shlr16 <REG_N>", "0100nnnn00101001", "R[n]=UR[n]>>16;"},
|
||||
{"shlr2 <REG_N>", "0100nnnn00001001", "R[n]=UR[n]>>2;"},
|
||||
{"shlr8 <REG_N>", "0100nnnn00011001", "R[n]=UR[n]>>8;"},
|
||||
{"sleep", "0000000000011011", "abort();"},
|
||||
{"stc GBR,<REG_N>", "0000nnnn00010010", "R[n]=GBR;"},
|
||||
{"stc SR,<REG_N>", "0000nnnn00000010", "R[n]=GET_SR();"},
|
||||
{"stc VBR,<REG_N>", "0000nnnn00100010", "R[n]=VBR;"},
|
||||
{"stc.l GBR,@-<REG_N>", "0100nnnn00010011", "R[n]-=4;WLAT(R[n],GBR);;"},
|
||||
{"stc.l SR,@-<REG_N>", "0100nnnn00000011", "R[n]-=4;WLAT(R[n],GET_SR());"},
|
||||
{"stc.l VBR,@-<REG_N>", "0100nnnn00100011", "R[n]-=4;WLAT(R[n],VBR);"},
|
||||
{"sts MACH,<REG_N>", "0000nnnn00001010", "R[n]=MACH;"},
|
||||
{"sts MACL,<REG_N>", "0000nnnn00011010", "R[n]=MACL;"},
|
||||
{"sts PR,<REG_N>", "0000nnnn00101010", "R[n]=PR;"},
|
||||
{"sts.l MACH,@-<REG_N>", "0100nnnn00000010", "R[n]-=4;WLAT(R[n],MACH);"},
|
||||
{"sts.l MACL,@-<REG_N>", "0100nnnn00010010", "R[n]-=4;WLAT(R[n],MACL);"},
|
||||
{"sts.l PR,@-<REG_N>", "0100nnnn00100010", "R[n]-=4;WLAT(R[n],PR);"},
|
||||
{"sub <REG_M>,<REG_N>", "0011nnnnmmmm1000", "R[n]-=R[m];"},
|
||||
{"subc <REG_M>,<REG_N>", "0011nnnnmmmm1010", "ult = R[n];R[n]-=R[m]+T;T=ult<UR[n];"},
|
||||
{"subv <REG_M>,<REG_N>", "0011nnnnmmmm1011", "abort();"},
|
||||
{"swap.b <REG_M>,<REG_N>", "0110nnnnmmmm1000", "R[n]=((R[m]<<8)&0xff00)|((R[m]>>8)&0x00ff);"},
|
||||
{"swap.w <REG_M>,<REG_N>", "0110nnnnmmmm1001", "R[n]=((R[m]<<16)&0xffff0000)|((R[m]>>16)&0x00ffff);"},
|
||||
{"tas.b @<REG_N>", "0100nnnn00011011", "ult=RBAT(R[n]);T=ult==0;WBAT(R[n],ult|0x80);"},
|
||||
{"trapa #<imm>", "11000011i8*1....", "trap(i,R);"},
|
||||
{"tst #<imm>,R0", "11001000i8*1....", "T=(R0&i)==0;"},
|
||||
{"tst <REG_M>,<REG_N>", "0010nnnnmmmm1000", "T=(R[n]&R[m])==0;"},
|
||||
{"tst.b #<imm>,@(R0,GBR)", "11001100i8*1....", "T=(RBAT(GBR+R0)&i)==0;"},
|
||||
{"xor #<imm>,R0", "11001010i8*1....", "R0^=i;"},
|
||||
{"xor <REG_M>,<REG_N>", "0010nnnnmmmm1010", "R[n]^=R[m];"},
|
||||
{"xor.b #<imm>,@(R0,GBR)", "11001110i8*1....", "ult=RBAT(GBR+R0);ult^=i;WBAT(GBR+R0,ult);"},
|
||||
{"xtrct <REG_M>,<REG_N>", "0010nnnnmmmm1101", "R[n]=((R[n]>>16)&0xffff)|((R[m]<<16)&0xffff0000);"},
|
||||
|
||||
#if 0
|
||||
{"mul.l <REG_M>,<REG_N>","0000nnnnmmmm0111","/* mull */"},
|
||||
{"dmuls.l <REG_M>,<REG_N>","0011nnnnmmmm1101","/* dmuls.l */"},
|
||||
{"dmulu.l <REG_M>,<REG_N>","0011nnnnmmmm0101",""},
|
||||
{"mac.l @<REG_M>+,@<REG_N>+","0000nnnnmmmm1111",""},
|
||||
{"bt/s <bdisp8>","10001101i8p1....",""},
|
||||
{"bf/s <bdisp8>","10001111i8p1....",""},
|
||||
{"dt <REG_N>","0100nnnn00010000",""},
|
||||
{"braf @<REG_N>","0000nnnn00100011",""},
|
||||
{"bsrf @<REG_N>","0000nnnn00000011",""},
|
||||
{"mulu <REG_M>,<REG_N>","0010nnnnmmmm1110",""},
|
||||
{"muls <REG_M>,<REG_N>","0010nnnnmmmm1111",""},
|
||||
#endif
|
||||
|
||||
{0, 0}};
|
||||
|
||||
/* Tables of things to put into enums for sh-opc.h */
|
||||
static char *nibble_type_list[] =
|
||||
{
|
||||
"HEX_0",
|
||||
"HEX_1",
|
||||
"HEX_2",
|
||||
"HEX_3",
|
||||
"HEX_4",
|
||||
"HEX_5",
|
||||
"HEX_6",
|
||||
"HEX_7",
|
||||
"HEX_8",
|
||||
"HEX_9",
|
||||
"HEX_A",
|
||||
"HEX_B",
|
||||
"HEX_C",
|
||||
"HEX_D",
|
||||
"HEX_E",
|
||||
"HEX_F",
|
||||
"REG_N",
|
||||
"REG_M",
|
||||
"BRANCH_12",
|
||||
"BRANCH_8",
|
||||
"DISP_8",
|
||||
"DISP_4",
|
||||
"IMM_4",
|
||||
"IMM_4BY2",
|
||||
"IMM_4BY4",
|
||||
"PCRELIMM_8BY2",
|
||||
"PCRELIMM_8BY4",
|
||||
"IMM_8",
|
||||
"IMM_8BY2",
|
||||
"IMM_8BY4",
|
||||
0
|
||||
};
|
||||
static
|
||||
char *arg_type_list[] =
|
||||
{
|
||||
"A_END",
|
||||
"A_BDISP12",
|
||||
"A_BDISP8",
|
||||
"A_DEC_M",
|
||||
"A_DEC_N",
|
||||
"A_DISP_GBR",
|
||||
"A_DISP_PC",
|
||||
"A_DISP_REG_M",
|
||||
"A_DISP_REG_N",
|
||||
"A_GBR",
|
||||
"A_IMM",
|
||||
"A_INC_M",
|
||||
"A_INC_N",
|
||||
"A_IND_M",
|
||||
"A_IND_N",
|
||||
"A_IND_R0_REG_M",
|
||||
"A_IND_R0_REG_N",
|
||||
"A_MACH",
|
||||
"A_MACL",
|
||||
"A_PR",
|
||||
"A_R0",
|
||||
"A_R0_GBR",
|
||||
"A_REG_M",
|
||||
"A_REG_N",
|
||||
"A_SR",
|
||||
"A_VBR",
|
||||
0,
|
||||
};
|
||||
|
||||
static void
|
||||
make_enum_list (name, s)
|
||||
char *name;
|
||||
char **s;
|
||||
{
|
||||
int i = 1;
|
||||
printf ("typedef enum {\n");
|
||||
while (*s)
|
||||
{
|
||||
printf ("\t%s,\n", *s, i);
|
||||
s++;
|
||||
i++;
|
||||
}
|
||||
printf ("} %s;\n", name);
|
||||
}
|
||||
|
||||
static void
|
||||
gengastab ()
|
||||
{
|
||||
op *p;
|
||||
sorttab ();
|
||||
for (p = tab; p->name; p++)
|
||||
{
|
||||
printf ("%s %-30s\n", p->code, p->name);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
genopc ()
|
||||
{
|
||||
op *p;
|
||||
make_enum_list ("sh_nibble_type", nibble_type_list);
|
||||
make_enum_list ("sh_arg_type", arg_type_list);
|
||||
|
||||
printf ("typedef struct {\n");
|
||||
printf ("char *name;\n");
|
||||
printf ("sh_arg_type arg[3];\n");
|
||||
printf ("sh_nibble_type nibbles[4];\n");
|
||||
printf ("} sh_opcode_info;\n");
|
||||
printf ("#ifdef DEFINE_TABLE\n");
|
||||
printf ("sh_opcode_info sh_table[]={\n");
|
||||
for (p = tab; p->name; p++)
|
||||
{
|
||||
printf ("\n\/\* %s %-20s*/", p->code, p->name);
|
||||
think (p);
|
||||
}
|
||||
printf ("0};\n");
|
||||
printf ("#endif\n");
|
||||
}
|
||||
|
||||
|
||||
m (ptr, a, rep)
|
||||
char **ptr;
|
||||
char *a;
|
||||
char *rep;
|
||||
{
|
||||
int l = strlen (a);
|
||||
if (strncmp (*ptr, a, l) == 0)
|
||||
{
|
||||
printf ("%s", rep);
|
||||
*ptr += l;
|
||||
if (**ptr)
|
||||
printf (",");
|
||||
}
|
||||
}
|
||||
|
||||
think (o)
|
||||
op *o;
|
||||
{
|
||||
int t;
|
||||
char *n;
|
||||
char *p;
|
||||
|
||||
printf ("{\"");
|
||||
n = o->name;
|
||||
while (*n && *n != ' ')
|
||||
{
|
||||
printf ("%c", *n);
|
||||
n++;
|
||||
}
|
||||
printf ("\",{");
|
||||
|
||||
p = n;
|
||||
|
||||
if (!*p)
|
||||
{
|
||||
printf ("0");
|
||||
}
|
||||
while (*p)
|
||||
{
|
||||
while (*p == ',' || *p == ' ')
|
||||
p++;
|
||||
m (&p, "#<imm>", "A_IMM");
|
||||
m (&p, "R0", "A_R0");
|
||||
m (&p, "<REG_N>", "A_REG_N");
|
||||
m (&p, "@<REG_N>+", "A_INC_N");
|
||||
m (&p, "@<REG_N>", "A_IND_N");
|
||||
m (&p, "@-<REG_N>", "A_DEC_N");
|
||||
m (&p, "<REG_M>", " A_REG_M");
|
||||
m (&p, "@<REG_M>+", "A_INC_M");
|
||||
m (&p, "@<REG_M>", "A_IND_M");
|
||||
m (&p, "@-<REG_M>", "A_DEC_M");
|
||||
m (&p, "@(<disp>,PC)", "A_DISP_PC");
|
||||
m (&p, "@(<disp>,<REG_M>)", "A_DISP_REG_M");
|
||||
m (&p, "@(<disp>,<REG_N>)", "A_DISP_REG_N");
|
||||
m (&p, "@(R0,<REG_N>)", "A_IND_R0_REG_N");
|
||||
m (&p, "@(R0,<REG_M>)", "A_IND_R0_REG_M");
|
||||
m (&p, "@(<disp>,GBR)", "A_DISP_GBR");
|
||||
m (&p, "@(R0,GBR)", "A_R0_GBR");
|
||||
m (&p, "<bdisp8>", "A_BDISP8");
|
||||
m (&p, "<bdisp12>", "A_BDISP12");
|
||||
m (&p, "SR", "A_SR");
|
||||
m (&p, "GBR", "A_GBR");
|
||||
m (&p, "VBR", "A_VBR");
|
||||
m (&p, "MACH", "A_MACH");
|
||||
m (&p, "MACL", "A_MACL");
|
||||
m (&p, "PR", "A_PR");
|
||||
|
||||
}
|
||||
printf ("},{");
|
||||
|
||||
p = o->code;
|
||||
while (*p)
|
||||
{
|
||||
m (&p, "0000", "HEX_0");
|
||||
m (&p, "0001", "HEX_1");
|
||||
m (&p, "0010", "HEX_2");
|
||||
m (&p, "0011", "HEX_3");
|
||||
m (&p, "0100", "HEX_4");
|
||||
m (&p, "0101", "HEX_5");
|
||||
m (&p, "0110", "HEX_6");
|
||||
m (&p, "0111", "HEX_7");
|
||||
|
||||
m (&p, "1000", "HEX_8");
|
||||
m (&p, "1001", "HEX_9");
|
||||
m (&p, "1010", "HEX_A");
|
||||
m (&p, "1011", "HEX_B");
|
||||
m (&p, "1100", "HEX_C");
|
||||
m (&p, "1101", "HEX_D");
|
||||
m (&p, "1110", "HEX_E");
|
||||
m (&p, "1111", "HEX_F");
|
||||
m (&p, "i8*1....", "IMM_8");
|
||||
m (&p, "i4*1", "IMM_4");
|
||||
m (&p, "i8p4....", "PCRELIMM_8BY4");
|
||||
m (&p, "i8p2....", "PCRELIMM_8BY2");
|
||||
m (&p, "i8*2....", "IMM_8BY2");
|
||||
m (&p, "i4*2", "IMM_4BY2");
|
||||
m (&p, "i8*4....", "IMM_8BY4");
|
||||
m (&p, "i4*4", "IMM_4BY4");
|
||||
m (&p, "i12.........", "BRANCH_12");
|
||||
m (&p, "i8p1....", "BRANCH_8");
|
||||
m (&p, "nnnn", "REG_N");
|
||||
m (&p, "mmmm", "REG_M");
|
||||
|
||||
}
|
||||
printf ("}},\n");
|
||||
}
|
||||
|
||||
qfunc (a, b)
|
||||
op *a;
|
||||
op *b;
|
||||
{
|
||||
char bufa[9];
|
||||
char bufb[9];
|
||||
memcpy (bufa, a->code, 4);
|
||||
memcpy (bufa + 4, a->code + 12, 4);
|
||||
bufa[8] = 0;
|
||||
|
||||
memcpy (bufb, b->code, 4);
|
||||
memcpy (bufb + 4, b->code + 12, 4);
|
||||
bufb[8] = 0;
|
||||
return (strcmp (bufa, bufb));
|
||||
}
|
||||
|
||||
|
||||
sorttab ()
|
||||
{
|
||||
op *p = tab;
|
||||
|
||||
int len = 0;
|
||||
|
||||
while (p->name)
|
||||
{
|
||||
p++;
|
||||
len++;
|
||||
}
|
||||
|
||||
qsort (tab, len, sizeof (*p), qfunc);
|
||||
|
||||
}
|
||||
|
||||
/* Convert a string of 4 binary digits into an int */
|
||||
|
||||
static
|
||||
int
|
||||
bton (s)
|
||||
char *s;
|
||||
|
||||
{
|
||||
int n = 0;
|
||||
int v = 8;
|
||||
while (v)
|
||||
{
|
||||
if (*s == '1')
|
||||
n |= v;
|
||||
v >>= 1;
|
||||
s++;
|
||||
}
|
||||
return n;
|
||||
}
|
||||
|
||||
static char table[1 << 16];
|
||||
|
||||
/* Take an opcode expand all varying fields in it out and fill all the
|
||||
right entries in 'table' with the opcode index*/
|
||||
|
||||
expand_opcode (shift, val, i, s)
|
||||
char *s;
|
||||
{
|
||||
int j;
|
||||
|
||||
if (*s == 0)
|
||||
{
|
||||
table[val] = i;
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (s[0])
|
||||
{
|
||||
|
||||
case '0':
|
||||
case '1':
|
||||
{
|
||||
|
||||
int n = bton (s);
|
||||
if (n >= 0)
|
||||
{
|
||||
expand_opcode (shift - 4, val | (n << shift), i, s + 4);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 'n':
|
||||
case 'm':
|
||||
for (j = 0; j < 16; j++)
|
||||
{
|
||||
expand_opcode (shift - 4, val | (j << shift), i, s + 4);
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
for (j = 0; j < (1 << (shift + 4)); j++)
|
||||
{
|
||||
table[val | j] = i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Print the jump table used to index an opcode into a switch
|
||||
statement entry */
|
||||
static void
|
||||
|
||||
dumptable ()
|
||||
{
|
||||
int lump = 256;
|
||||
int online = 16;
|
||||
|
||||
int i = 0;
|
||||
|
||||
while (i < 1 << 16)
|
||||
{
|
||||
int j = 0;
|
||||
int nc = 0;
|
||||
|
||||
printf ("unsigned char sh_jump_table%x[%d]={\n", i, lump);
|
||||
|
||||
while (j < lump)
|
||||
{
|
||||
int k = 0;
|
||||
while (k < online)
|
||||
{
|
||||
printf ("%2d", table[i + j + k]);
|
||||
if (j + k < lump)
|
||||
printf (",");
|
||||
|
||||
k++;
|
||||
}
|
||||
j += k;
|
||||
printf ("\n");
|
||||
}
|
||||
i += j;
|
||||
printf ("};\n");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
filltable ()
|
||||
{
|
||||
op *p;
|
||||
int index = 1;
|
||||
|
||||
sorttab ();
|
||||
for (p = tab; p->name; p++)
|
||||
{
|
||||
p->index = index++;
|
||||
expand_opcode (12, 0, p->index, p->code);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
gensim ()
|
||||
{
|
||||
op *p;
|
||||
int j;
|
||||
|
||||
printf ("{\n");
|
||||
printf ("switch (jump_table[iword]) {\n");
|
||||
|
||||
for (p = tab; p->name; p++)
|
||||
{
|
||||
int sextbit = -1;
|
||||
|
||||
char *s = p->code;
|
||||
|
||||
printf ("\/\* %s %s *\/\n", p->name, p->code);
|
||||
printf ("case %d: \n", p->index);
|
||||
|
||||
printf ("{\n");
|
||||
while (*s)
|
||||
{
|
||||
switch (*s)
|
||||
{
|
||||
case '0':
|
||||
case '1':
|
||||
case '.':
|
||||
s += 4;
|
||||
break;
|
||||
case 'n':
|
||||
printf ("int n = (iword >>8) & 0xf;\n");
|
||||
s += 4;
|
||||
break;
|
||||
case 'm':
|
||||
printf ("int m = (iword >>4) & 0xf;\n");
|
||||
s += 4;
|
||||
|
||||
break;
|
||||
|
||||
case 'i':
|
||||
printf ("int i = (iword & 0x");
|
||||
|
||||
switch (s[1])
|
||||
{
|
||||
case '4':
|
||||
printf ("f");
|
||||
break;
|
||||
case '8':
|
||||
printf ("ff");
|
||||
break;
|
||||
case '1':
|
||||
sextbit = 12;
|
||||
|
||||
printf ("fff");
|
||||
break;
|
||||
}
|
||||
printf (")");
|
||||
|
||||
switch (s[3])
|
||||
{
|
||||
case '1':
|
||||
break;
|
||||
case '2':
|
||||
printf ("<<1");
|
||||
break;
|
||||
case '4':
|
||||
printf ("<<2");
|
||||
break;
|
||||
}
|
||||
printf (";\n");
|
||||
s += 4;
|
||||
}
|
||||
}
|
||||
if (sextbit>0)
|
||||
{
|
||||
printf("i = (i ^ (1<<%d))-(1<<%d);\n",sextbit-1,sextbit-1);
|
||||
}
|
||||
|
||||
for (j = 0; j < 10; j++)
|
||||
{
|
||||
if (p->stuff[j])
|
||||
{
|
||||
printf ("%s\n", p->stuff[j]);
|
||||
}
|
||||
}
|
||||
printf ("break;\n", p->stuff);
|
||||
printf ("}\n");
|
||||
}
|
||||
printf ("}\n}\n");
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
main (ac, av)
|
||||
char **av;
|
||||
|
||||
{
|
||||
if (ac > 1)
|
||||
{
|
||||
if (strcmp (av[1], "-t") == 0)
|
||||
{
|
||||
gengastab ();
|
||||
}
|
||||
else if (strcmp (av[1], "-s") == 0)
|
||||
{
|
||||
filltable ();
|
||||
dumptable ();
|
||||
|
||||
}
|
||||
else if (strcmp (av[1], "-x") == 0)
|
||||
{
|
||||
filltable ();
|
||||
gensim ();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
genopc ();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
392
sim/sh/interp.c
Normal file
392
sim/sh/interp.c
Normal file
|
|
@ -0,0 +1,392 @@
|
|||
#define MSIZE (256*1024)
|
||||
#define MMASKL ((MSIZE -1) & ~3)
|
||||
#define MMASKW ((MSIZE -1) & ~1)
|
||||
#define MMASKB ((MSIZE -1) & ~0)
|
||||
/* Simulator for the Hitachi SH architecture.
|
||||
|
||||
Written by Steve Chamberlain of Cygnus Support.
|
||||
sac@cygnus.com
|
||||
|
||||
This file is part of SH sim
|
||||
|
||||
|
||||
THIS SOFTWARE IS NOT COPYRIGHTED
|
||||
|
||||
Cygnus offers the following for use in the public domain. Cygnus
|
||||
makes no warranty with regard to the software or it's performance
|
||||
and the user accepts the software "AS IS" with all faults.
|
||||
|
||||
CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
|
||||
THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||
|
||||
*/
|
||||
|
||||
#include <signal.h>
|
||||
#include <sys/times.h>
|
||||
#include <sys/param.h>
|
||||
|
||||
#define O_RECOMPILE 85
|
||||
#define DEFINE_TABLE
|
||||
|
||||
#define DISASSEMBLER_TABLE
|
||||
|
||||
#define SBIT(x) ((x)&sbit)
|
||||
#define R0 saved_state.asregs.regs[0]
|
||||
#define Rn saved_state.asregs.regs[n]
|
||||
#define Rm saved_state.asregs.regs[m]
|
||||
|
||||
#define UR0 (unsigned long)(saved_state.asregs.regs[0])
|
||||
#define UR (unsigned long)R
|
||||
#define UR (unsigned long)R
|
||||
|
||||
#define SR0 saved_state.asregs.regs[0]
|
||||
|
||||
#define GBR saved_state.asregs.gbr
|
||||
#define VBR saved_state.asregs.vbr
|
||||
#define MACH saved_state.asregs.mach
|
||||
#define MACL saved_state.asregs.macl
|
||||
#define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word)
|
||||
#define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;}
|
||||
|
||||
#define PC pc
|
||||
#define C cycles
|
||||
|
||||
#define LMEM(x) *((long *)(memory+(x&maskl)))
|
||||
#define BMEM(x) *((char *)(memory+(x&maskb)))
|
||||
#define UWMEM(x) *((unsigned short *)(memory+(x&maskw)))
|
||||
#define SWMEM(x) *((short *)(memory+(x&maskw)))
|
||||
#define WLAT(x,value) (LMEM(x) = value)
|
||||
#define RLAT(x) (LMEM(x))
|
||||
|
||||
#define WWAT(x,value) (UWMEM(x) = value)
|
||||
#define RSWAT(x) (SWMEM(x))
|
||||
#define RUWAT(x) (UWMEM(x))
|
||||
|
||||
#define WBAT(x,value) (BMEM(x) = value)
|
||||
#define RBAT(x) (BMEM(x))
|
||||
|
||||
#define SEXT(x) ((int)((char)x))
|
||||
#define SEXTW(y) ((int)((short)y))
|
||||
#define M saved_state.asregs.sr.bits.m
|
||||
#define Q saved_state.asregs.sr.bits.q
|
||||
#define SL(TEMPPC) iword= RUWAT(TEMPPC); goto top;
|
||||
int debug;
|
||||
typedef union
|
||||
{
|
||||
|
||||
struct
|
||||
{
|
||||
|
||||
int regs[16];
|
||||
int pc;
|
||||
int pr;
|
||||
|
||||
int gbr;
|
||||
int vbr;
|
||||
int mach;
|
||||
int macl;
|
||||
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
int d0:22;
|
||||
int m:1;
|
||||
int q:1;
|
||||
int i:4;
|
||||
int d1:2;
|
||||
int s:1;
|
||||
int t:1;
|
||||
}
|
||||
bits;
|
||||
int word;
|
||||
}
|
||||
sr;
|
||||
int ticks;
|
||||
int cycles;
|
||||
int insts;
|
||||
unsigned char *memory;
|
||||
int exception;
|
||||
|
||||
}
|
||||
asregs;
|
||||
int asints[25];
|
||||
|
||||
}
|
||||
|
||||
saved_state_type;
|
||||
|
||||
|
||||
|
||||
saved_state_type saved_state;
|
||||
|
||||
|
||||
|
||||
/*#include "../opcodes/sh-opc.h"*/
|
||||
|
||||
|
||||
static int
|
||||
get_now ()
|
||||
{
|
||||
struct tms b;
|
||||
times (&b);
|
||||
return b.tms_utime + b.tms_stime;
|
||||
}
|
||||
|
||||
static int
|
||||
now_persec ()
|
||||
{
|
||||
return HZ;
|
||||
}
|
||||
|
||||
/* simulate a monitor trap */
|
||||
trap (i, regs)
|
||||
int *regs;
|
||||
{
|
||||
switch (i)
|
||||
{
|
||||
case 1:
|
||||
printf ("%c", regs[0]);
|
||||
break;
|
||||
case 2:
|
||||
saved_state.asregs.exception = SIGQUIT;
|
||||
break;
|
||||
case 255:
|
||||
saved_state.asregs.exception = SIGILL;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
void
|
||||
control_c (sig, code, scp, addr)
|
||||
int sig;
|
||||
int code;
|
||||
char *scp;
|
||||
char *addr;
|
||||
{
|
||||
saved_state.asregs.exception = SIGINT;
|
||||
}
|
||||
|
||||
|
||||
int div1(R,m,n,T)
|
||||
int *R;
|
||||
int m;
|
||||
int n;
|
||||
int T;
|
||||
{
|
||||
unsigned long tmp0;
|
||||
unsigned char old_q, tmp1;
|
||||
|
||||
old_q = Q;
|
||||
Q= R[n] <0;
|
||||
|
||||
R[n] <<=1;
|
||||
R[n] |= T;
|
||||
|
||||
switch (old_q)
|
||||
{
|
||||
case 0:
|
||||
switch (M)
|
||||
{
|
||||
case 0:
|
||||
tmp0 = R[n];
|
||||
R[n] -= R[m];
|
||||
tmp1 = (R[n] > tmp0) != Q;
|
||||
break;
|
||||
case 1:
|
||||
tmp0 = R[n];
|
||||
R[n] += R[m];
|
||||
tmp1 = (R[n] < tmp0) == Q;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
switch (M)
|
||||
{
|
||||
case 0:
|
||||
tmp0 = R[n];
|
||||
R[n] += R[m];
|
||||
tmp1 = (R[n] < tmp0) != Q;
|
||||
break;
|
||||
case 1:
|
||||
tmp0 = R[n];
|
||||
R[n] -= R[m];
|
||||
tmp1 = (R[n] > tmp0) == Q;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
T=(Q==M);
|
||||
return T;
|
||||
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
sim_resume (step)
|
||||
{
|
||||
static int init1;
|
||||
int pc;
|
||||
register int cycles = 0;
|
||||
register int insts = 0;
|
||||
int tick_start = get_now ();
|
||||
void (*prev) ();
|
||||
extern unsigned char sh_jump_table0[];
|
||||
|
||||
register unsigned char *jump_table = sh_jump_table0;
|
||||
|
||||
register int *R = &(saved_state.asregs.regs[0]);
|
||||
register int T;
|
||||
register int PR;
|
||||
|
||||
register int maskb = MMASKB;
|
||||
register int maskw = MMASKW;
|
||||
register int maskl = MMASKL;
|
||||
register unsigned char *memory = saved_state.asregs.memory;
|
||||
register int sbit = (1<<31);
|
||||
|
||||
prev = signal (SIGINT, control_c);
|
||||
|
||||
if (step)
|
||||
{
|
||||
saved_state.asregs.exception = SIGTRAP;
|
||||
}
|
||||
else
|
||||
{
|
||||
saved_state.asregs.exception = 0;
|
||||
}
|
||||
|
||||
pc = saved_state.asregs.pc;
|
||||
PR = saved_state.asregs.pr;
|
||||
T = saved_state.asregs.sr.bits.t;
|
||||
|
||||
do
|
||||
{
|
||||
unsigned int iword = RUWAT (pc);
|
||||
unsigned long ult;
|
||||
|
||||
insts++;
|
||||
top:
|
||||
|
||||
#include "code.c"
|
||||
|
||||
pc += 2;
|
||||
cycles++;
|
||||
}
|
||||
while (!saved_state.asregs.exception);
|
||||
|
||||
if (saved_state.asregs.exception == SIGILL)
|
||||
{
|
||||
pc-=2;
|
||||
}
|
||||
|
||||
saved_state.asregs.ticks += get_now () - tick_start;
|
||||
saved_state.asregs.cycles += cycles;
|
||||
saved_state.asregs.insts += insts;
|
||||
saved_state.asregs.pc = pc;
|
||||
saved_state.asregs.sr.bits.t = T;
|
||||
saved_state.asregs.pr = PR;
|
||||
|
||||
signal (SIGINT, prev);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
sim_write (addr, buffer, size)
|
||||
long int addr;
|
||||
unsigned char *buffer;
|
||||
int size;
|
||||
{
|
||||
int i;
|
||||
init_pointers ();
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
{
|
||||
saved_state.asregs.memory[MMASKB & (addr + i)] = buffer[i];
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
sim_read (addr, buffer, size)
|
||||
long int addr;
|
||||
char *buffer;
|
||||
int size;
|
||||
{
|
||||
int i;
|
||||
|
||||
init_pointers ();
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
{
|
||||
buffer[i] = saved_state.asregs.memory[MMASKB & (addr + i)];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
sim_store_register (rn, value)
|
||||
int rn;
|
||||
int value;
|
||||
{
|
||||
saved_state.asregs.regs[rn] = value;
|
||||
}
|
||||
|
||||
sim_fetch_register (rn, buf)
|
||||
int rn;
|
||||
char *buf;
|
||||
{
|
||||
|
||||
int value = ((int *) (&saved_state))[rn];
|
||||
|
||||
buf[0] = value >> 24;
|
||||
buf[1] = value >> 16;
|
||||
buf[2] = value >> 8;
|
||||
buf[3] = value >> 0;
|
||||
|
||||
}
|
||||
|
||||
int
|
||||
sim_trace ()
|
||||
{
|
||||
|
||||
int i;
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
sim_stop_signal ()
|
||||
{
|
||||
return saved_state.asregs.exception;
|
||||
}
|
||||
|
||||
sim_set_pc (x)
|
||||
{
|
||||
saved_state.asregs.pc = x;
|
||||
}
|
||||
|
||||
|
||||
|
||||
sim_info ()
|
||||
{
|
||||
double timetaken = (double) saved_state.asregs.ticks / (double) now_persec ();
|
||||
double virttime = saved_state.asregs.cycles / 10.0e6;
|
||||
|
||||
printf ("\n\ninstructions executed %10d\n", saved_state.asregs.insts);
|
||||
printf ("cycles %10d\n", saved_state.asregs.cycles);
|
||||
printf ("real time taken %10.4f\n", timetaken);
|
||||
printf ("cycles/second %10d\n", (int)(saved_state.asregs.cycles/timetaken));
|
||||
printf ("virtual time taked %10.4f\n", virttime);
|
||||
printf ("simulation ratio %10.4f\n", virttime / timetaken);
|
||||
}
|
||||
|
||||
init_pointers ()
|
||||
{
|
||||
if (!saved_state.asregs.memory)
|
||||
{
|
||||
saved_state.asregs.memory = (unsigned char *) (calloc (64, MSIZE / 64));
|
||||
}
|
||||
}
|
||||
98
sim/sh/run.c
Normal file
98
sim/sh/run.c
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/* run front end support for H8/500
|
||||
Copyright (C) 1987, 1992 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of H8300 SIM
|
||||
|
||||
GNU CC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GNU CC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GNU CC; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
|
||||
|
||||
/* Steve Chamberlain
|
||||
sac@cygnus.com */
|
||||
|
||||
#include "bfd.h"
|
||||
#include "sysdep.h"
|
||||
|
||||
int
|
||||
main (ac, av)
|
||||
int ac;
|
||||
char **av;
|
||||
{
|
||||
bfd *abfd;
|
||||
bfd_vma start_address;
|
||||
asection *s;
|
||||
int i;
|
||||
int verbose = 0;
|
||||
int trace = 0;
|
||||
char *name = "";
|
||||
for (i = 1; i < ac; i++)
|
||||
{
|
||||
if (strcmp (av[i], "-v") == 0)
|
||||
{
|
||||
verbose = 1;
|
||||
}
|
||||
else if (strcmp (av[i], "-t") == 0)
|
||||
{
|
||||
trace = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
name = av[i];
|
||||
}
|
||||
}
|
||||
if (verbose)
|
||||
{
|
||||
printf ("run %s\n", name);
|
||||
}
|
||||
abfd = bfd_openr (name, "coff-sh");
|
||||
if (abfd)
|
||||
{
|
||||
|
||||
if (bfd_check_format (abfd, bfd_object))
|
||||
{
|
||||
|
||||
for (s = abfd->sections; s; s = s->next)
|
||||
{
|
||||
unsigned char *buffer = malloc (bfd_section_size (abfd, s));
|
||||
bfd_get_section_contents (abfd,
|
||||
s,
|
||||
buffer,
|
||||
0,
|
||||
bfd_section_size (abfd, s));
|
||||
sim_write (s->vma, buffer, bfd_section_size (abfd, s));
|
||||
}
|
||||
|
||||
start_address = bfd_get_start_address (abfd);
|
||||
sim_set_pc (start_address);
|
||||
if (trace)
|
||||
{
|
||||
int done = 0;
|
||||
while (!done)
|
||||
{
|
||||
done = sim_trace ();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
sim_resume (0, 0);
|
||||
}
|
||||
if (verbose)
|
||||
sim_info ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
Loading…
Reference in a new issue