Add ATPCS support to ARM disassembler.
Document ARM disassembler options.
This commit is contained in:
Nick Clifton
parent
94470b237b
commit
58efb6c0fd
7 changed files with 216 additions and 173 deletions
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@ -1,5 +1,8 @@
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2000-01-27 Nick Clifton <nickc@redhat.com>
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* binutils.texi (objdump): Document new ARM specific
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disassembler options.
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* objdump.c (usage): Call disassembler_usage().
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2000-01-27 Alan Modra <alan@spri.levels.unisa.edu.au>
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@ -1346,13 +1346,17 @@ some targets.
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If the target is an ARM architecture then this switch can be used to
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select which register name set is used during disassembler. Specifying
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@samp{--disassembler-options=reg-name-std} (the default) will select the
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register names as used in ARM's instruction set documentation, but with
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register 13 called 'sp', register 14 called 'lr' and register 15 called
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'pc'. Specifying @samp{--disassembler-options=reg-names-apcs} will
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select the name set used by the ARM Procedure Call Standard, whilst
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specifying @samp{--disassembler-options=reg-names-raw} will just use
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@samp{r} followed by the register number.
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@samp{-M reg-name-std} (the default) will select the register names as
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used in ARM's instruction set documentation, but with register 13 called
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'sp', register 14 called 'lr' and register 15 called 'pc'. Specifying
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@samp{-M reg-names-apcs} will select the name set used by the ARM
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Procedure Call Standard, whilst specifying @samp{-M reg-names-raw} will
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just use @samp{r} followed by the register number.
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There are also two variants on the APCS register naming scheme enabled
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by @samp{-M reg-names-atpcs} and @samp{-M reg-names-atpcs-special} which
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use the ARM/Thumb Procedure Call Standard naming conventions. (Eiuther
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with the normal register name sor the special register names).
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This option can also be used for ARM architectures to force the
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disassembler to interpret all instructions as THUMB instructions by
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@ -1,6 +1,8 @@
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2000-01-27 Nick Clifton <nickc@redhat.com>
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* dis-asm.h: Add prototype for disassembler_usage().
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Add prototype for arm_disassembler_options().
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Remvoe prototype for arm_toggle_regnames().
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1999-12-15 Doug Evans <dje@transmeta.com>
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@ -189,7 +189,7 @@ extern int print_insn_vax PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_tic80 PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_pj PARAMS ((bfd_vma, disassemble_info*));
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extern int arm_toggle_regnames PARAMS ((void));
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extern void print_arm_disassembler_options PARAMS ((FILE *));
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/* Fetch the disassembler for a given BFD, if that support is available. */
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extern disassembler_ftype disassembler PARAMS ((bfd *));
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@ -2,7 +2,21 @@
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* disassemble.c (disassembler_usage): New function: Print out any
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target specific disassembler options.
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Call arm_disassembler_options() if the ARM architecture is being
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supported.
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* arm-dis.c (NUM_ELEM): Define this macro if not already
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defined.
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(arm_regname): New struct type for ARM register names.
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(arm_toggle_regnames): Delete.
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(parse_disassembler_option): Use register name structure.
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(print_insn): New function: Combines duplicate code found in
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print_insn_big_arm and print_insn_little_arm.
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(print_insn_big_arm): Call print_insn.
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(print_insn_little_arm): Call print_insn.
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(print_arm_disassembler_options): Display list of supported,
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ARM specific disassembler options.
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2000-01-27 Thomas de Lellis <tdel@windriver.com>
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* arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
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@ -33,30 +33,48 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "elf/arm.h"
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#ifndef streq
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#define streq(a,b) (strcmp ((a), (b)) == 0)
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#define streq(a,b) (strcmp ((a), (b)) == 0)
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#endif
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#ifndef strneq
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#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
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#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
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#endif
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#ifndef NUM_ELEM
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#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
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#endif
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static char * arm_conditional[] =
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{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
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static char * arm_regnames_raw[] =
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{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
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typedef struct
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{
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const char * name;
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const char * description;
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const char * reg_names[16];
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}
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arm_regname;
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static char * arm_regnames_standard[] =
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{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"};
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static arm_regname regnames[] =
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{
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{ "raw" , "Select raw register names",
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
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{ "std", "Select register names used in ARM's ISA documentation",
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
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{ "apcs", "Select register names used in the APCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
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{ "atpcs", "Select register names used in the ATPCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
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{ "atpcs-special", "Select special register names used in the ATPCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
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};
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static char * arm_regnames_apcs[] =
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{"a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4",
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"v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc"};
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/* Default to standard register name set. */
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static unsigned int regname_selected = 1;
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/* Choose which register name set to use. */
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static char ** arm_regnames = arm_regnames_standard;
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#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
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#define arm_regnames regnames[regname_selected].reg_names
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static boolean force_thumb = false;
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@ -72,6 +90,7 @@ static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long))
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static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
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static void parse_disassembler_option PARAMS ((char *));
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static void parse_disassembler_options PARAMS ((char *));
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static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean));
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/* Functions. */
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static void
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@ -110,7 +129,6 @@ arm_decode_shift (given, func, stream)
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction (always 4 on ARM). */
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static int
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print_insn_arm (pc, info, given)
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bfd_vma pc;
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@ -155,18 +173,19 @@ print_insn_arm (pc, info, given)
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offset += pc + 8;
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/* Cope with the possibility of write-back being used.
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Probably a very dangerous thing for the programmer
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to do, but who are we to argue ? */
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/* Cope with the possibility of write-back
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being used. Probably a very dangerous thing
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for the programmer to do, but who are we to
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argue ? */
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if (given & 0x00200000)
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func (stream, "!");
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}
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else
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{
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/* post indexed */
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/* Post indexed. */
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func (stream, "], #%x", offset);
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offset = pc + 8; /* ie ignore the offset */
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offset = pc + 8; /* ie ignore the offset. */
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}
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func (stream, "\t; ");
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@ -223,7 +242,7 @@ print_insn_arm (pc, info, given)
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case 's':
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if ((given & 0x004f0000) == 0x004f0000)
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{
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/* PC relative with immediate offset */
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/* PC relative with immediate offset. */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if ((given & 0x00800000) == 0)
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@ -240,10 +259,10 @@ print_insn_arm (pc, info, given)
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arm_regnames[(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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{
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/* pre-indexed */
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/* Pre-indexed. */
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if ((given & 0x00400000) == 0x00400000)
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{
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/* immediate */
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/* Immediate. */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if (offset)
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func (stream, ", %s#%d",
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@ -252,7 +271,7 @@ print_insn_arm (pc, info, given)
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}
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else
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{
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/* register */
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/* Register. */
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func (stream, ", %s%s",
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(((given & 0x00800000) == 0)
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? "-" : ""),
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@ -264,10 +283,10 @@ print_insn_arm (pc, info, given)
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}
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else
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{
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/* post-indexed */
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/* Post-indexed. */
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if ((given & 0x00400000) == 0x00400000)
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{
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/* immediate */
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/* Immediate. */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if (offset)
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func (stream, "], %s#%d",
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@ -278,7 +297,7 @@ print_insn_arm (pc, info, given)
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}
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else
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{
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/* register */
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/* Register. */
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func (stream, "], %s%s",
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(((given & 0x00800000) == 0)
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? "-" : ""),
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@ -469,36 +488,46 @@ print_insn_arm (pc, info, given)
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{
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case '-':
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c++;
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while (*c >= '0' && *c <= '9')
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bitend = (bitend * 10) + *c++ - '0';
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if (!bitend)
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abort ();
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switch (*c)
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{
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case 'r':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%s", arm_regnames[reg]);
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}
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break;
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case 'd':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%d", reg);
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}
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break;
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case 'x':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "0x%08x", reg);
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/* Some SWI instructions have special meanings. */
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/* Some SWI instructions have special
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meanings. */
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if ((given & 0x0fffffff) == 0x0FF00000)
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func (stream, "\t; IMB");
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else if ((given & 0x0fffffff) == 0x0FF00001)
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@ -508,16 +537,20 @@ print_insn_arm (pc, info, given)
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case 'X':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%01x", reg & 0xf);
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}
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break;
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case 'f':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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if (reg > 7)
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func (stream, "#%s",
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arm_fp_const[reg & 7]);
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@ -529,6 +562,7 @@ print_insn_arm (pc, info, given)
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abort ();
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}
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break;
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case '`':
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c++;
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if ((given & (1 << bitstart)) == 0)
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@ -567,7 +601,6 @@ print_insn_arm (pc, info, given)
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction. */
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static int
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print_insn_thumb (pc, info, given)
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bfd_vma pc;
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@ -584,15 +617,14 @@ print_insn_thumb (pc, info, given)
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{
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char * c = insn->assembler;
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/* Special processing for Thumb 2 instruction BL sequence: */
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if (!*c) /* check for empty (not NULL) assembler string */
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/* Special processing for Thumb 2 instruction BL sequence: */
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if (!*c) /* Check for empty (not NULL) assembler string. */
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{
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info->bytes_per_chunk = 4;
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info->bytes_per_line = 4;
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func (stream, "bl\t");
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(*info->print_address_func)
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(BDISP23 (given) * 2 + pc + 4, info);
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info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
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return 4;
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}
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else
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@ -601,7 +633,7 @@ print_insn_thumb (pc, info, given)
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info->bytes_per_line = 4;
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given &= 0xffff;
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for (; *c; c++)
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{
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if (*c == '%')
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@ -618,9 +650,11 @@ print_insn_thumb (pc, info, given)
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case 'S':
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{
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long reg;
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reg = (given >> 3) & 0x7;
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if (given & (1 << 6))
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reg += 8;
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func (stream, "%s", arm_regnames[reg]);
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}
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break;
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@ -632,6 +666,7 @@ print_insn_thumb (pc, info, given)
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reg = given & 0x7;
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if (given & (1 << 7))
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reg += 8;
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func (stream, "%s", arm_regnames[reg]);
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}
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break;
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@ -644,17 +679,18 @@ print_insn_thumb (pc, info, given)
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case 'N':
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if (given & (1 << 8))
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domasklr = 1;
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/* fall through */
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/* Fall through. */
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case 'O':
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if (*c == 'O' && (given & (1 << 8)))
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domaskpc = 1;
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/* fall through */
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/* Fall through. */
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case 'M':
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{
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int started = 0;
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int reg;
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func (stream, "{");
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/* It would be nice if we could spot
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ranges, and generate the rS-rE format: */
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for (reg = 0; (reg < 8); reg++)
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@ -728,8 +764,8 @@ print_insn_thumb (pc, info, given)
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case 'a':
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/* PC-relative address -- the bottom two
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bits of the address are dropped before
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the calculation. */
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bits of the address are dropped
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before the calculation. */
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info->print_address_func
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(((pc + 4) & ~3) + (reg << 2), info);
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break;
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@ -787,23 +823,11 @@ print_insn_thumb (pc, info, given)
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}
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}
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/* no match */
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/* No match. */
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abort ();
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}
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/* Select a different register name set.
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Returns true if the name set selected is the APCS name set. */
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int
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arm_toggle_regnames ()
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{
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if (arm_regnames == arm_regnames_standard)
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arm_regnames = arm_regnames_apcs;
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else
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arm_regnames = arm_regnames_standard;
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return arm_regnames == arm_regnames_apcs;
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}
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/* Parse an individual disassembler option. */
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static void
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parse_disassembler_option (option)
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char * option;
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@ -813,27 +837,31 @@ parse_disassembler_option (option)
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if (strneq (option, "reg-names-", 10))
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{
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int i;
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option += 10;
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for (i = NUM_ARM_REGNAMES; i--;)
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if (streq (option, regnames[i].name))
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{
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regname_selected = i;
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break;
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}
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if (streq (option, "std"))
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arm_regnames = arm_regnames_standard;
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else if (streq (option, "apcs"))
|
||||
arm_regnames = arm_regnames_apcs;
|
||||
else if (streq (option, "raw"))
|
||||
arm_regnames = arm_regnames_raw;
|
||||
else
|
||||
fprintf (stderr, "Unrecognised register name set: %s\n", option);
|
||||
if (i < 0)
|
||||
fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
|
||||
}
|
||||
else if (streq (option, "force-thumb"))
|
||||
force_thumb = 1;
|
||||
else if (streq (option, "no-force-thumb"))
|
||||
force_thumb = 0;
|
||||
else
|
||||
fprintf (stderr, "Unrecognised disassembler option: %s\n", option);
|
||||
fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Parse the string of disassembler options, spliting it at whitespaces. */
|
||||
static void
|
||||
parse_disassembler_options (options)
|
||||
char * options;
|
||||
|
|
@ -860,24 +888,24 @@ parse_disassembler_options (options)
|
|||
while (space);
|
||||
}
|
||||
|
||||
/* NOTE: There are no checks in these routines that the relevant number of
|
||||
data bytes exist. */
|
||||
|
||||
int
|
||||
print_insn_big_arm (pc, info)
|
||||
/* NOTE: There are no checks in these routines that
|
||||
the relevant number of data bytes exist. */
|
||||
static int
|
||||
print_insn (pc, info, little)
|
||||
bfd_vma pc;
|
||||
struct disassemble_info * info;
|
||||
boolean little;
|
||||
{
|
||||
unsigned char b[4];
|
||||
long given;
|
||||
int status;
|
||||
int is_thumb;
|
||||
|
||||
|
||||
if (info->disassembler_options)
|
||||
{
|
||||
parse_disassembler_options (info->disassembler_options);
|
||||
|
||||
/* To avoid repeated parsing of the options, we remove it here. */
|
||||
/* To avoid repeated parsing of these options, we remove them here. */
|
||||
info->disassembler_options = NULL;
|
||||
}
|
||||
|
||||
|
|
@ -899,46 +927,70 @@ print_insn_big_arm (pc, info)
|
|||
else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
|
||||
{
|
||||
elf_symbol_type * es;
|
||||
unsigned int type;
|
||||
|
||||
es = *(elf_symbol_type **)(info->symbols);
|
||||
is_thumb = (ELF_ST_TYPE (es->internal_elf_sym.st_info) == STT_ARM_TFUNC)
|
||||
|| (ELF_ST_TYPE (es->internal_elf_sym.st_info) == STT_ARM_16BIT);
|
||||
}
|
||||
}
|
||||
|
||||
info->bytes_per_chunk = 4;
|
||||
info->display_endian = BFD_ENDIAN_BIG;
|
||||
|
||||
/* Always fetch word aligned values. */
|
||||
|
||||
status = (*info->read_memory_func) (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, pc, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (is_thumb)
|
||||
{
|
||||
if (pc & 0x2)
|
||||
{
|
||||
given = (b[2] << 8) | b[3];
|
||||
|
||||
status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
info->memory_error_func (status, pc + 4, info);
|
||||
return -1;
|
||||
}
|
||||
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
|
||||
|
||||
given |= (b[0] << 24) | (b[1] << 16);
|
||||
is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
|
||||
}
|
||||
else
|
||||
given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
|
||||
}
|
||||
|
||||
info->bytes_per_chunk = 4;
|
||||
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
|
||||
|
||||
if (little)
|
||||
{
|
||||
status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info);
|
||||
if (status != 0 && is_thumb)
|
||||
{
|
||||
info->bytes_per_chunk = 2;
|
||||
|
||||
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
|
||||
b[3] = b[2] = 0;
|
||||
}
|
||||
|
||||
if (status != 0)
|
||||
{
|
||||
info->memory_error_func (status, pc, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
|
||||
}
|
||||
else
|
||||
given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
|
||||
|
||||
{
|
||||
status = info->read_memory_func
|
||||
(pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
info->memory_error_func (status, pc, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (is_thumb)
|
||||
{
|
||||
if (pc & 0x2)
|
||||
{
|
||||
given = (b[2] << 8) | b[3];
|
||||
|
||||
status = info->read_memory_func
|
||||
((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
info->memory_error_func (status, pc + 4, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
given |= (b[0] << 24) | (b[1] << 16);
|
||||
}
|
||||
else
|
||||
given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
|
||||
}
|
||||
else
|
||||
given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
|
||||
}
|
||||
|
||||
if (is_thumb)
|
||||
status = print_insn_thumb (pc, info, given);
|
||||
else
|
||||
|
|
@ -947,73 +999,37 @@ print_insn_big_arm (pc, info)
|
|||
return status;
|
||||
}
|
||||
|
||||
int
|
||||
print_insn_big_arm (pc, info)
|
||||
bfd_vma pc;
|
||||
struct disassemble_info * info;
|
||||
{
|
||||
return print_insn (pc, info, false);
|
||||
}
|
||||
|
||||
int
|
||||
print_insn_little_arm (pc, info)
|
||||
bfd_vma pc;
|
||||
struct disassemble_info * info;
|
||||
{
|
||||
unsigned char b[4];
|
||||
long given;
|
||||
int status;
|
||||
int is_thumb;
|
||||
|
||||
if (info->disassembler_options)
|
||||
{
|
||||
parse_disassembler_options (info->disassembler_options);
|
||||
|
||||
/* To avoid repeated parsing of the options, we remove it here. */
|
||||
info->disassembler_options = NULL;
|
||||
}
|
||||
|
||||
is_thumb = force_thumb;
|
||||
|
||||
if (!is_thumb && info->symbols != NULL)
|
||||
{
|
||||
if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
|
||||
{
|
||||
coff_symbol_type * cs;
|
||||
|
||||
cs = coffsymbol (*info->symbols);
|
||||
is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
|
||||
|| cs->native->u.syment.n_sclass == C_THUMBSTAT
|
||||
|| cs->native->u.syment.n_sclass == C_THUMBLABEL
|
||||
|| cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
|
||||
|| cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
|
||||
}
|
||||
else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
|
||||
{
|
||||
elf_symbol_type * es;
|
||||
|
||||
es = *(elf_symbol_type **)(info->symbols);
|
||||
is_thumb = (ELF_ST_TYPE (es->internal_elf_sym.st_info) == STT_ARM_TFUNC)
|
||||
|| (ELF_ST_TYPE (es->internal_elf_sym.st_info) == STT_ARM_16BIT);
|
||||
}
|
||||
}
|
||||
|
||||
info->bytes_per_chunk = 4;
|
||||
info->display_endian = BFD_ENDIAN_LITTLE;
|
||||
|
||||
status = (*info->read_memory_func) (pc, (bfd_byte *) &b[0], 4, info);
|
||||
if (status != 0 && is_thumb)
|
||||
{
|
||||
info->bytes_per_chunk = 2;
|
||||
|
||||
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
|
||||
b[3] = b[2] = 0;
|
||||
}
|
||||
|
||||
if (status != 0)
|
||||
{
|
||||
info->memory_error_func (status, pc, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
|
||||
|
||||
if (is_thumb)
|
||||
status = print_insn_thumb (pc, info, given);
|
||||
else
|
||||
status = print_insn_arm (pc, info, given);
|
||||
|
||||
return status;
|
||||
return print_insn (pc, info, true);
|
||||
}
|
||||
|
||||
void
|
||||
print_arm_disassembler_options (FILE * stream)
|
||||
{
|
||||
int i;
|
||||
|
||||
fprintf (stream, _("\n\
|
||||
The following ARM specific disassembler options are supported for use with\n\
|
||||
the -M switch:\n"));
|
||||
|
||||
for (i = NUM_ARM_REGNAMES; i--;)
|
||||
fprintf (stream, " reg-names-%s %*c%s\n",
|
||||
regnames[i].name,
|
||||
14 - strlen (regnames[i].name), ' ',
|
||||
regnames[i].description);
|
||||
|
||||
fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
|
||||
fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -255,5 +255,9 @@ disassembler (abfd)
|
|||
void
|
||||
disassembler_usage (FILE * stream)
|
||||
{
|
||||
#ifdef ARCH_arm
|
||||
print_arm_disassembler_options (stream);
|
||||
#endif
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue