darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Fix parameters passed to CPRead[13] and CPRead[14].

Browse source
This commit is contained in:
Nick Clifton 2002-01-10 11:14:57 +00:00
parent db60ec6263
commit 57165fb4bb
4 changed files with 476 additions and 421 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
sim/arm/ChangeLog
View file

@ -1,3 +1,11 @@
2002-01-10 Nick Clifton <nickc@cambridge.redhat.com>
* arminit.c (ARMul_Abort): Fix parameters passed to CPRead[13].
* armemu.c (ARMul_Emulate32): Fix parameters passed to CPRead[13]
and CPRead[14].
Fix formatting. Improve layout.
* armemu.h: Fix formatting. Improve layout.
2002-01-09 Nick Clifton <nickc@cambridge.redhat.com>
* wrapper.c (sim_fetch_register): If fetching more than 4 bytes

808
sim/arm/armemu.c
View file

File diff suppressed because it is too large Load diff

71
sim/arm/armemu.h
View file

@ -305,9 +305,9 @@ extern ARMword isize;
#define NEXTCYCLE(c)
/* Macros to extract parts of instructions. */
#define DESTReg (BITS(12,15))
#define LHSReg (BITS(16,19))
#define RHSReg (BITS(0,3))
#define DESTReg (BITS (12, 15))
#define LHSReg (BITS (16, 19))
#define RHSReg (BITS ( 0, 3))
#define DEST (state->Reg[DESTReg])
@ -367,42 +367,62 @@ extern ARMword isize;
/* Determine if access to coprocessor CP is permitted.
The XScale has a register in CP15 which controls access to CP0 - CP13. */
#define CP_ACCESS_ALLOWED(STATE, CP) \
( ((CP) >= 14) \
|| (! (STATE)->is_XScale) \
#define CP_ACCESS_ALLOWED(STATE, CP) \
( ((CP) >= 14) \
|| (! (STATE)->is_XScale) \
|| (read_cp15_reg (15, 0, 1) & (1 << (CP))))
/* Macro to rotate n right by b bits. */
#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
/* Macros to store results of instructions. */
#define WRITEDEST(d) if (DESTReg == 15) \
WriteR15 (state, d) ; \
else \
DEST = d
#define WRITEDEST(d) \
do \
{ \
if (DESTReg == 15) \
WriteR15 (state, d); \
else \
DEST = d; \
} \
while (0)
#define WRITESDEST(d) if (DESTReg == 15) \
WriteSR15 (state, d) ; \
else { \
DEST = d ; \
ARMul_NegZero (state, d) ; \
}
#define WRITESDEST(d) \
do \
{ \
if (DESTReg == 15) \
WriteSR15 (state, d); \
else \
{ \
DEST = d; \
ARMul_NegZero (state, d); \
} \
} \
while (0)
#define WRITEDESTB(d) if (DESTReg == 15) \
WriteR15Branch (state, d) ; \
else \
DEST = d
#define WRITEDESTB(d) \
do \
{ \
if (DESTReg == 15) \
WriteR15Branch (state, d); \
else \
DEST = d; \
} \
while (0)
#define BYTETOBUS(data) ((data & 0xff) | \
((data & 0xff) << 8) | \
((data & 0xff) << 16) | \
((data & 0xff) << 24))
#define BUSTOBYTE(address, data) \
if (state->bigendSig) \
temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
else \
temp = (data >> ((address & 3) << 3)) & 0xff
#define BUSTOBYTE(address, data) \
do \
{ \
if (state->bigendSig) \
temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \
else \
temp = (data >> ((address & 3) << 3)) & 0xff; \
} \
while (0)
#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb)
#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb)
@ -414,7 +434,6 @@ extern ARMword isize;
/* Values for Emulate. */
#define STOP 0 /* stop */
#define CHANGEMODE 1 /* change mode */
#define ONCE 2 /* execute just one interation */

10
sim/arm/arminit.c
View file

@ -302,13 +302,15 @@ ARMul_Abort (ARMul_State * state, ARMword vector)
SETABORT (IBIT, SVC26MODE, isize);
break;
case ARMul_IRQV: /* IRQ */
if (!state->is_XScale
|| (state->CPRead[13](state, 0, 0) & ARMul_CP13_R0_IRQ))
if ( ! state->is_XScale
|| ! state->CPRead[13] (state, 0, & temp)
|| (temp & ARMul_CP13_R0_IRQ))
SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
break;
case ARMul_FIQV: /* FIQ */
if (!state->is_XScale
|| (state->CPRead[13](state, 0, 0) & ARMul_CP13_R0_FIQ))
if ( ! state->is_XScale
|| ! state->CPRead[13] (state, 0, & temp)
|| (temp & ARMul_CP13_R0_FIQ))
SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
break;
}