2001-01-06 Jan Hubicka <jh@suse.cz>, Andreas Jaeger <aj@suse.de>
* doc/as.texinfo: Document '#' as comment character for i386 and x86_64. Add AMD x86-64 into menu of machine dependent information. * doc/c-i386.texi: Document x86_64 extensions.
This commit is contained in:
Andreas Jaeger
parent
7bc70a8e57
commit
55b6267185
3 changed files with 204 additions and 30 deletions
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@ -1,3 +1,10 @@
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2001-01-06 Jan Hubicka <jh@suse.cz>, Andreas Jaeger <aj@suse.de>
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* doc/as.texinfo: Document '#' as comment character for i386 and
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x86_64. Add AMD x86-64 into menu of machine dependent information.
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* doc/c-i386.texi: Document x86_64 extensions.
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Fri Jan 5 13:26:42 MET 2001 Jan Hubicka <jh@suse.cz>
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* tc-i386.c (md_assemble): Handle third byte of the opcode as prefix.
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@ -187,7 +194,7 @@ Wed Dec 20 14:21:22 MET 2000 Jan Hubicka <jh@suse.cz>
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2000-12-15 Diego Novillo <dnovillo@redhat.com>
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* config/tc-i386.c (intel_e09_1): Only flag as a memory operand if
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it's not an offset expression.
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it's not an offset expression.
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(intel_e10_1): Ditto. Also, if the operand is an offset expression,
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keep the braces '[' and ']' in the output string.
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(intel_e11): Ditto. Also remove comparison intel_parser.op_modifier
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@ -252,7 +259,7 @@ Wed Dec 20 14:21:22 MET 2000 Jan Hubicka <jh@suse.cz>
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* macro.c: Fix formatting.
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* config/tc-mips.c: Fix formatting.
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* doc/c-mips.texi: Fix formatting.
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Mon Dec 11 14:35:42 MET 2000 Jan hubicka <jh@suse.cz>
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* tc-i386.c (md_assemble): Refuse 's' and 'l' suffixes in the intel
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@ -1667,6 +1667,9 @@ is considered a comment and is ignored. The line comment character is
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@ifset HPPA
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@samp{;} for the HPPA;
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@end ifset
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@ifset I80386
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@samp{#} on the i386 and x86-64;
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@end ifset
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@ifset I960
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@samp{#} on the i960;
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@end ifset
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@ -1698,7 +1701,7 @@ is considered a comment and is ignored. The line comment character is
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@samp{#} on the V850;
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@end ifset
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see @ref{Machine Dependencies}. @refill
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@c FIXME What about i386, m88k, i860?
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@c FIXME What about m88k, i860?
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@ifset GENERIC
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On some machines there are two different line comment characters. One
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@ -5244,7 +5247,7 @@ subject, see the hardware manufacturer's manual.
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* ESA/390-Dependent:: IBM ESA/390 Dependent Features
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@end ifset
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@ifset I80386
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* i386-Dependent:: Intel 80386 Dependent Features
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* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features
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@end ifset
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@ifset I860
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* i860-Dependent:: Intel 80860 Dependent Features
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@ -13,6 +13,12 @@
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@cindex i386 support
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@cindex i80306 support
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@cindex x86-64 support
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The i386 version @code{@value{AS}} supports both the original Intel 386
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architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
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extending the Intel architecture to 64-bits.
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@menu
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* i386-Options:: Options
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* i386-Syntax:: AT&T Syntax versus Intel Syntax
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@ -32,10 +38,29 @@
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@node i386-Options
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@section Options
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@cindex options for i386 (none)
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@cindex i386 options (none)
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The 80386 has no machine dependent options.
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@cindex options for i386
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@cindex options for x86-64
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@cindex i386 options
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@cindex x86-64 options
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The i386 version of @code{@value{AS}} has a few machine
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dependent options:
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@table @code
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@cindex @samp{--32} option, i386
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@cindex @samp{--32} option, x86-64
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@cindex @samp{--64} option, i386
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@cindex @samp{--64} option, x86-64
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@item --32 | --64
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Select the word size, either 32 bits or 64 bits. Selecting 32-bit
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implies Intel i386 architecture, while 64-bit implies AMD x86-64
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architecture.
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These options are only available with the ELF object file format, and
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require that the necessary BFD support has been included (on a 32-bit
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platform you have to add --enable-64-bit-bfd to configure enable 64-bit
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usage and use x86-64 as target platform).
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@end table
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@node i386-Syntax
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@section AT&T Syntax versus Intel Syntax
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@ -46,6 +71,12 @@ The 80386 has no machine dependent options.
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@cindex att_syntax pseudo op, i386
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@cindex i386 syntax compatibility
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@cindex syntax compatibility, i386
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@cindex x86-64 intel_syntax pseudo op
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@cindex intel_syntax pseudo op, x86-64
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@cindex x86-64 att_syntax pseudo op
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@cindex att_syntax pseudo op, x86-64
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@cindex x86-64 syntax compatibility
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@cindex syntax compatibility, x86-64
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@code{@value{AS}} now supports assembly using Intel assembler syntax.
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@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
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@ -64,6 +95,14 @@ between the two syntaxes are:
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@cindex jump/call operands, i386
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@cindex i386 jump/call operands
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@cindex operand delimiters, i386
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@cindex immediate operands, x86-64
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@cindex x86-64 immediate operands
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@cindex register operands, x86-64
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@cindex x86-64 register operands
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@cindex jump/call operands, x86-64
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@cindex x86-64 jump/call operands
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@cindex operand delimiters, x86-64
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@itemize @bullet
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@item
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AT&T immediate operands are preceded by @samp{$}; Intel immediate
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@ -74,6 +113,8 @@ operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
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@cindex i386 source, destination operands
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@cindex source, destination operands; i386
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@cindex x86-64 source, destination operands
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@cindex source, destination operands; x86-64
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@item
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AT&T and Intel syntax use the opposite order for source and destination
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operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
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@ -85,17 +126,23 @@ reversed order. @ref{i386-Bugs}.
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@cindex mnemonic suffixes, i386
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@cindex sizes operands, i386
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@cindex i386 size suffixes
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@cindex mnemonic suffixes, x86-64
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@cindex sizes operands, x86-64
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@cindex x86-64 size suffixes
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@item
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In AT&T syntax the size of memory operands is determined from the last
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character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
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@samp{w}, and @samp{l} specify byte (8-bit), word (16-bit), and long
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(32-bit) memory references. Intel syntax accomplishes this by prefixing
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memory operands (@emph{not} the instruction mnemonics) with @samp{byte
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ptr}, @samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al,
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byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax.
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@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
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(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
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this by prefixing memory operands (@emph{not} the instruction mnemonics) with
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@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
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Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
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syntax.
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@cindex return instructions, i386
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@cindex i386 jump, call, return
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@cindex return instructions, x86-64
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@cindex x86-64 jump, call, return
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@item
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Immediate form long jumps and calls are
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@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
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@ -107,6 +154,8 @@ is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
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@cindex sections, i386
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@cindex i386 sections
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@cindex sections, x86-64
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@cindex x86-64 sections
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@item
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The AT&T assembler does not provide support for multiple section
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programs. Unix style systems expect all programs to be single sections.
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@ -117,17 +166,20 @@ programs. Unix style systems expect all programs to be single sections.
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@cindex i386 instruction naming
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@cindex instruction naming, i386
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@cindex x86-64 instruction naming
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@cindex instruction naming, x86-64
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Instruction mnemonics are suffixed with one character modifiers which
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specify the size of operands. The letters @samp{b}, @samp{w}, and
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@samp{l} specify byte, word, and long operands. If no suffix is
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specified by an instruction then @code{@value{AS}} tries to fill in the
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missing suffix based on the destination register operand (the last one
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by convention). Thus, @samp{mov %ax, %bx} is equivalent to @samp{movw
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%ax, %bx}; also, @samp{mov $1, %bx} is equivalent to @samp{movw $1,
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%bx}. Note that this is incompatible with the AT&T Unix assembler which
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assumes that a missing mnemonic suffix implies long operand size. (This
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incompatibility does not affect compiler output since compilers always
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explicitly specify the mnemonic suffix.)
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specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
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and @samp{q} specify byte, word, long and quadruple word operands. If
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no suffix is specified by an instruction then @code{@value{AS}} tries to
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fill in the missing suffix based on the destination register operand
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(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
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to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
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@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
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assembler which assumes that a missing mnemonic suffix implies long
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operand size. (This incompatibility does not affect compiler output
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since compilers always explicitly specify the mnemonic suffix.)
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Almost all instructions have the same names in AT&T and Intel format.
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There are a few exceptions. The sign extend and zero extend
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@ -141,10 +193,14 @@ are tacked on to this base name, the @emph{from} suffix before the
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@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
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``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
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thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
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and @samp{wl} (from word to long).
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@samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
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@samp{wq} (from word to quadruple word), and @samp{lq} (from long to
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quadruple word).
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@cindex conversion instructions, i386
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@cindex i386 conversion instructions
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@cindex conversion instructions, x86-64
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@cindex x86-64 conversion instructions
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The Intel-syntax conversion instructions
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@itemize @bullet
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@ -159,14 +215,25 @@ The Intel-syntax conversion instructions
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@item
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@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
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@item
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@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
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(x86-64 only),
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@item
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@samp{cdo} --- sign-extend quad in @samp{%rax} to octuple in
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@samp{%rdx:%rax} (x86-64 only),
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@end itemize
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@noindent
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are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, and @samp{cltd} in
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AT&T naming. @code{@value{AS}} accepts either naming for these instructions.
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are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
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@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
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instructions.
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@cindex jump instructions, i386
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@cindex call instructions, i386
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@cindex jump instructions, x86-64
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@cindex call instructions, x86-64
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Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
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AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
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convention.
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@ -176,6 +243,8 @@ convention.
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@cindex i386 registers
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@cindex registers, i386
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@cindex x86-64 registers
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@cindex registers, x86-64
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Register operands are always prefixed with @samp{%}. The 80386 registers
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consist of
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|
@ -215,6 +284,44 @@ the 2 test registers @samp{%tr6} and @samp{%tr7}.
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the 8 floating point register stack @samp{%st} or equivalently
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@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
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@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
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These registers are overloaded by 8 MMX registers @samp{%mm0},
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@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
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@samp{%mm6} and @samp{%mm7}.
|
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|
||||
@item
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the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
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||||
@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
|
||||
@end itemize
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||||
|
||||
The AMD x86-64 architecture extends the register set by:
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||||
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||||
@itemize @bullet
|
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@item
|
||||
enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
|
||||
accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
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||||
@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
|
||||
pointer)
|
||||
|
||||
@item
|
||||
the 8 extended registers @samp{%r8}--@samp{%r15}.
|
||||
|
||||
@item
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||||
the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
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||||
|
||||
@item
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||||
the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
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||||
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||||
@item
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||||
the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
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||||
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||||
@item
|
||||
the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
|
||||
|
||||
@item
|
||||
the 8 debug registers: @samp{%db8}--@samp{%db15}.
|
||||
|
||||
@item
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||||
the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
|
||||
@end itemize
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||||
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||||
@node i386-Prefixes
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||||
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|
@ -281,6 +388,20 @@ complete the current instruction. This should never be needed for the
|
|||
The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
|
||||
to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
|
||||
times if the current address size is 16-bits).
|
||||
@cindex REX prefixes, i386
|
||||
@item
|
||||
The @samp{rex} family of prefixes is used by x86-64 to encode
|
||||
extensions to i386 instruction set. The @samp{rex} prefix has four
|
||||
bits --- an operand size overwrite (@code{64}) used to change operand size
|
||||
from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
|
||||
register set.
|
||||
|
||||
You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
|
||||
instruction emits @samp{rex} prefix with all the bits set. By omitting
|
||||
the @code{64}, @code{x}, @code{y} or @code{z} you may write other
|
||||
prefixes as well. Normally, there is no need to write the prefixes
|
||||
explicitly, since gas will automatically generate them based on the
|
||||
instruction operands.
|
||||
@end itemize
|
||||
|
||||
@node i386-Memory
|
||||
|
|
@ -288,6 +409,8 @@ times if the current address size is 16-bits).
|
|||
|
||||
@cindex i386 memory references
|
||||
@cindex memory references, i386
|
||||
@cindex x86-64 memory references
|
||||
@cindex memory references, x86-64
|
||||
An Intel syntax indirect memory reference of the form
|
||||
|
||||
@smallexample
|
||||
|
|
@ -344,14 +467,34 @@ prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
|
|||
always chooses PC relative addressing for jump/call labels.
|
||||
|
||||
Any instruction that has a memory operand, but no register operand,
|
||||
@emph{must} specify its size (byte, word, or long) with an instruction
|
||||
mnemonic suffix (@samp{b}, @samp{w}, or @samp{l}, respectively).
|
||||
@emph{must} specify its size (byte, word, long, or quadruple) with an
|
||||
instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
|
||||
respectively).
|
||||
|
||||
The x86-64 architecture adds an RIP (instruction pointer relative)
|
||||
addressing. This addressing mode is specified by using @samp{rip} as a
|
||||
base register. Only constant offsets are valid. For example:
|
||||
|
||||
@table @asis
|
||||
@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
|
||||
Points to the address 1234 bytes past the end of the current
|
||||
instruction.
|
||||
|
||||
@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
|
||||
Points to the @code{symbol} in RIP relative way, this is shorter than
|
||||
the default absolute addressing.
|
||||
@end table
|
||||
|
||||
Other addressing modes remain unchanged in x86-64 architecture, except
|
||||
registers used are 64-bit instead of 32-bit.
|
||||
|
||||
@node i386-jumps
|
||||
@section Handling of Jump Instructions
|
||||
|
||||
@cindex jump optimization, i386
|
||||
@cindex i386 jump optimization
|
||||
@cindex jump optimization, x86-64
|
||||
@cindex x86-64 jump optimization
|
||||
Jump instructions are always optimized to use the smallest possible
|
||||
displacements. This is accomplished by using byte (8-bit) displacement
|
||||
jumps whenever the target is sufficiently close. If a byte displacement
|
||||
|
|
@ -380,6 +523,8 @@ cx_nonzero:
|
|||
|
||||
@cindex i386 floating point
|
||||
@cindex floating point, i386
|
||||
@cindex x86-64 floating point
|
||||
@cindex floating point, x86-64
|
||||
All 80387 floating point types except packed BCD are supported.
|
||||
(BCD support may be added without much difficulty). These data
|
||||
types are 16-, 32-, and 64- bit integers, and single (32-bit),
|
||||
|
|
@ -392,6 +537,10 @@ data type. Constructors build these data types into memory.
|
|||
@cindex @code{single} directive, i386
|
||||
@cindex @code{double} directive, i386
|
||||
@cindex @code{tfloat} directive, i386
|
||||
@cindex @code{float} directive, x86-64
|
||||
@cindex @code{single} directive, x86-64
|
||||
@cindex @code{double} directive, x86-64
|
||||
@cindex @code{tfloat} directive, x86-64
|
||||
@itemize @bullet
|
||||
@item
|
||||
Floating point constructors are @samp{.float} or @samp{.single},
|
||||
|
|
@ -405,6 +554,10 @@ top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
|
|||
@cindex @code{long} directive, i386
|
||||
@cindex @code{int} directive, i386
|
||||
@cindex @code{quad} directive, i386
|
||||
@cindex @code{word} directive, x86-64
|
||||
@cindex @code{long} directive, x86-64
|
||||
@cindex @code{int} directive, x86-64
|
||||
@cindex @code{quad} directive, x86-64
|
||||
@item
|
||||
Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
|
||||
@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
|
||||
|
|
@ -428,6 +581,9 @@ then stores the result in the 4 byte location @samp{mem})
|
|||
@cindex MMX, i386
|
||||
@cindex 3DNow!, i386
|
||||
@cindex SIMD, i386
|
||||
@cindex MMX, x86-64
|
||||
@cindex 3DNow!, x86-64
|
||||
@cindex SIMD, x86-64
|
||||
|
||||
@code{@value{AS}} supports Intel's MMX instruction set (SIMD
|
||||
instructions for integer data), available on Intel's Pentium MMX
|
||||
|
|
@ -457,7 +613,10 @@ instructions is reversed from the Intel syntax.
|
|||
@cindex @code{code16gcc} directive, i386
|
||||
@cindex @code{code16} directive, i386
|
||||
@cindex @code{code32} directive, i386
|
||||
While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code,
|
||||
@cindex @code{code64} directive, i386
|
||||
@cindex @code{code64} directive, x86-64
|
||||
While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
|
||||
or 64-bit x86-64 code depending on the default configuration,
|
||||
it also supports writing code to run in real mode or in 16-bit protected
|
||||
mode code segments. To do this, put a @samp{.code16} or
|
||||
@samp{.code16gcc} directive before the assembly language instructions to
|
||||
|
|
@ -522,6 +681,8 @@ register is @samp{%st(i)}.
|
|||
|
||||
@cindex arch directive, i386
|
||||
@cindex i386 arch directive
|
||||
@cindex arch directive, x86-64
|
||||
@cindex x86-64 arch directive
|
||||
|
||||
@code{@value{AS}} may be told to assemble for a particular CPU
|
||||
architecture with the @code{.arch @var{cpu_type}} directive. This
|
||||
|
|
@ -531,7 +692,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
|
|||
@multitable @columnfractions .20 .20 .20 .20
|
||||
@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
|
||||
@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
|
||||
@item @samp{pentiumpro} @tab @samp{k6} @tab @samp{athlon}
|
||||
@item @samp{pentiumpro} @tab @samp {pentium4} @tab @samp {k6} @tab @samp {athlon}
|
||||
@item @samp{sledgehammer}
|
||||
@end multitable
|
||||
|
||||
Apart from the warning, there is only one other effect on
|
||||
|
|
@ -548,8 +710,10 @@ explicitly request the two byte opcode by writing @samp{sarl %eax}.
|
|||
@cindex i386 @code{mul}, @code{imul} instructions
|
||||
@cindex @code{mul} instruction, i386
|
||||
@cindex @code{imul} instruction, i386
|
||||
@cindex @code{mul} instruction, x86-64
|
||||
@cindex @code{imul} instruction, x86-64
|
||||
There is some trickery concerning the @samp{mul} and @samp{imul}
|
||||
instructions that deserves mention. The 16-, 32-, and 64-bit expanding
|
||||
instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
|
||||
multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
|
||||
for @samp{imul}) can be output only in the one operand form. Thus,
|
||||
@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
|
||||
|
|
|
|||
Loading…
Reference in a new issue