Merge SH4 branch simulator in to devo.
This commit is contained in:
Andrew Cagney
parent
52352d38d6
commit
4de6b5d361
4 changed files with 1964 additions and 362 deletions
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@ -40,4 +40,34 @@ Things-to-lose:
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Do-last:
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sh4_files="ChangeLog interp.c gencode.c"
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if ( echo $* | grep keep\-sh4 > /dev/null ) ; then
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for i in $sh4_files ; do
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if test ! -d $i && (grep sanitize-sh4 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Keeping sh4 stuff in $i
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fi
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fi
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done
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else
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for i in * ; do
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if test ! -d $i && (grep sanitize-sh4 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Removing traces of \"sh4\" from $i...
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fi
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cp $i new
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sed '/start\-sanitize\-sh4/,/end-\sanitize\-sh4/d' < $i > new
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if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
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if [ -n "${verbose}" ] ; then
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echo Caching $i in .Recover...
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fi
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mv $i .Recover
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fi
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mv new $i
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fi
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done
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fi
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# End of file.
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115
sim/sh/ChangeLog
115
sim/sh/ChangeLog
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@ -1,3 +1,7 @@
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Tue Sep 2 13:15:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* gencode.c (tab): Order instructions according to SH3 document.
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Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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@ -19,6 +23,117 @@ Mon Aug 25 16:17:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_open): Add ABFD argument.
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Mon Jun 23 15:49:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (get_dr): Avoid SIGFPE by moving integers instead of
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FP's around.
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(set_dr): Ditto.
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start-sanitize-sh4
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Mon Jun 23 15:02:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (XD, SET_XD): Delete.
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(XF, SET_XF, XD_TO_XF): Define, move around registers in either
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FP bank.
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* gencode.c (fmov): Update.
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end-sanitize-sh4
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Sun Jun 22 19:33:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (set_fpscr1): From J"orn Rennecke
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<amylaar@cygnus.co.uk>, Fix typo. Ditto for comment.
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start-sanitize-sh4
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Tue Aug 12 00:19:11 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
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* interp.c (special_address): New function.
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(BUSERROR): Call it. Added parameters bits_written and data.
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Changed all callers.
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* gencode.c (tab): Fixed ocbwb and pref.
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end-sanitize-sh4
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start-sanitize-sh4
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Fri Jun 20 22:03:18 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
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* interp.c (do_wdat, do_wdat): Fix bug in register number calculation.
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end-sanitize-sh4
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Thu Jun 19 00:28:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_create_inferior): Clear registers each time an
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inferior is started.
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start-sanitize-sh4
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Mon Jun 16 14:01:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (*FP, FP_OP, FP_CMP, FP_UNARY): Provide a hook for
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when a host doesn't support IEEE FP.
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(*DP): Provide alternative definition that supports 64bit floating
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point.
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(target_little_endian): Combine little_endian and little_endian_p.
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(saved_state_type): Make fpscr and sr simple integers.
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(SET_FPSCR, GET_FPSCR): Use macros to update fpscr register.
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(set_fpscr1): New function. Handle swapping when PR / FR bits
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changed. Call via *_FPSCR macro.
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(SET_SR*, GET_SR*): Use macro's to access the SR bits - avoids
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endian problems.
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* gencode.c (tab): Update.
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end-sanitize-sh4
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Sun Jun 15 15:22:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* gencode.c (main): Perform basic checks on tab entries.
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* Makefile.in (gencode): Always compile with -g.
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Sat Jun 14 13:45:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* gencode.c (gensim): Move ref checking code to before `stuff'.
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For branches with delay slots refs were not being checked.
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* interp.c (sim_resume): Use nia to specify the next instruction
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address instead of overloading pc.
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(C): Delete definiton - refer to cycles directly.
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(SEXT12): New macro - sign extend a 12 bit quantity.
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(Delay_Slot): Rename from SL.
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* gencode.c (tab): Update/simplify.
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* gencode.c (gensim): Better formatting of output code.
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(gensim): Replace 10 with constant MAX_NR_STUFF- define as 15.
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(tab): Sort alphabetically. Break `stuff' into multiple lines.
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Fri Jun 13 22:10:13 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
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* gencode.c (braf, bsrf): Fix branch destination calculation to
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be in accordance with the documentation.
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Fri Jun 13 15:33:53 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
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* interp.c (init_pointers): Fix little endian test.
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start-sanitize-sh4
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Thu Jun 5 12:56:08 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
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* interp.c (init_pointers): SH4 hardware is always WORDS_BIT_ENDIAN.
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* gencode (fmov from/to memory): take endian_mismatch into account
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for 32 bit moves too.
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end-sanitize-sh4
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Wed May 28 23:42:35 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
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* gencode.c (swap.b): Fix treatment of high word.
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start-sanitize-sh4
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Wed May 28 23:42:35 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
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* sh/gencode.c,
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* interp.c: experimental SH4 support. Lacks sanitation.
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DFmode moves are probaly broken for target little endian.
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end-sanitize-sh4
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Tue May 20 10:23:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_open): Add callback argument.
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1607
sim/sh/gencode.c
1607
sim/sh/gencode.c
File diff suppressed because it is too large
Load diff
574
sim/sh/interp.c
574
sim/sh/interp.c
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@ -56,6 +56,92 @@
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#define DEFINE_TABLE
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#define DISASSEMBLER_TABLE
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typedef union
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{
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struct
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{
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int regs[16];
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int pc;
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int pr;
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int gbr;
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int vbr;
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int mach;
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int macl;
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int sr;
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int fpul;
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int fpscr;
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/* sh3e */
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union fregs_u
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{
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float f[16];
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double d[8];
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int i[16];
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}
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/* start-sanitize-sh4 */
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#if 1
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fregs[2];
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#else
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/* end-sanitize-sh4 */
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fregs;
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/* start-sanitize-sh4 */
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#endif
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/* end-sanitize-sh4 */
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int ssr;
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int spc;
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/* sh3 */
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int bank[2][8];
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int ticks;
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int stalls;
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int memstalls;
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int cycles;
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int insts;
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int prevlock;
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int thislock;
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int exception;
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int end_of_registers;
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int msize;
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#define PROFILE_FREQ 1
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#define PROFILE_SHIFT 2
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int profile;
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unsigned short *profile_hist;
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unsigned char *memory;
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}
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asregs;
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int asints[28];
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} saved_state_type;
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saved_state_type saved_state;
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/* These variables are at file scope so that functions other than
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sim_resume can use the fetch/store macros */
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static int target_little_endian;
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static int host_little_endian;
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#if 1
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static int maskl = ~0;
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static int maskw = ~0;
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#endif
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static SIM_OPEN_KIND sim_kind;
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static char *myname;
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/* Short hand definitions of the registers */
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#define SBIT(x) ((x)&sbit)
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#define R0 saved_state.asregs.regs[0]
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#define Rn saved_state.asregs.regs[n]
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@ -70,21 +156,118 @@
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#define SPC saved_state.asregs.spc
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#define MACH saved_state.asregs.mach
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#define MACL saved_state.asregs.macl
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#define M saved_state.asregs.sr.bits.m
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#define Q saved_state.asregs.sr.bits.q
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#define S saved_state.asregs.sr.bits.s
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#define FPSCR saved_state.asregs.fpscr
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#define FPUL saved_state.asregs.fpul
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#define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word)
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#define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;}
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#define PC pc
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#define C cycles
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static SIM_OPEN_KIND sim_kind;
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static char *myname;
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static int little_endian_p;
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/* Alternate bank of registers r0-r6 */
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/* Note: code controling SR handles flips between BANK0 and BANK1 */
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#define Rn_BANK(n) (saved_state.asregs.bank[!SR_RB][(n)])
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#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[!SR_RB][(n)] = (EXP); } while (0)
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/* Manipulate SR */
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#define SR_MASK_M (1 << 9)
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#define SR_MASK_Q (1 << 8)
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#define SR_MASK_I (0xf << 4)
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#define SR_MASK_S (1 << 1)
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#define SR_MASK_T (1 << 0)
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#define SR_MASK_BL (1 << 28)
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#define SR_MASK_RB (1 << 29)
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#define SR_MASK_MD (1 << 30)
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#define M ((saved_state.asregs.sr & SR_MASK_M) != 0)
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#define Q ((saved_state.asregs.sr & SR_MASK_Q) != 0)
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#define S ((saved_state.asregs.sr & SR_MASK_S) != 0)
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#define T ((saved_state.asregs.sr & SR_MASK_T) != 0)
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#define SR_BL ((saved_state.asregs.sr & SR_MASK_BL) != 0)
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#define SR_RB ((saved_state.asregs.sr & SR_MASK_RB) != 0)
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#define SR_MD ((saved_state.asregs.sr & SR_MASK_MD) != 0)
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/* Note: don't use this for privileged bits */
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#define SET_SR_BIT(EXP, BIT) \
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do { \
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if ((EXP) & 1) \
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saved_state.asregs.sr |= (BIT); \
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else \
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saved_state.asregs.sr &= ~(BIT); \
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} while (0)
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#define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
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#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
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#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
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#define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
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#define GET_SR() (saved_state.asregs.sr - 0)
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#define SET_SR(x) set_sr (x)
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static void
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set_sr (new_sr)
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int new_sr;
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{
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/* do we need to swap banks */
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int old_gpr = (SR_MD ? !SR_RB : 0);
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int new_gpr = ((new_sr & SR_MASK_MD)
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? (new_sr & SR_MASK_RB) == 0
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: 0);
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if (old_gpr != new_gpr)
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{
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int i;
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for (i = 0; i < 8; i++)
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{
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saved_state.asregs.bank[old_gpr][i] = saved_state.asregs.regs[i];
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saved_state.asregs.regs[i] = saved_state.asregs.bank[new_gpr][i];
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}
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}
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}
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/* Manipulate FPSCR */
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/* start-sanitize-sh4 */
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#if 1
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#define FPSCR_MASK_FR (1 << 21)
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#define FPSCR_MASK_SZ (1 << 20)
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#define FPSCR_MASK_PR (1 << 19)
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#define FPSCR_FR ((GET_FPSCR() & FPSCR_MASK_FR) != 0)
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#define FPSCR_SZ ((GET_FPSCR() & FPSCR_MASK_SZ) != 0)
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#define FPSCR_PR ((GET_FPSCR() & FPSCR_MASK_PR) != 0)
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static void
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set_fpscr1 (x)
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int x;
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{
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int old = saved_state.asregs.fpscr;
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saved_state.asregs.fpscr = (x);
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/* swap the floating point register banks */
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if ((saved_state.asregs.fpscr ^ old) & FPSCR_MASK_FR)
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{
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union fregs_u tmpf = saved_state.asregs.fregs[0];
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saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
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saved_state.asregs.fregs[1] = tmpf;
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}
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}
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#define GET_FPSCR() (saved_state.asregs.fpscr)
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#define SET_FPSCR(x) \
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do { \
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set_fpscr1 (x); \
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} while (0)
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#else
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/* end-sanitize-sh4 */
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#define set_fpscr1(x)
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#define SET_FPSCR(x) (saved_state.asregs.fpscr = (x))
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#define GET_FPSCR() (saved_state.asregs.fpscr)
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/* start-sanitize-sh4 */
|
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#endif
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||||
/* end-sanitize-sh4 */
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||||
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int
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fail ()
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|
|
@ -92,6 +275,21 @@ fail ()
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abort ();
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}
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|
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int
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special_address (addr, bits_written, data)
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void *addr;
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int bits_written, data;
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{
|
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if ((unsigned) addr >> 24 == 0xf0 && bits_written == 32 && (data & 1) == 0)
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/* This invalidates (if not associative) or might invalidate
|
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(if assiciative) an instruction cache line. This is used for
|
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trampolines. Since we don't simulate the cache, this is a no-op
|
||||
as far as the simulator is concerned. */
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return 1;
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/* We can't do anything useful with the other stuff, so fail. */
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return 0;
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}
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|
||||
/* This function exists solely for the purpose of setting a breakpoint to
|
||||
catch simulated bus errors when running the simulator under GDB. */
|
||||
|
||||
|
|
@ -100,8 +298,18 @@ bp_holder ()
|
|||
{
|
||||
}
|
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|
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#define BUSERROR(addr, mask) \
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if (addr & ~mask) { saved_state.asregs.exception = SIGBUS; bp_holder (); }
|
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/* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
|
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being implemented by ../common/sim_resume.c and the below should
|
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make a call to sim_engine_halt */
|
||||
|
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#define BUSERROR(addr, mask, bits_written, data) \
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if (addr & ~mask) \
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{ \
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if (special_address (addr, bits_written, data)) \
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return; \
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saved_state.asregs.exception = SIGBUS; \
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bp_holder (); \
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}
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||||
|
||||
/* Define this to enable register lifetime checking.
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The compiler generates "add #0,rn" insns to mark registers as invalid,
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|
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@ -128,76 +336,122 @@ static int IOMEM PARAMS ((int addr, int write, int value));
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|
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static host_callback *callback;
|
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|
||||
/* These variables are at file scope so that functions other than
|
||||
sim_resume can use the fetch/store macros */
|
||||
|
||||
static int little_endian;
|
||||
|
||||
/* Floating point registers */
|
||||
|
||||
/* start-sanitize-sh4 */
|
||||
#if 1
|
||||
static int maskl = ~0;
|
||||
static int maskw = ~0;
|
||||
#endif
|
||||
typedef union
|
||||
|
||||
#define DR(n) (get_dr (n))
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static double
|
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get_dr (n)
|
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int n;
|
||||
{
|
||||
|
||||
struct
|
||||
{
|
||||
|
||||
int regs[16];
|
||||
int pc;
|
||||
int pr;
|
||||
|
||||
int gbr;
|
||||
int vbr;
|
||||
int mach;
|
||||
int macl;
|
||||
|
||||
union
|
||||
n = (n & ~1);
|
||||
if (host_little_endian)
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int d0:22;
|
||||
unsigned int m:1;
|
||||
unsigned int q:1;
|
||||
unsigned int i:4;
|
||||
unsigned int d1:2;
|
||||
unsigned int s:1;
|
||||
unsigned int t:1;
|
||||
}
|
||||
bits;
|
||||
int word;
|
||||
}
|
||||
sr;
|
||||
int i[2];
|
||||
double d;
|
||||
} dr;
|
||||
dr.i[1] = saved_state.asregs.fregs[0].i[n + 0];
|
||||
dr.i[0] = saved_state.asregs.fregs[0].i[n + 1];
|
||||
return dr.d;
|
||||
}
|
||||
else
|
||||
return (saved_state.asregs.fregs[0].d[n >> 1]);
|
||||
}
|
||||
|
||||
int fpul;
|
||||
float fpscr;
|
||||
float fregs[16];
|
||||
#define SET_DR(n, EXP) set_dr ((n), (EXP))
|
||||
static void
|
||||
set_dr (n, exp)
|
||||
int n;
|
||||
double exp;
|
||||
{
|
||||
n = (n & ~1);
|
||||
if (host_little_endian)
|
||||
{
|
||||
union
|
||||
{
|
||||
int i[2];
|
||||
double d;
|
||||
} dr;
|
||||
dr.d = exp;
|
||||
saved_state.asregs.fregs[0].i[n + 0] = dr.i[1];
|
||||
saved_state.asregs.fregs[0].i[n + 1] = dr.i[0];
|
||||
}
|
||||
else
|
||||
saved_state.asregs.fregs[0].d[n >> 1] = exp;
|
||||
}
|
||||
|
||||
int ssr;
|
||||
int spc;
|
||||
int bregs[16];
|
||||
#define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
|
||||
#define FI(n) (saved_state.asregs.fregs[0].i[(n)])
|
||||
|
||||
int ticks;
|
||||
int stalls;
|
||||
int memstalls;
|
||||
int cycles;
|
||||
int insts;
|
||||
#define FR(n) (saved_state.asregs.fregs[0].f[(n)])
|
||||
#define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
|
||||
|
||||
#define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
|
||||
#define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
|
||||
#define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
|
||||
|
||||
|
||||
#define FP_OP(n, OP, m) \
|
||||
{ \
|
||||
if (FPSCR_PR) \
|
||||
{ \
|
||||
if (((n) & 1) || ((m) & 1)) \
|
||||
saved_state.asregs.exception = SIGILL; \
|
||||
else \
|
||||
SET_DR(n, (DR(n) OP DR(m))); \
|
||||
} \
|
||||
else \
|
||||
SET_FR(n, (FR(n) OP FR(m))); \
|
||||
} while (0)
|
||||
|
||||
#define FP_UNARY(n, OP) \
|
||||
{ \
|
||||
if (FPSCR_PR) \
|
||||
{ \
|
||||
if ((n) & 1) \
|
||||
saved_state.asregs.exception = SIGILL; \
|
||||
else \
|
||||
SET_DR(n, (OP (DR(n)))); \
|
||||
} \
|
||||
else \
|
||||
SET_FR(n, (OP (FR(n)))); \
|
||||
} while (0)
|
||||
|
||||
#define FP_CMP(n, OP, m) \
|
||||
{ \
|
||||
if (FPSCR_PR) \
|
||||
{ \
|
||||
if (((n) & 1) || ((m) & 1)) \
|
||||
saved_state.asregs.exception = SIGILL; \
|
||||
else \
|
||||
SET_SR_T (DR(n) OP DR(m)); \
|
||||
} \
|
||||
else \
|
||||
SET_SR_T (FR(n) OP FR(m)); \
|
||||
} while (0)
|
||||
|
||||
#else
|
||||
/* end-sanitize-sh4 */
|
||||
#define FI(n) (saved_state.asregs.fregs.i[(n)])
|
||||
#define FR(n) (saved_state.asregs.fregs.f[(n)])
|
||||
|
||||
#define SET_FI(n,EXP) (saved_state.asregs.fregs.i[(n)] = (EXP))
|
||||
#define SET_FR(n,EXP) (saved_state.asregs.fregs.f[(n)] = (EXP))
|
||||
|
||||
#define FP_OP(n, OP, m) (SET_FR(n, (FR(n) OP FR(m))))
|
||||
#define FP_UNARY(n, OP) (SET_FR(n, (OP (FR(n)))))
|
||||
#define FP_CMP(n, OP, m) SET_SR_T(FR(n) OP FR(m))
|
||||
/* start-sanitize-sh4 */
|
||||
#endif
|
||||
/* end-sanitize-sh4 */
|
||||
|
||||
int prevlock;
|
||||
int thislock;
|
||||
int exception;
|
||||
int msize;
|
||||
#define PROFILE_FREQ 1
|
||||
#define PROFILE_SHIFT 2
|
||||
int profile;
|
||||
unsigned short *profile_hist;
|
||||
unsigned char *memory;
|
||||
}
|
||||
asregs;
|
||||
int asints[28];
|
||||
} saved_state_type;
|
||||
|
||||
saved_state_type saved_state;
|
||||
|
||||
static void INLINE
|
||||
wlat_little (memory, x, value, maskl)
|
||||
|
|
@ -205,7 +459,7 @@ wlat_little (memory, x, value, maskl)
|
|||
{
|
||||
int v = value;
|
||||
unsigned char *p = memory + ((x) & maskl);
|
||||
BUSERROR(x, maskl);
|
||||
BUSERROR(x, maskl, 32, v);
|
||||
p[3] = v >> 24;
|
||||
p[2] = v >> 16;
|
||||
p[1] = v >> 8;
|
||||
|
|
@ -218,7 +472,7 @@ wwat_little (memory, x, value, maskw)
|
|||
{
|
||||
int v = value;
|
||||
unsigned char *p = memory + ((x) & maskw);
|
||||
BUSERROR(x, maskw);
|
||||
BUSERROR(x, maskw, 16, v);
|
||||
|
||||
p[1] = v >> 8;
|
||||
p[0] = v;
|
||||
|
|
@ -231,7 +485,7 @@ wbat_any (memory, x, value, maskb)
|
|||
unsigned char *p = memory + (x & maskb);
|
||||
if (x > 0x5000000)
|
||||
IOMEM (x, 1, value);
|
||||
BUSERROR(x, maskb);
|
||||
BUSERROR(x, maskb, 8, value);
|
||||
|
||||
p[0] = value;
|
||||
}
|
||||
|
|
@ -242,7 +496,7 @@ wlat_big (memory, x, value, maskl)
|
|||
{
|
||||
int v = value;
|
||||
unsigned char *p = memory + ((x) & maskl);
|
||||
BUSERROR(x, maskl);
|
||||
BUSERROR(x, maskl, 32, v);
|
||||
|
||||
p[0] = v >> 24;
|
||||
p[1] = v >> 16;
|
||||
|
|
@ -256,7 +510,7 @@ wwat_big (memory, x, value, maskw)
|
|||
{
|
||||
int v = value;
|
||||
unsigned char *p = memory + ((x) & maskw);
|
||||
BUSERROR(x, maskw);
|
||||
BUSERROR(x, maskw, 16, v);
|
||||
|
||||
p[0] = v >> 8;
|
||||
p[1] = v;
|
||||
|
|
@ -267,7 +521,7 @@ wbat_big (memory, x, value, maskb)
|
|||
unsigned char *memory;
|
||||
{
|
||||
unsigned char *p = memory + (x & maskb);
|
||||
BUSERROR(x, maskb);
|
||||
BUSERROR(x, maskb, 8, value);
|
||||
|
||||
if (x > 0x5000000)
|
||||
IOMEM (x, 1, value);
|
||||
|
|
@ -281,7 +535,7 @@ rlat_little (memory, x, maskl)
|
|||
unsigned char *memory;
|
||||
{
|
||||
unsigned char *p = memory + ((x) & maskl);
|
||||
BUSERROR(x, maskl);
|
||||
BUSERROR(x, maskl, -32, -1);
|
||||
|
||||
return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
|
||||
}
|
||||
|
|
@ -291,7 +545,7 @@ rwat_little (memory, x, maskw)
|
|||
unsigned char *memory;
|
||||
{
|
||||
unsigned char *p = memory + ((x) & maskw);
|
||||
BUSERROR(x, maskw);
|
||||
BUSERROR(x, maskw, -16, -1);
|
||||
|
||||
return (p[1] << 8) | p[0];
|
||||
}
|
||||
|
|
@ -301,7 +555,7 @@ rbat_any (memory, x, maskb)
|
|||
unsigned char *memory;
|
||||
{
|
||||
unsigned char *p = memory + ((x) & maskb);
|
||||
BUSERROR(x, maskb);
|
||||
BUSERROR(x, maskb, -8, -1);
|
||||
|
||||
return p[0];
|
||||
}
|
||||
|
|
@ -311,7 +565,6 @@ rlat_big (memory, x, maskl)
|
|||
unsigned char *memory;
|
||||
{
|
||||
unsigned char *p = memory + ((x) & maskl);
|
||||
BUSERROR(x, maskl);
|
||||
|
||||
return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
|
||||
}
|
||||
|
|
@ -321,7 +574,7 @@ rwat_big (memory, x, maskw)
|
|||
unsigned char *memory;
|
||||
{
|
||||
unsigned char *p = memory + ((x) & maskw);
|
||||
BUSERROR(x, maskw);
|
||||
BUSERROR(x, maskw, -16, -1);
|
||||
|
||||
return (p[0] << 8) | p[1];
|
||||
}
|
||||
|
|
@ -337,12 +590,72 @@ rwat_big (memory, x, maskw)
|
|||
#define RSWAT(x) ((short)(RWAT(x)))
|
||||
#define RSBAT(x) (SEXT(RBAT(x)))
|
||||
|
||||
#define MA() ((pc & 3) != 0 ? ++memstalls : 0)
|
||||
/* start-sanitize-sh4 */
|
||||
#define RDAT(x, n) (do_rdat (memory, (x), (n), (little_endian)))
|
||||
static int
|
||||
do_rdat (memory, x, n, little_endian)
|
||||
char *memory;
|
||||
int x;
|
||||
int n;
|
||||
int little_endian;
|
||||
{
|
||||
int f0;
|
||||
int f1;
|
||||
int i = (n & 1);
|
||||
int j = (n & ~1);
|
||||
if (little_endian)
|
||||
{
|
||||
f0 = rlat_little (memory, x + 0, maskl);
|
||||
f1 = rlat_little (memory, x + 4, maskl);
|
||||
}
|
||||
else
|
||||
{
|
||||
f0 = rlat_big (memory, x + 0, maskl);
|
||||
f1 = rlat_big (memory, x + 4, maskl);
|
||||
}
|
||||
saved_state.asregs.fregs[i].i[(j + 0)] = f0;
|
||||
saved_state.asregs.fregs[i].i[(j + 1)] = f1;
|
||||
return 0;
|
||||
}
|
||||
/* end-sanitize-sh4 */
|
||||
|
||||
#define SEXT(x) (((x&0xff) ^ (~0x7f))+0x80)
|
||||
/* start-sanitize-sh4 */
|
||||
#define WDAT(x, n) (do_wdat (memory, (x), (n), (little_endian)))
|
||||
static int
|
||||
do_wdat (memory, x, n, little_endian)
|
||||
char *memory;
|
||||
int x;
|
||||
int n;
|
||||
int little_endian;
|
||||
{
|
||||
int f0;
|
||||
int f1;
|
||||
int i = (n & 1);
|
||||
int j = (n & ~1);
|
||||
f0 = saved_state.asregs.fregs[i].i[(j + 0)];
|
||||
f1 = saved_state.asregs.fregs[i].i[(j + 1)];
|
||||
if (little_endian)
|
||||
{
|
||||
wlat_little (memory, (x + 0), f0, maskl);
|
||||
wlat_little (memory, (x + 4), f1, maskl);
|
||||
}
|
||||
else
|
||||
{
|
||||
wlat_big (memory, (x + 0), f0, maskl);
|
||||
wlat_big (memory, (x + 4), f1, maskl);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
/* end-sanitize-sh4 */
|
||||
|
||||
|
||||
#define MA(n) do { memstalls += (((pc & 3) != 0) ? (n) : ((n) - 1)); } while (0)
|
||||
|
||||
#define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
|
||||
#define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
|
||||
#define SEXTW(y) ((int)((short)y))
|
||||
|
||||
#define SL(TEMPPC) iword= RUWAT(TEMPPC); goto top;
|
||||
#define Delay_Slot(TEMPPC) iword = RUWAT(TEMPPC); goto top;
|
||||
|
||||
int empty[16];
|
||||
|
||||
|
|
@ -421,6 +734,7 @@ swap (memory, n)
|
|||
unsigned char *memory;
|
||||
int n;
|
||||
{
|
||||
int little_endian = target_little_endian;
|
||||
WLAT (0, n);
|
||||
}
|
||||
|
||||
|
|
@ -429,6 +743,7 @@ swap16 (memory, n)
|
|||
unsigned char *memory;
|
||||
int n;
|
||||
{
|
||||
int little_endian = target_little_endian;
|
||||
WWAT (0, n);
|
||||
}
|
||||
|
||||
|
|
@ -627,17 +942,17 @@ control_c (sig, code, scp, addr)
|
|||
}
|
||||
|
||||
static int
|
||||
div1 (R, iRn2, iRn1, T)
|
||||
div1 (R, iRn2, iRn1/*, T*/)
|
||||
int *R;
|
||||
int iRn1;
|
||||
int iRn2;
|
||||
int T;
|
||||
/* int T;*/
|
||||
{
|
||||
unsigned long tmp0;
|
||||
unsigned char old_q, tmp1;
|
||||
|
||||
old_q = Q;
|
||||
Q = (unsigned char) ((0x80000000 & R[iRn1]) != 0);
|
||||
SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0));
|
||||
R[iRn1] <<= 1;
|
||||
R[iRn1] |= (unsigned long) T;
|
||||
|
||||
|
|
@ -653,10 +968,10 @@ div1 (R, iRn2, iRn1, T)
|
|||
switch (Q)
|
||||
{
|
||||
case 0:
|
||||
Q = tmp1;
|
||||
SET_SR_Q (tmp1);
|
||||
break;
|
||||
case 1:
|
||||
Q = (unsigned char) (tmp1 == 0);
|
||||
SET_SR_Q ((unsigned char) (tmp1 == 0));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
|
@ -667,10 +982,10 @@ div1 (R, iRn2, iRn1, T)
|
|||
switch (Q)
|
||||
{
|
||||
case 0:
|
||||
Q = (unsigned char) (tmp1 == 0);
|
||||
SET_SR_Q ((unsigned char) (tmp1 == 0));
|
||||
break;
|
||||
case 1:
|
||||
Q = tmp1;
|
||||
SET_SR_Q (tmp1);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
|
@ -686,10 +1001,10 @@ div1 (R, iRn2, iRn1, T)
|
|||
switch (Q)
|
||||
{
|
||||
case 0:
|
||||
Q = tmp1;
|
||||
SET_SR_Q (tmp1);
|
||||
break;
|
||||
case 1:
|
||||
Q = (unsigned char) (tmp1 == 0);
|
||||
SET_SR_Q ((unsigned char) (tmp1 == 0));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
|
@ -700,18 +1015,19 @@ div1 (R, iRn2, iRn1, T)
|
|||
switch (Q)
|
||||
{
|
||||
case 0:
|
||||
Q = (unsigned char) (tmp1 == 0);
|
||||
SET_SR_Q ((unsigned char) (tmp1 == 0));
|
||||
break;
|
||||
case 1:
|
||||
Q = tmp1;
|
||||
SET_SR_Q (tmp1);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
T = (Q == M);
|
||||
return T;
|
||||
/*T = (Q == M);*/
|
||||
SET_SR_T (Q == M);
|
||||
/*return T;*/
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -761,6 +1077,7 @@ macw (regs, memory, n, m)
|
|||
unsigned char *memory;
|
||||
int m, n;
|
||||
{
|
||||
int little_endian = target_little_endian;
|
||||
long tempm, tempn;
|
||||
long prod, macl, sum;
|
||||
|
||||
|
|
@ -822,19 +1139,12 @@ sim_size (power)
|
|||
}
|
||||
}
|
||||
|
||||
static void
|
||||
set_static_little_endian (x)
|
||||
int x;
|
||||
{
|
||||
little_endian = x;
|
||||
}
|
||||
|
||||
static void
|
||||
init_pointers ()
|
||||
{
|
||||
int little_endian = little_endian_p;
|
||||
|
||||
set_static_little_endian (little_endian);
|
||||
host_little_endian = 0;
|
||||
*(char*)&host_little_endian = 1;
|
||||
host_little_endian &= 1;
|
||||
|
||||
if (saved_state.asregs.msize != 1 << sim_memory_size)
|
||||
{
|
||||
|
|
@ -916,17 +1226,17 @@ sim_resume (sd, step, siggnal)
|
|||
register int thislock;
|
||||
register unsigned int doprofile;
|
||||
register int pollcount = 0;
|
||||
register int little_endian = little_endian_p;
|
||||
register int little_endian = target_little_endian;
|
||||
|
||||
int tick_start = get_now ();
|
||||
void (*prev) ();
|
||||
void (*prev_fpe) ();
|
||||
extern unsigned char sh_jump_table0[];
|
||||
|
||||
register unsigned char *jump_table = sh_jump_table0;
|
||||
|
||||
register int *R = &(saved_state.asregs.regs[0]);
|
||||
register float *F = &(saved_state.asregs.fregs[0]);
|
||||
register int T;
|
||||
/*register int T;*/
|
||||
register int PR;
|
||||
|
||||
register int maskb = ((saved_state.asregs.msize - 1) & ~0);
|
||||
|
|
@ -936,6 +1246,7 @@ sim_resume (sd, step, siggnal)
|
|||
register unsigned int sbit = ((unsigned int) 1 << 31);
|
||||
|
||||
prev = signal (SIGINT, control_c);
|
||||
prev_fpe = signal (SIGFPE, SIG_IGN);
|
||||
|
||||
init_pointers ();
|
||||
|
||||
|
|
@ -952,7 +1263,7 @@ sim_resume (sd, step, siggnal)
|
|||
|
||||
pc = saved_state.asregs.pc;
|
||||
PR = saved_state.asregs.pr;
|
||||
T = saved_state.asregs.sr.bits.t;
|
||||
/*T = GET_SR () & SR_MASK_T;*/
|
||||
prevlock = saved_state.asregs.prevlock;
|
||||
thislock = saved_state.asregs.thislock;
|
||||
doprofile = saved_state.asregs.profile;
|
||||
|
|
@ -966,6 +1277,7 @@ sim_resume (sd, step, siggnal)
|
|||
{
|
||||
register unsigned int iword = RUWAT (pc);
|
||||
register unsigned int ult;
|
||||
register unsigned int nia = pc + 2;
|
||||
#ifndef ACE_FAST
|
||||
insts++;
|
||||
#endif
|
||||
|
|
@ -974,7 +1286,7 @@ sim_resume (sd, step, siggnal)
|
|||
#include "code.c"
|
||||
|
||||
|
||||
pc += 2;
|
||||
pc = nia;
|
||||
|
||||
pollcount++;
|
||||
if (pollcount > 1000)
|
||||
|
|
@ -1025,7 +1337,8 @@ sim_resume (sd, step, siggnal)
|
|||
saved_state.asregs.memstalls += memstalls;
|
||||
saved_state.asregs.insts += insts;
|
||||
saved_state.asregs.pc = pc;
|
||||
saved_state.asregs.sr.bits.t = T;
|
||||
/* restore the T and other cached SR bits */
|
||||
SET_SR (GET_SR());
|
||||
saved_state.asregs.pr = PR;
|
||||
|
||||
saved_state.asregs.prevlock = prevlock;
|
||||
|
|
@ -1036,6 +1349,7 @@ sim_resume (sd, step, siggnal)
|
|||
dump_profile ();
|
||||
}
|
||||
|
||||
signal (SIGFPE, prev_fpe);
|
||||
signal (SIGINT, prev);
|
||||
}
|
||||
|
||||
|
|
@ -1081,8 +1395,14 @@ sim_store_register (sd, rn, memory)
|
|||
int rn;
|
||||
unsigned char *memory;
|
||||
{
|
||||
int little_endian;
|
||||
init_pointers ();
|
||||
saved_state.asregs.regs[rn] = RLAT(0);
|
||||
little_endian = target_little_endian;
|
||||
if (&saved_state.asints[rn]
|
||||
== &saved_state.asregs.fpscr)
|
||||
set_fpscr1 (RLAT(0));
|
||||
else
|
||||
saved_state.asints[rn] = RLAT(0);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -1091,8 +1411,10 @@ sim_fetch_register (sd, rn, memory)
|
|||
int rn;
|
||||
unsigned char *memory;
|
||||
{
|
||||
int little_endian;
|
||||
init_pointers ();
|
||||
WLAT (0, saved_state.asregs.regs[rn]);
|
||||
little_endian = target_little_endian;
|
||||
WLAT (0, saved_state.asints[rn]);
|
||||
}
|
||||
|
||||
int
|
||||
|
|
@ -1197,7 +1519,7 @@ sim_open (kind, cb, abfd, argv)
|
|||
callback->printf_filtered (callback, "Missing argument to `-E'.\n");
|
||||
return 0;
|
||||
}
|
||||
little_endian_p = strcmp (*p, "big") != 0;
|
||||
target_little_endian = strcmp (*p, "big") != 0;
|
||||
}
|
||||
else if (isdigit (**p))
|
||||
parse_and_set_memory_size (*p);
|
||||
|
|
@ -1248,16 +1570,18 @@ sim_load (sd, prog, abfd, from_tty)
|
|||
}
|
||||
|
||||
SIM_RC
|
||||
sim_create_inferior (sd, abfd, argv, env)
|
||||
sim_create_inferior (sd, prog_bfd, argv, env)
|
||||
SIM_DESC sd;
|
||||
struct _bfd *abfd;
|
||||
struct _bfd *prog_bfd;
|
||||
char **argv;
|
||||
char **env;
|
||||
{
|
||||
if (abfd != NULL)
|
||||
saved_state.asregs.pc = bfd_get_start_address (abfd);
|
||||
else
|
||||
saved_state.asregs.pc = 0;
|
||||
/* clear the registers (retaining the PC) */
|
||||
memset (&saved_state, 0,
|
||||
(char*)&saved_state.asregs.end_of_registers - (char*)&saved_state);
|
||||
/* set the PC */
|
||||
if (prog_bfd != NULL)
|
||||
saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
|
||||
return SIM_RC_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue