Add support to AArch64 disassembler for verifying instructions. Add verifier for LDPSW.

PR target/19722
opcodes	* aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
	* aarch64-opc.c (verify_ldpsw): New function.
	* aarch64-opc.h (verify_ldpsw): New prototype.
	* aarch64-tbl.h: Add initialiser for verifier field.
	(LDPSW): Set verifier to verify_ldpsw.

binutils* testsuite/binutils-all/aarch64/illegal.s: New test.
	* testsuite/binutils-all/aarch64/illegal.d: New test driver.

include	* opcode/aarch64.h (struct aarch64_opcode): Add verifier field.

binutils/ChangeLog

@@ -1,3 +1,9 @@
+2016-04-28  Nick Clifton  <nickc@redhat.com>
+
+	PR target/19722
+	* testsuite/binutils-all/aarch64/illegal.s: New test.
+	* testsuite/binutils-all/aarch64/illegal.d: New test driver.
+
 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 
 	* resres.c: Likewise.

binutils/testsuite/binutils-all/aarch64/illegal.d

@@ -0,0 +1,12 @@
+#PROG: objcopy
+#objdump: -d
+#name: Check that the disassembler complains about illegal instructions.
+
+.*: +file format .*aarch64.*
+
+Disassembly of section \.text:
+
+0+000 <.*>:
+[ 	]+0:[ 	]+68ea18cc[ 	]+.inst[ 	]+0x68ea18cc ; undefined
+#pass
+

binutils/testsuite/binutils-all/aarch64/illegal.s

@@ -0,0 +1,7 @@
+	# Test disassembly of illegal instructions.
+	.text
+	
+	# ldpsw   x12, x6, [x6],#-8 ; illegal because one of the dest regs is also the address reg
+	.inst 0x68ea18cc
+
+	# FIXME: Add more illegal instructions here.

include/ChangeLog

@@ -1,3 +1,8 @@
+2016-04-28  Nick Clifton  <nickc@redhat.com>
+
+	PR target/19722
+	* opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
+
 2016-04-27  Alan Modra  <amodra@gmail.com>
 
 	* bfdlink.h (struct bfd_link_hash_entry): Add "section" field to

include/opcode/aarch64.h

@@ -535,6 +535,9 @@ struct aarch64_opcode
 
   /* Flags providing information about this instruction */
   uint32_t flags;
+
+  /* If non-NULL, a function to verify that a given instruction is valid.  */
+  bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 };
 
 typedef struct aarch64_opcode aarch64_opcode;

opcodes/ChangeLog

@@ -1,3 +1,12 @@
+2016-04-28  Nick Clifton  <nickc@redhat.com>
+
+	PR target/19722
+	* aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
+	* aarch64-opc.c (verify_ldpsw): New function.
+	* aarch64-opc.h (verify_ldpsw): New prototype.
+	* aarch64-tbl.h: Add initialiser for verifier field.
+	(LDPSW): Set verifier to verify_ldpsw.
+
 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR binutils/19983

opcodes/aarch64-dis.c

@@ -2047,6 +2047,7 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
     {
       const aarch64_operand *opnd;
       enum aarch64_opnd type;
+
       type = opcode->operands[i];
       if (type == AARCH64_OPND_NIL)
 	break;
@@ -2059,6 +2060,13 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
 	}
     }
 
+  /* If the opcode has a verifier, then check it now.  */
+  if (opcode->verifier && ! opcode->verifier (opcode, code))
+    {
+      DEBUG_TRACE ("operand verifier FAIL");
+      goto decode_fail;
+    }
+
   /* Match the qualifiers.  */
   if (aarch64_match_operands_constraint (inst, NULL) == 1)
     {

opcodes/aarch64-opc.c

@@ -3417,6 +3417,34 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
 #undef C14
 #undef C15
 
+#define BIT(INSN,BT)     (((INSN) >> (BT)) & 1)
+#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
+
+bfd_boolean
+verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
+	      const aarch64_insn insn)
+{
+  int t  = BITS (insn, 4, 0);
+  int n  = BITS (insn, 9, 5);
+  int t2 = BITS (insn, 14, 10);
+
+  if (BIT (insn, 23))
+    {
+      /* Write back enabled.  */
+      if ((t == n || t2 == n) && n != 31)
+	return FALSE;
+    }
+
+  if (BIT (insn, 22))
+    {
+      /* Load */
+      if (t == t2)
+	return FALSE;
+    }
+
+  return TRUE;
+}
+
 /* Include the opcode description table as well as the operand description
    table.  */
 #include "aarch64-tbl.h"

opcodes/aarch64-opc.h

@@ -390,4 +390,7 @@ get_logsz (unsigned int size)
   return ls[size - 1];
 }
 
+/* Instruction Verifiers.  */
+extern bfd_boolean verify_ldpsw (const struct aarch64_opcode *, const aarch64_insn);
+
 #endif /* OPCODES_AARCH64_OPC_H */