* arm-dis.c: Split up the comments describing the format codes, so
that the ARM and 16-bit Thumb opcode tables each have comments preceding them that describe all the codes, and only the codes, valid in those tables. (32-bit Thumb table is already like this.) Reorder the lists in all three comments to match the order in which the codes are implemented. Remove all forward declarations of static functions. Convert all function definitions to ISO C format. (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Return nothing. (print_insn_thumb16): Remove unused case 'I'. (print_insn): Update for changed calling convention of subroutines.
This commit is contained in:
Zack Weinberg
parent
1ae72221f9
commit
4a5329c63a
2 changed files with 119 additions and 140 deletions
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@ -1,3 +1,18 @@
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2005-06-07 Zack Weinberg <zack@codesourcery.com>
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* arm-dis.c: Split up the comments describing the format codes, so
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that the ARM and 16-bit Thumb opcode tables each have comments
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preceding them that describe all the codes, and only the codes,
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valid in those tables. (32-bit Thumb table is already like this.)
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Reorder the lists in all three comments to match the order in
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which the codes are implemented.
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Remove all forward declarations of static functions. Convert all
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function definitions to ISO C format.
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(print_insn_arm, print_insn_thumb16, print_insn_thumb32):
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Return nothing.
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(print_insn_thumb16): Remove unused case 'I'.
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(print_insn): Update for changed calling convention of subroutines.
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2005-05-25 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
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@ -49,66 +49,57 @@
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#define WORD_ADDRESS(pc) ((pc) & ~0x3)
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/* Format of the disassembler control string :
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/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
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ordered: they must be searched linearly from the top to obtain a correct
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match. */
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/* print_insn_arm recognizes the following format control codes:
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%% %
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%a print address for ldr/str instruction
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%s print address for ldr/str halfword/signextend instruction
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%b print branch destination
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%c print condition code (always bits 28-31)
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%m print register mask for ldm/stm instruction
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%o print operand2 (immediate or register + shift)
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%p print 'p' iff bits 12-15 are 15
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%t print 't' iff bit 21 set and bit 24 clear
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%A print address for ldc/stc/ldf/stf instruction
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%B print arm BLX(1) destination
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%I print cirrus signed shift immediate: bits 0..3|4..6
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%C print the PSR sub type.
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%F print the COUNT field of a LFM/SFM instruction.
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%P print floating point precision in arithmetic insn
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%Q print floating point precision in ldf/stf insn
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%R print floating point rounding mode
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%<bitfield>r print as an ARM register
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%<bitfield>d print the bitfield in decimal
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%<bitfield>W print the bitfield plus one in decimal
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%<bitfield>x print the bitfield in hex
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%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
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%<bitfield>W print the bitfield plus one in decimal
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%<bitfield>r print as an ARM register
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%<bitfield>f print a floating point constant if >7 else a
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floating point register
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%<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
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%<bitfield>g print as an iWMMXt 64-bit register
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%<bitfield>G print as an iWMMXt general purpose or control register
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%<code>y print a single precision VFP reg.
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Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
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%<code>z print a double precision VFP reg
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Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
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%c print condition code (always bits 28-31)
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%P print floating point precision in arithmetic insn
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%Q print floating point precision in ldf/stf insn
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%R print floating point rounding mode
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%<bitnum>'c print specified char iff bit is one
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%<bitnum>`c print specified char iff bit is zero
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%<bitnum>?ab print a if bit is one else print b
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%p print 'p' iff bits 12-15 are 15
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%t print 't' iff bit 21 set and bit 24 clear
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%o print operand2 (immediate or register + shift)
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%a print address for ldr/str instruction
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%s print address for ldr/str halfword/signextend instruction
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%b print branch destination
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%B print arm BLX(1) destination
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%A print address for ldc/stc/ldf/stf instruction
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%m print register mask for ldm/stm instruction
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%C print the PSR sub type.
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%F print the COUNT field of a LFM/SFM instruction.
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%E print the LSB and WIDTH fields of a BFI or BFC instruction.
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%V print the 16-bit immediate field of a MOVT or MOVW instruction.
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IWMMXT specific format options:
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%<bitfield>g print as an iWMMXt 64-bit register
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%<bitfield>G print as an iWMMXt general purpose or control register
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%<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
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%Z print the Immediate of a WSHUFH instruction.
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%L print as an iWMMXt N/M width field.
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%l like 'A' except use byte offsets for 'B' & 'H' versions
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Thumb specific format options:
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%D print Thumb register (bits 0..2 as high number if bit 7 set)
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%S print Thumb register (bits 3..5 as high number if bit 6 set)
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%<bitfield>I print bitfield as a signed decimal
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(top bit of range being the sign bit)
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%M print Thumb register mask
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%N print Thumb register mask (with LR)
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%O print Thumb register mask (with PC)
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%I print cirrus signed shift immediate: bits 0..3|4..6
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%<bitfield>B print Thumb branch destination (signed displacement)
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%<bitfield>W print (bitfield * 4) as a decimal
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%<bitfield>H print (bitfield * 2) as a decimal
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%<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
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%<bitfield>c print bitfield as a condition code
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%e print arm SMI operand (bits 0..7,8..19).
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%s print Thumb right-shift immediate (6..10; 0 == 32). */
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/* Note: There is a partial ordering in this table - it must be searched from
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the top to obtain a correct match. */
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%L print as an iWMMXt N/M width field.
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%Z print the Immediate of a WSHUFH instruction.
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%l like 'A' except use byte offsets for 'B' & 'H' versions.
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%e print arm SMI operand (bits 0..7,8..19).
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%E print the LSB and WIDTH fields of a BFI or BFC instruction.
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%V print the 16-bit immediate field of a MOVT or MOVW instruction. */
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static const struct arm_opcode arm_opcodes[] =
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{
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@ -632,6 +623,27 @@ static const struct arm_opcode arm_opcodes[] =
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{0, 0x00000000, 0x00000000, 0}
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};
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/* print_insn_thumb16 recognizes the following format control codes:
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%S print Thumb register (bits 3..5 as high number if bit 6 set)
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%D print Thumb register (bits 0..2 as high number if bit 7 set)
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%<bitfield>I print bitfield as a signed decimal
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(top bit of range being the sign bit)
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%N print Thumb register mask (with LR)
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%O print Thumb register mask (with PC)
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%M print Thumb register mask
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%b print CZB's 6-bit unsigned branch destination
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%s print Thumb right-shift immediate (6..10; 0 == 32).
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%<bitfield>r print bitfield as an ARM register
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%<bitfield>d print bitfield as a decimal
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%<bitfield>H print (bitfield * 2) as a decimal
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%<bitfield>W print (bitfield * 4) as a decimal
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%<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
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%<bitfield>B print Thumb branch destination (signed displacement)
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%<bitfield>c print bitfield as a condition code
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%<bitnum>'c print specified char iff bit is one
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%<bitnum>?ab print a if bit is one else print b. */
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static const struct thumb_opcode thumb_opcodes[] =
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{
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/* Thumb instructions. */
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@ -761,17 +773,9 @@ static const struct thumb_opcode thumb_opcodes[] =
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We adopt the convention that hw1 is the high 16 bits of .value and
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.mask, hw2 the low 16 bits.
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%-escapes defined for these instructions:
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print_insn_thumb32 recognizes the following format control codes:
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%% %
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%<bitfield>d print bitfield in decimal
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%<bitfield>W print bitfield*4 in decimal
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%<bitfield>r print bitfield as an ARM register
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%<bitfield>c print bitfield as a condition code
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%<bitnum>'c print "c" iff bit is one
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%<bitnum>`c print "c" iff bit is zero
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%<bitnum>?ab print "a" if bit is one, else "b"
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%I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
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%M print a modified 12-bit immediate (same location)
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@ -786,11 +790,20 @@ static const struct thumb_opcode thumb_opcodes[] =
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%E print the lsb and width fields of a bfc/bfi instruction
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%F print the lsb and width fields of a sbfx/ubfx instruction
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%B print an unconditional branch offset
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%b print a conditional branch offset
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%B print an unconditional branch offset
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%s print the shift field of an SSAT instruction
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%R print the rotation field of an SXT instruction
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%<bitfield>d print bitfield in decimal
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%<bitfield>W print bitfield*4 in decimal
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%<bitfield>r print bitfield as an ARM register
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%<bitfield>c print bitfield as a condition code
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%<bitnum>'c print "c" iff bit is one
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%<bitnum>`c print "c" iff bit is zero
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%<bitnum>?ab print "a" if bit is one, else "b"
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With one exception at the bottom (done because BL and BLX(1) need
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to come dead last), this table was machine-sorted first in
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decreasing order of number of bits set in the mask, then in
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@ -1062,39 +1075,15 @@ static char * arm_fp_const[] =
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static char * arm_shift[] =
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{"lsl", "lsr", "asr", "ror"};
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/* Forward declarations. */
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static void arm_decode_shift
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PARAMS ((long, fprintf_ftype, void *));
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static int print_insn_arm
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PARAMS ((bfd_vma, struct disassemble_info *, long));
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static int print_insn_thumb16
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PARAMS ((bfd_vma, struct disassemble_info *, long));
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static int print_insn_thumb32
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PARAMS ((bfd_vma, struct disassemble_info *, long));
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static void parse_disassembler_options
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PARAMS ((char *));
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static int print_insn
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PARAMS ((bfd_vma, struct disassemble_info *, bfd_boolean));
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static int set_iwmmxt_regnames
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PARAMS ((void));
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int get_arm_regname_num_options
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PARAMS ((void));
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int set_arm_regname_option
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PARAMS ((int));
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int get_arm_regnames
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PARAMS ((int, const char **, const char **, const char ***));
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/* Functions. */
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int
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get_arm_regname_num_options ()
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get_arm_regname_num_options (void)
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{
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return NUM_ARM_REGNAMES;
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}
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int
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set_arm_regname_option (option)
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int option;
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set_arm_regname_option (int option)
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{
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int old = regname_selected;
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regname_selected = option;
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@ -1102,11 +1091,8 @@ set_arm_regname_option (option)
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}
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int
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get_arm_regnames (option, setname, setdescription, register_names)
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int option;
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const char **setname;
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const char **setdescription;
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const char ***register_names;
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get_arm_regnames (int option, const char **setname, const char **setdescription,
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const char ***register_names)
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{
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*setname = regnames[option].name;
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*setdescription = regnames[option].description;
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@ -1115,10 +1101,7 @@ get_arm_regnames (option, setname, setdescription, register_names)
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}
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static void
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arm_decode_shift (given, func, stream)
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long given;
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fprintf_ftype func;
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void * stream;
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arm_decode_shift (long given, fprintf_ftype func, void *stream)
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{
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func (stream, "%s", arm_regnames[given & 0xf]);
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@ -1149,7 +1132,7 @@ arm_decode_shift (given, func, stream)
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}
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static int
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set_iwmmxt_regnames ()
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set_iwmmxt_regnames (void)
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{
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const char * setname;
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const char * setdesc;
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@ -1165,15 +1148,11 @@ set_iwmmxt_regnames ()
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return iwmmxt_regnames;
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}
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction (always 4 on ARM). */
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static int
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print_insn_arm (pc, info, given)
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bfd_vma pc;
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struct disassemble_info *info;
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long given;
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/* Print one ARM instruction from PC on INFO->STREAM. */
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static void
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print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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{
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const struct arm_opcode *insn;
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void *stream = info->stream;
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@ -1911,20 +1890,16 @@ print_insn_arm (pc, info, given)
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else
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func (stream, "%c", *c);
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}
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return 4;
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return;
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}
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}
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abort ();
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}
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction. */
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/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
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static int
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print_insn_thumb16 (pc, info, given)
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bfd_vma pc;
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struct disassemble_info *info;
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long given;
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static void
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print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
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{
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const struct thumb_opcode *insn;
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void *stream = info->stream;
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@ -2093,11 +2068,6 @@ print_insn_thumb16 (pc, info, given)
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func (stream, "0x%04x", reg);
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break;
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case 'I':
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reg = ((reg ^ (1 << bitend)) - (1 << bitend));
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func (stream, "%d", reg);
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break;
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case 'B':
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reg = ((reg ^ (1 << bitend)) - (1 << bitend));
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(*info->print_address_func)
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@ -2145,18 +2115,17 @@ print_insn_thumb16 (pc, info, given)
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abort ();
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}
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}
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return 2;
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return;
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}
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/* No match. */
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abort ();
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}
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static int
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print_insn_thumb32 (pc, info, given)
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bfd_vma pc;
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struct disassemble_info *info;
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long given;
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/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
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static void
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print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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{
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const struct arm_opcode *insn;
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void *stream = info->stream;
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@ -2554,7 +2523,7 @@ print_insn_thumb32 (pc, info, given)
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abort ();
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}
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}
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return 4;
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return;
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}
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/* No match. */
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@ -2581,8 +2550,7 @@ arm_symbol_is_valid (asymbol * sym,
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/* Parse an individual disassembler option. */
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void
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parse_arm_disassembler_option (option)
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char * option;
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parse_arm_disassembler_option (char *option)
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{
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if (option == NULL)
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return;
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@ -2619,8 +2587,7 @@ parse_arm_disassembler_option (option)
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or commas. (Whitespace separators supported for backwards compatibility). */
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static void
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parse_disassembler_options (options)
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char * options;
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parse_disassembler_options (char *options)
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{
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if (options == NULL)
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return;
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@ -2642,16 +2609,14 @@ parse_disassembler_options (options)
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the relevant number of data bytes exist. */
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static int
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print_insn (pc, info, little)
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bfd_vma pc;
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struct disassemble_info * info;
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bfd_boolean little;
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print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
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{
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unsigned char b[4];
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long given;
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int status;
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int is_thumb;
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int (*printer) (bfd_vma, struct disassemble_info *, long);
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int size;
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void (*printer) (bfd_vma, struct disassemble_info *, long);
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if (info->disassembler_options)
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{
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@ -2697,6 +2662,7 @@ print_insn (pc, info, little)
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is four bytes long and is either ordered 0123 or 3210. */
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printer = print_insn_arm;
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info->bytes_per_chunk = 4;
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size = 4;
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status = info->read_memory_func (pc, (bfd_byte *)b, 4, info);
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if (little)
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@ -2710,8 +2676,10 @@ print_insn (pc, info, little)
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instruction lengths. Fortunately, the bits that determine
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the length of the current instruction are always to be found
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in the first two bytes. */
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printer = print_insn_thumb16;
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info->bytes_per_chunk = 2;
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size = 2;
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status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
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if (!status)
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{
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@ -2733,9 +2701,8 @@ print_insn (pc, info, little)
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given = (b[1]) | (b[0] << 8) | (given << 16);
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printer = print_insn_thumb32;
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size = 4;
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}
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else
|
||||
printer = print_insn_thumb16;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2752,27 +2719,24 @@ print_insn (pc, info, little)
|
|||
addresses, since the addend is not currently pc-relative. */
|
||||
pc = 0;
|
||||
|
||||
return printer (pc, info, given);
|
||||
printer (pc, info, given);
|
||||
return size;
|
||||
}
|
||||
|
||||
int
|
||||
print_insn_big_arm (pc, info)
|
||||
bfd_vma pc;
|
||||
struct disassemble_info * info;
|
||||
print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
|
||||
{
|
||||
return print_insn (pc, info, FALSE);
|
||||
}
|
||||
|
||||
int
|
||||
print_insn_little_arm (pc, info)
|
||||
bfd_vma pc;
|
||||
struct disassemble_info * info;
|
||||
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
|
||||
{
|
||||
return print_insn (pc, info, TRUE);
|
||||
}
|
||||
|
||||
void
|
||||
print_arm_disassembler_options (FILE * stream)
|
||||
print_arm_disassembler_options (FILE *stream)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue