* gas/config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
(do_crypto_3op_1): New function. (do_sha1c): Likewise. (do_sha1p): Likewise. (do_sha1m): Likewise. (do_sha1su0): Likewise. (do_sha256h): Likewise. (do_sha256h2): Likewise. (do_sha256su1): Likewise. (insns): Add SHA 3 operand instructions. * gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise. * opcodes/arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
This commit is contained in:
Matthew Gretton-Dann
parent
4f51b4bdbb
commit
48adcd8ed5
7 changed files with 206 additions and 2 deletions
|
|
@ -1,3 +1,16 @@
|
|||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
|
||||
(do_crypto_3op_1): New function.
|
||||
(do_sha1c): Likewise.
|
||||
(do_sha1p): Likewise.
|
||||
(do_sha1m): Likewise.
|
||||
(do_sha1su0): Likewise.
|
||||
(do_sha256h): Likewise.
|
||||
(do_sha256h2): Likewise.
|
||||
(do_sha256su1): Likewise.
|
||||
(insns): Add SHA 3 operand instructions.
|
||||
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* config/tc-arm.c (neon_type_mask): Add P64 type.
|
||||
|
|
|
|||
|
|
@ -12351,7 +12351,8 @@ struct neon_tab_entry
|
|||
X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
|
||||
X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
|
||||
X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
|
||||
X(aes, 0x3b00300, N_INV, N_INV)
|
||||
X(aes, 0x3b00300, N_INV, N_INV), \
|
||||
X(sha3op, 0x2000c00, N_INV, N_INV)
|
||||
|
||||
enum neon_opc
|
||||
{
|
||||
|
|
@ -16199,6 +16200,21 @@ do_crypto_2op_1 (unsigned elttype, int op)
|
|||
inst.instruction |= 0xf0000000;
|
||||
}
|
||||
|
||||
static void
|
||||
do_crypto_3op_1 (int u, int op)
|
||||
{
|
||||
set_it_insn_type (OUTSIDE_IT_INSN);
|
||||
|
||||
if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
|
||||
N_32 | N_UNT | N_KEY).type == NT_invtype)
|
||||
return;
|
||||
|
||||
inst.error = NULL;
|
||||
|
||||
NEON_ENCODE (INTEGER, inst);
|
||||
neon_three_same (1, u, 8 << op);
|
||||
}
|
||||
|
||||
static void
|
||||
do_aese (void)
|
||||
{
|
||||
|
|
@ -16223,7 +16239,47 @@ do_aesimc (void)
|
|||
do_crypto_2op_1 (N_8, 3);
|
||||
}
|
||||
|
||||
static void
|
||||
do_sha1c (void)
|
||||
{
|
||||
do_crypto_3op_1 (0, 0);
|
||||
}
|
||||
|
||||
static void
|
||||
do_sha1p (void)
|
||||
{
|
||||
do_crypto_3op_1 (0, 1);
|
||||
}
|
||||
|
||||
static void
|
||||
do_sha1m (void)
|
||||
{
|
||||
do_crypto_3op_1 (0, 2);
|
||||
}
|
||||
|
||||
static void
|
||||
do_sha1su0 (void)
|
||||
{
|
||||
do_crypto_3op_1 (0, 3);
|
||||
}
|
||||
|
||||
static void
|
||||
do_sha256h (void)
|
||||
{
|
||||
do_crypto_3op_1 (1, 0);
|
||||
}
|
||||
|
||||
static void
|
||||
do_sha256h2 (void)
|
||||
{
|
||||
do_crypto_3op_1 (1, 1);
|
||||
}
|
||||
|
||||
static void
|
||||
do_sha256su1 (void)
|
||||
{
|
||||
do_crypto_3op_1 (1, 2);
|
||||
}
|
||||
|
||||
/* Overall per-instruction processing. */
|
||||
|
||||
|
|
@ -18461,7 +18517,13 @@ static const struct asm_opcode insns[] =
|
|||
nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
|
||||
nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
|
||||
nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
|
||||
|
||||
nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
|
||||
nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
|
||||
nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
|
||||
nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
|
||||
nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
|
||||
nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
|
||||
nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
|
||||
|
||||
#undef ARM_VARIANT
|
||||
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
|
||||
|
|
|
|||
|
|
@ -3,6 +3,11 @@
|
|||
* gas/arm/armv8-a+crypto.d: Update testcase.
|
||||
* gas/arm/armv8-a+crypto.s: Likewise.
|
||||
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* gas/arm/armv8-a+crypto.d: Update testcase.
|
||||
* gas/arm/armv8-a+crypto.s: Likewise.
|
||||
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* gas/arm/armv8-a+crypto.d: New testcase.
|
||||
|
|
|
|||
|
|
@ -22,6 +22,34 @@ Disassembly of section .text:
|
|||
0[0-9a-f]+ <[^>]+> f3b0e3ce aesimc.8 q7, q7
|
||||
0[0-9a-f]+ <[^>]+> f3f003e0 aesimc.8 q8, q8
|
||||
0[0-9a-f]+ <[^>]+> f3f0e3ee aesimc.8 q15, q15
|
||||
0[0-9a-f]+ <[^>]+> f2000c40 sha1c.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> f20eec4e sha1c.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> f2400ce0 sha1c.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> f24eecee sha1c.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> f2100c40 sha1p.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> f21eec4e sha1p.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> f2500ce0 sha1p.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> f25eecee sha1p.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> f2200c40 sha1m.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> f22eec4e sha1m.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> f2600ce0 sha1m.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> f26eecee sha1m.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> f2300c40 sha1su0.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> f23eec4e sha1su0.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> f2700ce0 sha1su0.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> f27eecee sha1su0.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> f3000c40 sha256h.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> f30eec4e sha256h.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> f3400ce0 sha256h.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> f34eecee sha256h.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> f3100c40 sha256h2.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> f31eec4e sha256h2.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> f3500ce0 sha256h2.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> f35eecee sha256h2.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> f3200c40 sha256su1.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> f32eec4e sha256su1.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> f3600ce0 sha256su1.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> f36eecee sha256su1.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> efa0 0e00 vmull.p64 q0, d0, d0
|
||||
0[0-9a-f]+ <[^>]+> efef eeaf vmull.p64 q15, d31, d31
|
||||
0[0-9a-f]+ <[^>]+> ffb0 0300 aese.8 q0, q0
|
||||
|
|
@ -40,3 +68,31 @@ Disassembly of section .text:
|
|||
0[0-9a-f]+ <[^>]+> ffb0 e3ce aesimc.8 q7, q7
|
||||
0[0-9a-f]+ <[^>]+> fff0 03e0 aesimc.8 q8, q8
|
||||
0[0-9a-f]+ <[^>]+> fff0 e3ee aesimc.8 q15, q15
|
||||
0[0-9a-f]+ <[^>]+> ef00 0c40 sha1c.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> ef0e ec4e sha1c.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> ef40 0ce0 sha1c.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> ef4e ecee sha1c.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> ef10 0c40 sha1p.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> ef1e ec4e sha1p.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> ef50 0ce0 sha1p.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> ef5e ecee sha1p.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> ef20 0c40 sha1m.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> ef2e ec4e sha1m.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> ef60 0ce0 sha1m.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> ef6e ecee sha1m.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> ef30 0c40 sha1su0.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> ef3e ec4e sha1su0.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> ef70 0ce0 sha1su0.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> ef7e ecee sha1su0.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> ff00 0c40 sha256h.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> ff0e ec4e sha256h.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> ff40 0ce0 sha256h.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> ff4e ecee sha256h.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> ff10 0c40 sha256h2.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> ff1e ec4e sha256h2.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> ff50 0ce0 sha256h2.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> ff5e ecee sha256h2.32 q15, q15, q15
|
||||
0[0-9a-f]+ <[^>]+> ff20 0c40 sha256su1.32 q0, q0, q0
|
||||
0[0-9a-f]+ <[^>]+> ff2e ec4e sha256su1.32 q7, q7, q7
|
||||
0[0-9a-f]+ <[^>]+> ff60 0ce0 sha256su1.32 q8, q8, q8
|
||||
0[0-9a-f]+ <[^>]+> ff6e ecee sha256su1.32 q15, q15, q15
|
||||
|
|
|
|||
|
|
@ -21,6 +21,35 @@
|
|||
aesimc.8 q7, q7
|
||||
aesimc.8 q8, q8
|
||||
aesimc.8 q15, q15
|
||||
sha1c.32 q0, q0, q0
|
||||
sha1c.32 q7, q7, q7
|
||||
sha1c.32 q8, q8, q8
|
||||
sha1c.32 q15, q15, q15
|
||||
sha1p.32 q0, q0, q0
|
||||
sha1p.32 q7, q7, q7
|
||||
sha1p.32 q8, q8, q8
|
||||
sha1p.32 q15, q15, q15
|
||||
sha1m.32 q0, q0, q0
|
||||
sha1m.32 q7, q7, q7
|
||||
sha1m.32 q8, q8, q8
|
||||
sha1m.32 q15, q15, q15
|
||||
sha1su0.32 q0, q0, q0
|
||||
sha1su0.32 q7, q7, q7
|
||||
sha1su0.32 q8, q8, q8
|
||||
sha1su0.32 q15, q15, q15
|
||||
sha256h.32 q0, q0, q0
|
||||
sha256h.32 q7, q7, q7
|
||||
sha256h.32 q8, q8, q8
|
||||
sha256h.32 q15, q15, q15
|
||||
sha256h2.32 q0, q0, q0
|
||||
sha256h2.32 q7, q7, q7
|
||||
sha256h2.32 q8, q8, q8
|
||||
sha256h2.32 q15, q15, q15
|
||||
sha256su1.32 q0, q0, q0
|
||||
sha256su1.32 q7, q7, q7
|
||||
sha256su1.32 q8, q8, q8
|
||||
sha256su1.32 q15, q15, q15
|
||||
|
||||
|
||||
.thumb
|
||||
vmull.p64 q0, d0, d0
|
||||
|
|
@ -41,3 +70,31 @@
|
|||
aesimc.8 q7, q7
|
||||
aesimc.8 q8, q8
|
||||
aesimc.8 q15, q15
|
||||
sha1c.32 q0, q0, q0
|
||||
sha1c.32 q7, q7, q7
|
||||
sha1c.32 q8, q8, q8
|
||||
sha1c.32 q15, q15, q15
|
||||
sha1p.32 q0, q0, q0
|
||||
sha1p.32 q7, q7, q7
|
||||
sha1p.32 q8, q8, q8
|
||||
sha1p.32 q15, q15, q15
|
||||
sha1m.32 q0, q0, q0
|
||||
sha1m.32 q7, q7, q7
|
||||
sha1m.32 q8, q8, q8
|
||||
sha1m.32 q15, q15, q15
|
||||
sha1su0.32 q0, q0, q0
|
||||
sha1su0.32 q7, q7, q7
|
||||
sha1su0.32 q8, q8, q8
|
||||
sha1su0.32 q15, q15, q15
|
||||
sha256h.32 q0, q0, q0
|
||||
sha256h.32 q7, q7, q7
|
||||
sha256h.32 q8, q8, q8
|
||||
sha256h.32 q15, q15, q15
|
||||
sha256h2.32 q0, q0, q0
|
||||
sha256h2.32 q7, q7, q7
|
||||
sha256h2.32 q8, q8, q8
|
||||
sha256h2.32 q15, q15, q15
|
||||
sha256su1.32 q0, q0, q0
|
||||
sha256su1.32 q7, q7, q7
|
||||
sha256su1.32 q8, q8, q8
|
||||
sha256su1.32 q15, q15, q15
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
|
||||
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* arm-dis.c (neon_opcodes): Handle VMULL.P64.
|
||||
|
|
|
|||
|
|
@ -625,6 +625,13 @@ static const struct opcode32 neon_opcodes[] =
|
|||
{FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
|
||||
|
||||
/* Three registers of the same length. */
|
||||
{FPU_CRYPTO_EXT_ARMV8, 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
||||
{FPU_CRYPTO_EXT_ARMV8, 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
||||
{FPU_CRYPTO_EXT_ARMV8, 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
||||
{FPU_CRYPTO_EXT_ARMV8, 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
||||
{FPU_CRYPTO_EXT_ARMV8, 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
||||
{FPU_CRYPTO_EXT_ARMV8, 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
||||
{FPU_CRYPTO_EXT_ARMV8, 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
|
||||
{FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
{FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
{FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
|
|
|
|||
Loading…
Reference in a new issue