* cris.cpu (simplecris-common-writable-specregs)
(simplecris-common-readable-specregs): Split from simplecris-common-specregs. All users changed. (cris-implemented-writable-specregs-v0) (cris-implemented-readable-specregs-v0): Similar from cris-implemented-specregs-v0. (cris-implemented-writable-specregs-v3) (cris-implemented-readable-specregs-v3) (cris-implemented-writable-specregs-v8) (cris-implemented-readable-specregs-v8) (cris-implemented-writable-specregs-v10) (cris-implemented-readable-specregs-v10) (cris-implemented-writable-specregs-v32) (cris-implemented-readable-specregs-v32): Similar. (bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New insns and specializations.
This commit is contained in:
Hans-Peter Nilsson
parent
cb712a9ecd
commit
48ad829861
2 changed files with 130 additions and 28 deletions
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@ -1,3 +1,22 @@
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2005-12-06 Hans-Peter Nilsson <hp@axis.com>
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* cris.cpu (simplecris-common-writable-specregs)
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(simplecris-common-readable-specregs): Split from
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simplecris-common-specregs. All users changed.
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(cris-implemented-writable-specregs-v0)
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(cris-implemented-readable-specregs-v0): Similar from
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cris-implemented-specregs-v0.
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(cris-implemented-writable-specregs-v3)
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(cris-implemented-readable-specregs-v3)
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(cris-implemented-writable-specregs-v8)
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(cris-implemented-readable-specregs-v8)
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(cris-implemented-writable-specregs-v10)
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(cris-implemented-readable-specregs-v10)
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(cris-implemented-writable-specregs-v32)
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(cris-implemented-readable-specregs-v32): Similar.
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(bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New
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insns and specializations.
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2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
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Add ms2
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139
cpu/cris.cpu
139
cpu/cris.cpu
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@ -371,59 +371,89 @@
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(define-pmacro cris-timing-const-QI cris-timing-const-HI)
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(define-pmacro cris-timing-const-sr-QI cris-timing-const-sr-HI)
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(define-pmacro (simplecris-common-specregs)
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"The common special registers in pre-v32 models."
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((QI 0) (QI 1) (HI 4) (HI 5)
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(SI 8) (SI 9) (SI 10) (SI 11) (SI 12) (SI 13))
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(define-pmacro (simplecris-common-writable-specregs)
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"The common writable special registers in pre-v32 models."
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((HI 5) (SI 9) (SI 10) (SI 11) (SI 12) (SI 13))
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)
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(define-pmacro (cris-implemented-specregs-v0)
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"Special registers in v0 and their sizes"
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(.splice (.unsplice (simplecris-common-specregs)) (HI 6) (HI 7))
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(define-pmacro (simplecris-common-readable-specregs)
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"The common readable special registers in pre-v32 models."
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(.splice (.unsplice (simplecris-common-writable-specregs))
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(QI 0) (QI 1) (HI 4) (SI 8))
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)
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(define-pmacro (cris-implemented-writable-specregs-v0)
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"Special writable registers in v0 and their sizes"
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(.splice (.unsplice (simplecris-common-writable-specregs)) (HI 6) (HI 7))
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)
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(define-pmacro
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cris-implemented-specregs-const-v0
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cris-implemented-specregs-v0
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cris-implemented-writable-specregs-v0
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)
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(define-pmacro (cris-implemented-readable-specregs-v0)
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"Special readable registers in v0 and their sizes"
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(.splice (.unsplice (simplecris-common-readable-specregs)) (HI 6) (HI 7))
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)
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(define-pmacro (cris-implemented-specregs-v3)
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"Special registers in v3 and their sizes"
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(.splice (.unsplice (cris-implemented-specregs-v0)) (SI 14))
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(define-pmacro (cris-implemented-writable-specregs-v3)
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"Special writable registers in v3 and their sizes"
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(.splice (.unsplice (cris-implemented-writable-specregs-v0)) (SI 14))
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)
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(define-pmacro
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cris-implemented-specregs-const-v3
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cris-implemented-specregs-v3
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cris-implemented-writable-specregs-v3
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)
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(define-pmacro (cris-implemented-readable-specregs-v3)
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"Special readable registers in v3 and their sizes"
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(.splice (.unsplice (cris-implemented-readable-specregs-v0)) (SI 14))
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)
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(define-pmacro (cris-implemented-specregs-v8)
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"Special registers in v8 and their sizes"
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(.splice (.unsplice (simplecris-common-specregs)) (SI 14))
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(define-pmacro (cris-implemented-writable-specregs-v8)
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"Special writable registers in v8 and their sizes"
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(.splice (.unsplice (simplecris-common-writable-specregs)) (SI 14))
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)
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(define-pmacro
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cris-implemented-specregs-const-v8
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cris-implemented-specregs-v8
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cris-implemented-writable-specregs-v8
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)
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(define-pmacro (cris-implemented-readable-specregs-v8)
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"Special readable registers in v8 and their sizes"
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(.splice (.unsplice (simplecris-common-readable-specregs)) (SI 14))
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)
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(define-pmacro (cris-implemented-specregs-v10)
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"Special registers in v10 and their sizes"
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(.splice (.unsplice (simplecris-common-specregs)) (SI 7) (SI 14) (SI 15))
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(define-pmacro (cris-implemented-writable-specregs-v10)
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"Special writable registers in v10 and their sizes"
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(.splice (.unsplice (simplecris-common-writable-specregs))
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(SI 7) (SI 14) (SI 15))
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)
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(define-pmacro
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cris-implemented-specregs-const-v10
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cris-implemented-specregs-v10
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cris-implemented-writable-specregs-v10
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)
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(define-pmacro (cris-implemented-readable-specregs-v10)
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"Special registers in v10 and their sizes"
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(.splice (.unsplice (simplecris-common-readable-specregs))
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(SI 7) (SI 14) (SI 15))
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)
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(define-pmacro (cris-implemented-specregs-v32)
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"Special registers in v32 and their sizes"
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((QI 0) (QI 1) (QI 2) (QI 3) (HI 4)
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(SI 5) (SI 6) (SI 7) (SI 8) (SI 9)
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(define-pmacro (cris-implemented-writable-specregs-v32)
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"Special writable registers in v32 and their sizes"
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((QI 2) (QI 3)
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(SI 5) (SI 6) (SI 7) (SI 9)
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(SI 10) (SI 11) (SI 12) (SI 13) (SI 14) (SI 15))
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)
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(define-pmacro (cris-implemented-readable-specregs-v32)
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"Special readable registers in v32 and their sizes"
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(.splice (.unsplice (cris-implemented-writable-specregs-v32))
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(QI 0) (QI 1) (HI 4) (SI 8))
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)
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; For v32, all special register operations on constants (that is,
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; move) take 32-bit operands, not the real size of the register, as in
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; other move operations.
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(define-pmacro (cris-implemented-specregs-const-v32)
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(.map (.pmacro (regno) (SI regno)) (.iota 16))
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(.map (.pmacro (x) (SI (.cadr2 x)))
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(cris-implemented-writable-specregs-v32))
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)
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(define-pmacro cris-swap-codes
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@ -2579,7 +2609,7 @@
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(r)
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((eq prno (.cadr2 r))
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(set-subreg-gr (.car2 r) (regno Rd-sfield) newval)))
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((.sym cris-implemented-specregs- VER))))
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((.sym cris-implemented-readable-specregs- VER))))
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(else (error "move-spr-r from unimplemented register")))
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(reset-x-p))))
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(cris-cpu-models)))
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@ -2633,7 +2663,7 @@
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(r)
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((eq rno (.cadr2 r))
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(set newval ((.sym (.car2 r) -ext) (cris-get-mem (.car2 r) Rs)))))
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((.sym cris-implemented-specregs- VER))))
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((.sym cris-implemented-writable-specregs- VER))))
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(else (error "Trying to set unimplemented special register")))
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(set Pd newval)
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(reset-x-p))
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@ -2717,7 +2747,7 @@
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(r)
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((eq rno (.cadr2 r))
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(cris-set-mem (.car2 r) Rd-sfield Ps)))
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((.sym cris-implemented-specregs- VER))))
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((.sym cris-implemented-readable-specregs- VER))))
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(else (error "write from unimplemented special register")))
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(reset-x-p))))
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(cris-cpu-models)))
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@ -4333,6 +4363,59 @@
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(c-call VOID "cris_flush_simulator_decode_cache" pc))
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)
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; (BDAP.D [PC+],PC [ 1111 | 11010110 | 1111 ]
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; This [PC+I] prefix is used for DSO-local jumps in PIC code, together with
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; move-m-pcplus-p0: "move [pc=pc+N],p0"
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(dni-c-SI-attr
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bdap-32-pc "bdap.d [PC+],PC"
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(MACH-PC)
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"bdap ${sconst32},PC"
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(+ (f-dest 15) MODE_AUTOINCREMENT INDIR_BDAP_M SIZE_DWORD (f-source 15) const32)
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(sequence
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((SI newpc) (SI oldpc) (SI offs))
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(set offs const32)
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(set oldpc (add SI pc 6))
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(set newpc (add SI oldpc offs))
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(set prefixreg newpc)
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(set prefix-set 1))
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)
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; (MOVE [PC+],P0 [ 0000 | 11100011 | 1111 ])
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; This insn is used for DSO-local jumps in PIC code. See bdap-32-pc.
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(dni ; Must not use dni-cmt-* because we force MODE_AUTOINCREMENT.
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move-m-pcplus-p0 "move [PC+],P0"
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(MACH-PC)
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"move [PC+],P0"
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(+ (f-dest 0) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED (f-source 15))
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(if prefix-set
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(sequence
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((QI dummy))
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; We model the memory read, but throw the result away, as the
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; destination register is read-only. We need to assign the result of
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; cris-get-mem though, as CGEN-FIXME: invalid C code will otherwise
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; be generated.
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(set dummy (cris-get-mem QI pc))
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(reset-x-p))
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(error "move [PC+],P0 without prefix is not implemented"))
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(cris-mem-timing)
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)
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; This insn is used in Linux in the form "move [$sp=$sp+16],$p8"; it's
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; similar to move-m-pcplus-p0 above. The same comments apply here.
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(dni
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move-m-spplus-p8 "move [SP+],P8"
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(MACH-PC)
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"move [SP+],P8"
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(+ (f-dest 8) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED (f-source 14))
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(if prefix-set
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(sequence
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((SI dummy))
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(set dummy (cris-get-mem SI sp))
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(reset-x-p))
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(error "move [SP+],P8 without prefix is not implemented"))
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(cris-mem-timing)
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)
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; ADDO.m [Rs],Rd,ACR [ Rd | 100101mm | Rs ]
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; ADDO.m [Rs+],Rd,ACR [ Rd | 110101mm | Rs ]
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(dni-cmt-bwd
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