* elf32-v850.c (v850_elf_is_target_special_symbol): New function.
(bfd_elf32_bfd_is_target_special_symbol): Define. * v850.h (V850_INVERSE_PCREL): Define. * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the destination address by subtracting the operand from the current address. * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store a positive value in the insn. (extract_u16_loop): Do not negate the returned value. (D16_LOOP): Add V850_INVERSE_PCREL flag. (ceilf.sw): Remove duplicate entry. (cvtf.hs): New entry. (cvtf.sh): Likewise. (fmaf.s): Likewise. (fmsf.s): Likewise. (fnmaf.s): Likewise. (fnmsf.s): Likewise. (maddf.s): Restrict to E3V5 architectures. (msubf.s): Likewise. (nmaddf.s): Likewise. (nmsubf.s): Likewise.
This commit is contained in:
Nick Clifton
parent
cb8af559c1
commit
41702d50f7
7 changed files with 60 additions and 9 deletions
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@ -1,3 +1,8 @@
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2013-04-03 Nick Clifton <nickc@redhat.com>
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* elf32-v850.c (v850_elf_is_target_special_symbol): New function.
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(bfd_elf32_bfd_is_target_special_symbol): Define.
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2013-04-03 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
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* elf64-aarch64.c (elf64_aarch64_gc_sweep_hook): Use
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@ -1920,6 +1920,12 @@ v850_elf_is_local_label_name (bfd *abfd ATTRIBUTE_UNUSED, const char *name)
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return ( (name[0] == '.' && (name[1] == 'L' || name[1] == '.'))
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|| (name[0] == '_' && name[1] == '.' && name[2] == 'L' && name[3] == '_'));
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}
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static bfd_boolean
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v850_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
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{
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return v850_elf_is_local_label_name (abfd, sym->name);
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}
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/* We overload some of the bfd_reloc error codes for own purposes. */
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#define bfd_reloc_gp_not_found bfd_reloc_other
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@ -3791,6 +3797,8 @@ static const struct bfd_elf_special_section v850_elf_special_sections[] =
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#define elf_backend_rela_normal 1
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#define bfd_elf32_bfd_is_local_label_name v850_elf_is_local_label_name
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#define bfd_elf32_bfd_is_target_special_symbol v850_elf_is_target_special_symbol
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#define bfd_elf32_bfd_reloc_type_lookup v850_elf_reloc_type_lookup
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#define bfd_elf32_bfd_reloc_name_lookup v850_elf_reloc_name_lookup
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#define bfd_elf32_bfd_merge_private_bfd_data v850_elf_merge_private_bfd_data
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@ -1,3 +1,7 @@
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2013-04-03 Nick Clifton <nickc@redhat.com>
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* v850.h (V850_INVERSE_PCREL): Define.
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2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
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PR binutils/15068
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@ -232,6 +232,9 @@ extern const struct v850_operand v850_operands[];
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/* This operand is a prefetch oparation. */
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#define V850_OPERAND_PREFOP 0x800000
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/* A PC-relative displacement where a positive value indicates a backwards displacement. */
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#define V850_INVERSE_PCREL 0x1000000
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extern int v850_msg_is_out_of_range (const char *);
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#endif /* V850_H */
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@ -1,3 +1,25 @@
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2013-04-03 Nick Clifton <nickc@redhat.com>
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* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
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destination address by subtracting the operand from the current
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address.
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* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
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a positive value in the insn.
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(extract_u16_loop): Do not negate the returned value.
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(D16_LOOP): Add V850_INVERSE_PCREL flag.
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(ceilf.sw): Remove duplicate entry.
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(cvtf.hs): New entry.
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(cvtf.sh): Likewise.
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(fmaf.s): Likewise.
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(fmsf.s): Likewise.
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(fnmaf.s): Likewise.
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(fnmsf.s): Likewise.
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(maddf.s): Restrict to E3V5 architectures.
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(msubf.s): Likewise.
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(nmaddf.s): Likewise.
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(nmsubf.s): Likewise.
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2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (get_sib): Add the sizeflag argument. Properly
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@ -94,6 +94,9 @@ print_value (int flags,
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if (flags & V850_PCREL)
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{
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bfd_vma addr = value + memaddr;
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if (flags & V850_INVERSE_PCREL)
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addr = memaddr - value;
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info->print_address_func (addr, info);
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}
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else if (flags & V850_OPERAND_DISP)
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@ -301,7 +301,9 @@ extract_d9 (unsigned long insn, int * invalid)
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static unsigned long
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insert_u16_loop (unsigned long insn, long value, const char ** errmsg)
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{
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if (value < -0xffff || value > 0)
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/* Loop displacement is encoded as a positive value,
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even though the instruction branches backwards. */
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if (value < 0 || value > 0xffff)
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{
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if ((value % 2) != 0)
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* errmsg = branch_out_of_range_and_odd_offset;
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@ -311,14 +313,13 @@ insert_u16_loop (unsigned long insn, long value, const char ** errmsg)
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else if ((value % 2) != 0)
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* errmsg = branch_to_odd_offset;
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return insn | ((-value & 0xfffe) << 16);
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return insn | ((value & 0xfffe) << 16);
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}
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static unsigned long
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extract_u16_loop (unsigned long insn, int * invalid)
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{
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long ret = (insn >> 16) & 0xfffe;
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ret = -ret;
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if (invalid != 0)
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*invalid = 0;
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@ -1211,7 +1212,7 @@ const struct v850_operand v850_operands[] =
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/* The unsigned DISP16 field in a format 7 insn. */
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#define D16_LOOP (D16_15 + 1)
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{ 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL },
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{ 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL },
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/* The DISP17 field in a format 7 insn. */
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#define D17_16 (D16_LOOP + 1)
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@ -1814,7 +1815,6 @@ const struct v850_opcode v850_opcodes[] =
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{ "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
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/* Default value for FFF is 0(not defined in spec). */
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{ "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
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@ -1830,10 +1830,12 @@ const struct v850_opcode v850_opcodes[] =
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{ "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
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{ "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
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{ "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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@ -1853,18 +1855,22 @@ const struct v850_opcode v850_opcodes[] =
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{ "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP },
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{ "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
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{ "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
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{ "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP },
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{ "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
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{ "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
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{ "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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{ "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP },
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{ "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP },
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{ "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
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{ "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
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{ "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
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{ "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
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{ "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
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{ "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
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