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gas/testsuite/

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2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/intelok.d: Account for 32-bit displacements being shown
	in hex.

opcodes/
2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
	hex (but retain it being displayed as signed). Remove redundant
	checks. Add handling of displacements for 16-bit addressing in Intel
	mode.
This commit is contained in:
Jan Beulich 2005-05-25 06:50:23 +00:00
parent c7e2e997e4
commit 3d456fa193
4 changed files with 63 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
gas/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2005-05-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.d: Account for 32-bit displacements being shown
in hex.
2005-05-24 H.J. Lu <hongjiu.lu@intel.com>
* gas/elf/group0b.d: Updated.

6
gas/testsuite/gas/i386/intelok.d
View file

@ -104,8 +104,8 @@ Disassembly of section .text:
[ ]*[0-9a-f]+: 8b 40 0c[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+12\]
[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+18\]
[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+18\]
[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+2\]
[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+2\]
[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
[ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\]
[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\]
[ ]*[0-9a-f]+: 8b 04 8d 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[ecx\*4\]
@ -156,7 +156,7 @@ Disassembly of section .text:
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1]
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
[ ]*[0-9a-f]+: 8b 80 01 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\]
[ ]*[0-9a-f]+: 8b 80 01 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\]
[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\]
[ ]*[0-9a-f]+: a1 01 00 00 00[ ]+mov[ ]+eax,ds:0x1

7
opcodes/ChangeLog
View file

@ -1,3 +1,10 @@
2005-05-25 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
hex (but retain it being displayed as signed). Remove redundant
checks. Add handling of displacements for 16-bit addressing in Intel
mode.
2005-05-25 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (prefix_name): Remove pointless mode_64bit check.

50
opcodes/i386-dis.c
View file

@ -3337,21 +3337,22 @@ OP_E (int bytemode, int sizeflag)
oappend (scratchbuf);
}
}
if (intel_syntax)
if (mod != 0 || (base & 7) == 5)
{
/* Don't print zero displacements. */
if (disp != 0)
if (intel_syntax && disp)
{
if ((bfd_signed_vma) disp > 0)
{
*obufp++ = '+';
*obufp = '\0';
}
print_operand_value (scratchbuf, 0, disp);
oappend (scratchbuf);
else if (mod != 1)
{
*obufp++ = '-';
*obufp = '\0';
disp = - (bfd_signed_vma) disp;
}
print_operand_value (scratchbuf, mod != 1, disp);
oappend (scratchbuf);
}
*obufp++ = close_char;
@ -3410,10 +3411,41 @@ OP_E (int bytemode, int sizeflag)
{
*obufp++ = open_char;
*obufp = '\0';
oappend (index16[rm + add]);
oappend (index16[rm]);
if (intel_syntax && disp)
{
if ((bfd_signed_vma) disp > 0)
{
*obufp++ = '+';
*obufp = '\0';
}
else if (mod != 1)
{
*obufp++ = '-';
*obufp = '\0';
disp = - (bfd_signed_vma) disp;
}
print_operand_value (scratchbuf, mod != 1, disp);
oappend (scratchbuf);
}
*obufp++ = close_char;
*obufp = '\0';
}
else if (intel_syntax)
{
if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
| PREFIX_ES | PREFIX_FS | PREFIX_GS))
;
else
{
oappend (names_seg[ds_reg - es_reg]);
oappend (":");
}
print_operand_value (scratchbuf, 1, disp & 0xffff);
oappend (scratchbuf);
}
}
}