Whitespace cleanup
This commit is contained in:
Anthony Green
parent
f12d1e8a66
commit
3ba611c3ca
1 changed files with 55 additions and 4 deletions
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@ -366,6 +366,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 8) & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned v = (inst & 0xff);
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TRACE("inc");
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cpu.asregs.regs[a] = av + v;
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}
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@ -375,6 +376,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 8) & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned v = (inst & 0xff);
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TRACE("dec");
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cpu.asregs.regs[a] = av - v;
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}
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@ -383,6 +385,7 @@ sim_resume (sd, step, siggnal)
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{
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int a = (inst >> 8) & 0xf;
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unsigned v = (inst & 0xff);
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TRACE("gsr");
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cpu.asregs.regs[a] = cpu.asregs.sregs[v];
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}
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@ -391,6 +394,7 @@ sim_resume (sd, step, siggnal)
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{
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int a = (inst >> 8) & 0xf;
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unsigned v = (inst & 0xff);
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TRACE("ssr");
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cpu.asregs.sregs[v] = cpu.asregs.regs[a];
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}
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@ -416,6 +420,7 @@ sim_resume (sd, step, siggnal)
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case 0x01: /* ldi.l (immediate) */
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{
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int reg = (inst >> 4) & 0xf;
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TRACE("ldi.l");
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unsigned int val = EXTRACT_WORD(pc+2);
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cpu.asregs.regs[reg] = val;
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@ -426,6 +431,7 @@ sim_resume (sd, step, siggnal)
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{
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int dest = (inst >> 4) & 0xf;
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int src = (inst ) & 0xf;
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TRACE("mov");
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cpu.asregs.regs[dest] = cpu.asregs.regs[src];
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}
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@ -434,6 +440,7 @@ sim_resume (sd, step, siggnal)
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{
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unsigned int fn = EXTRACT_WORD(pc+2);
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unsigned int sp = cpu.asregs.regs[1];
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TRACE("jsra");
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/* Save a slot for the static chain. */
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sp -= 4;
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@ -479,6 +486,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("add.l");
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cpu.asregs.regs[a] = av + bv;
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}
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@ -488,6 +496,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int sp = cpu.asregs.regs[a] - 4;
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TRACE("push");
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wlat (scpu, opc, sp, cpu.asregs.regs[b]);
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cpu.asregs.regs[a] = sp;
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@ -498,6 +507,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int sp = cpu.asregs.regs[a];
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TRACE("pop");
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cpu.asregs.regs[b] = rlat (scpu, opc, sp);
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cpu.asregs.regs[a] = sp + 4;
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@ -507,6 +517,7 @@ sim_resume (sd, step, siggnal)
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("lda.l");
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cpu.asregs.regs[reg] = rlat (scpu, opc, addr);
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pc += 4;
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@ -516,6 +527,7 @@ sim_resume (sd, step, siggnal)
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("sta.l");
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wlat (scpu, opc, addr, cpu.asregs.regs[reg]);
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pc += 4;
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@ -526,6 +538,7 @@ sim_resume (sd, step, siggnal)
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int src = inst & 0xf;
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int dest = (inst >> 4) & 0xf;
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int xv;
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TRACE("ld.l");
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xv = cpu.asregs.regs[src];
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cpu.asregs.regs[dest] = rlat (scpu, opc, xv);
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@ -535,6 +548,7 @@ sim_resume (sd, step, siggnal)
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{
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int dest = (inst >> 4) & 0xf;
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int val = inst & 0xf;
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TRACE("st.l");
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wlat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
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}
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@ -544,6 +558,7 @@ sim_resume (sd, step, siggnal)
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unsigned int addr = EXTRACT_WORD(pc+2);
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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TRACE("ldo.l");
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addr += cpu.asregs.regs[b];
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cpu.asregs.regs[a] = rlat (scpu, opc, addr);
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@ -555,6 +570,7 @@ sim_resume (sd, step, siggnal)
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unsigned int addr = EXTRACT_WORD(pc+2);
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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TRACE("sto.l");
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addr += cpu.asregs.regs[a];
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wlat (scpu, opc, addr, cpu.asregs.regs[b]);
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@ -570,7 +586,6 @@ sim_resume (sd, step, siggnal)
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int vb = cpu.asregs.regs[b];
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TRACE("cmp");
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if (va == vb)
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cc = CC_EQ;
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else
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@ -591,6 +606,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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signed char bv = cpu.asregs.regs[b];
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TRACE("sex.b");
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cpu.asregs.regs[a] = (int) bv;
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}
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@ -600,6 +616,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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signed short bv = cpu.asregs.regs[b];
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TRACE("sex.s");
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cpu.asregs.regs[a] = (int) bv;
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}
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@ -609,6 +626,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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signed char bv = cpu.asregs.regs[b];
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TRACE("zex.b");
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cpu.asregs.regs[a] = (int) bv & 0xff;
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}
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@ -618,6 +636,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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signed short bv = cpu.asregs.regs[b];
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TRACE("zex.s");
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cpu.asregs.regs[a] = (int) bv & 0xffff;
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}
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@ -628,9 +647,10 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("mul.x");
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signed long long r =
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(signed long long) av * (signed long long) bv;
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TRACE("mul.x");
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cpu.asregs.regs[a] = r >> 32;
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}
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break;
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@ -640,9 +660,10 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("umul.x");
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unsigned long long r =
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(unsigned long long) av * (unsigned long long) bv;
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TRACE("umul.x");
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cpu.asregs.regs[a] = r >> 32;
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}
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break;
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@ -682,6 +703,7 @@ sim_resume (sd, step, siggnal)
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case 0x1a: /* jmpa */
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{
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unsigned int tgt = EXTRACT_WORD(pc+2);
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TRACE("jmpa");
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pc = tgt - 2;
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}
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@ -689,8 +711,8 @@ sim_resume (sd, step, siggnal)
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case 0x1b: /* ldi.b (immediate) */
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int val = EXTRACT_WORD(pc+2);
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TRACE("ldi.b");
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cpu.asregs.regs[reg] = val;
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pc += 4;
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@ -701,6 +723,7 @@ sim_resume (sd, step, siggnal)
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int src = inst & 0xf;
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int dest = (inst >> 4) & 0xf;
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int xv;
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TRACE("ld.b");
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xv = cpu.asregs.regs[src];
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cpu.asregs.regs[dest] = rbat (scpu, opc, xv);
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@ -710,6 +733,7 @@ sim_resume (sd, step, siggnal)
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("lda.b");
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cpu.asregs.regs[reg] = rbat (scpu, opc, addr);
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pc += 4;
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@ -719,6 +743,7 @@ sim_resume (sd, step, siggnal)
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{
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int dest = (inst >> 4) & 0xf;
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int val = inst & 0xf;
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TRACE("st.b");
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wbat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
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}
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@ -727,6 +752,7 @@ sim_resume (sd, step, siggnal)
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("sta.b");
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wbat (scpu, opc, addr, cpu.asregs.regs[reg]);
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pc += 4;
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@ -737,6 +763,7 @@ sim_resume (sd, step, siggnal)
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int reg = (inst >> 4) & 0xf;
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unsigned int val = EXTRACT_WORD(pc+2);
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TRACE("ldi.s");
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cpu.asregs.regs[reg] = val;
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pc += 4;
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@ -747,6 +774,7 @@ sim_resume (sd, step, siggnal)
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int src = inst & 0xf;
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int dest = (inst >> 4) & 0xf;
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int xv;
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TRACE("ld.s");
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xv = cpu.asregs.regs[src];
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cpu.asregs.regs[dest] = rsat (scpu, opc, xv);
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@ -756,6 +784,7 @@ sim_resume (sd, step, siggnal)
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("lda.s");
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cpu.asregs.regs[reg] = rsat (scpu, opc, addr);
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pc += 4;
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@ -765,6 +794,7 @@ sim_resume (sd, step, siggnal)
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{
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int dest = (inst >> 4) & 0xf;
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int val = inst & 0xf;
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TRACE("st.s");
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wsat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
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}
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@ -773,6 +803,7 @@ sim_resume (sd, step, siggnal)
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("sta.s");
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wsat (scpu, opc, addr, cpu.asregs.regs[reg]);
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pc += 4;
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@ -781,6 +812,7 @@ sim_resume (sd, step, siggnal)
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case 0x25: /* jmp */
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{
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int reg = (inst >> 4) & 0xf;
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TRACE("jmp");
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pc = cpu.asregs.regs[reg] - 2;
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}
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@ -790,6 +822,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int av, bv;
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TRACE("and");
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av = cpu.asregs.regs[a];
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bv = cpu.asregs.regs[b];
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@ -802,6 +835,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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int av = cpu.asregs.regs[a];
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int bv = cpu.asregs.regs[b];
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TRACE("lshr");
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cpu.asregs.regs[a] = (unsigned) ((unsigned) av >> bv);
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}
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@ -812,6 +846,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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int av = cpu.asregs.regs[a];
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int bv = cpu.asregs.regs[b];
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TRACE("ashl");
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cpu.asregs.regs[a] = av << bv;
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}
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@ -822,6 +857,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("sub.l");
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cpu.asregs.regs[a] = av - bv;
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}
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@ -831,6 +867,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int bv = cpu.asregs.regs[b];
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TRACE("neg");
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cpu.asregs.regs[a] = - bv;
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}
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@ -840,6 +877,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int av, bv;
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TRACE("or");
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av = cpu.asregs.regs[a];
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bv = cpu.asregs.regs[b];
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@ -851,6 +889,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int bv = cpu.asregs.regs[b];
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TRACE("not");
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cpu.asregs.regs[a] = 0xffffffff ^ bv;
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}
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@ -861,6 +900,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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int av = cpu.asregs.regs[a];
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int bv = cpu.asregs.regs[b];
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TRACE("ashr");
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cpu.asregs.regs[a] = av >> bv;
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}
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@ -870,6 +910,7 @@ sim_resume (sd, step, siggnal)
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int av, bv;
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TRACE("xor");
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av = cpu.asregs.regs[a];
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bv = cpu.asregs.regs[b];
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@ -882,6 +923,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("mul.l");
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cpu.asregs.regs[a] = av * bv;
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}
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@ -889,6 +931,7 @@ sim_resume (sd, step, siggnal)
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case 0x30: /* swi */
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{
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unsigned int inum = EXTRACT_WORD(pc+2);
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TRACE("swi");
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/* Set the special registers appropriately. */
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cpu.asregs.sregs[2] = 3; /* MOXIE_EX_SWI */
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@ -969,6 +1012,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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int av = cpu.asregs.regs[a];
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int bv = cpu.asregs.regs[b];
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TRACE("div.l");
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cpu.asregs.regs[a] = av / bv;
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}
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@ -979,6 +1023,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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unsigned int av = cpu.asregs.regs[a];
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unsigned int bv = cpu.asregs.regs[b];
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TRACE("udiv.l");
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cpu.asregs.regs[a] = (av / bv);
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}
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@ -989,6 +1034,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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int av = cpu.asregs.regs[a];
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int bv = cpu.asregs.regs[b];
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TRACE("mod.l");
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cpu.asregs.regs[a] = av % bv;
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}
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@ -999,6 +1045,7 @@ sim_resume (sd, step, siggnal)
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int b = inst & 0xf;
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unsigned int av = cpu.asregs.regs[a];
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unsigned int bv = cpu.asregs.regs[b];
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TRACE("umod.l");
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cpu.asregs.regs[a] = (av % bv);
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}
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@ -1013,6 +1060,7 @@ sim_resume (sd, step, siggnal)
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unsigned int addr = EXTRACT_WORD(pc+2);
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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TRACE("ldo.b");
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addr += cpu.asregs.regs[b];
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cpu.asregs.regs[a] = rbat (scpu, opc, addr);
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@ -1024,6 +1072,7 @@ sim_resume (sd, step, siggnal)
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unsigned int addr = EXTRACT_WORD(pc+2);
|
||||
int a = (inst >> 4) & 0xf;
|
||||
int b = inst & 0xf;
|
||||
|
||||
TRACE("sto.b");
|
||||
addr += cpu.asregs.regs[a];
|
||||
wbat (scpu, opc, addr, cpu.asregs.regs[b]);
|
||||
|
|
@ -1035,6 +1084,7 @@ sim_resume (sd, step, siggnal)
|
|||
unsigned int addr = EXTRACT_WORD(pc+2);
|
||||
int a = (inst >> 4) & 0xf;
|
||||
int b = inst & 0xf;
|
||||
|
||||
TRACE("ldo.s");
|
||||
addr += cpu.asregs.regs[b];
|
||||
cpu.asregs.regs[a] = rsat (scpu, opc, addr);
|
||||
|
|
@ -1046,6 +1096,7 @@ sim_resume (sd, step, siggnal)
|
|||
unsigned int addr = EXTRACT_WORD(pc+2);
|
||||
int a = (inst >> 4) & 0xf;
|
||||
int b = inst & 0xf;
|
||||
|
||||
TRACE("sto.s");
|
||||
addr += cpu.asregs.regs[a];
|
||||
wsat (scpu, opc, addr, cpu.asregs.regs[b]);
|
||||
|
|
|
|||
Loading…
Reference in a new issue